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Searched refs:phy_clk (Results 1 – 9 of 9) sorted by relevance

/f-stack/freebsd/mips/ingenic/
H A Djz4780_dwc_fdt.c63 clk_t phy_clk; member
76 err = clk_get_by_ofw_name(dev, 0, "otg_phy", &sc->phy_clk); in jz4780_dwc_otg_clk_enable()
81 err = clk_set_freq(sc->phy_clk, 48000000, 0); in jz4780_dwc_otg_clk_enable()
87 err = clk_enable(sc->phy_clk); in jz4780_dwc_otg_clk_enable()
99 err = clk_enable(sc->phy_clk); in jz4780_dwc_otg_clk_enable()
164 if (sc->phy_clk) in jz4780_dwc_otg_attach()
165 clk_release(sc->phy_clk); in jz4780_dwc_otg_attach()
182 if (sc->phy_clk) in jz4780_dwc_otg_detach()
183 clk_release(sc->phy_clk); in jz4780_dwc_otg_detach()
H A Djz4780_clock.c645 clk_t phy_clk, ext_clk; in jz4780_ehci_clk_config() local
649 phy_clk = NULL; in jz4780_ehci_clk_config()
655 &phy_clk) != 0) in jz4780_ehci_clk_config()
657 if (clk_get_parent(phy_clk, &ext_clk) != 0) in jz4780_ehci_clk_config()
661 if (clk_set_freq(phy_clk, phy_freq, 0) != 0) in jz4780_ehci_clk_config()
666 clk_release(phy_clk); in jz4780_ehci_clk_config()
/f-stack/freebsd/contrib/device-tree/Bindings/ufs/
H A Dcdns,ufshc.txt22 the "phy_clk" clock can also be added, if needed.
31 clock-names = "core_clk", "phy_clk";
H A Dufs-hisi.txt16 order as the clocks property. "ref_clk", "phy_clk" is optional
37 clock-names = "ref_clk", "phy_clk";
H A Dufshcd-pltfrm.txt80 clock-names = "core_clk", "ref_clk", "phy_clk", "iface_clk";
/f-stack/freebsd/contrib/device-tree/Bindings/phy/
H A Dphy-cadence-sierra.txt22 the clock to the lanes. "phy_clk" is deprecated.
54 clock-names = "phy_clk";
/f-stack/freebsd/contrib/device-tree/src/arm64/hisilicon/
H A Dhi3670.dtsi669 clock-names = "ref_clk", "phy_clk";
H A Dhi3660.dtsi1047 clock-names = "ref_clk", "phy_clk";
/f-stack/freebsd/contrib/device-tree/src/arm64/ti/
H A Dk3-j721e-main.dtsi1022 clock-names = "core_clk", "phy_clk", "ref_clk";