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Searched refs:phase (Results 1 – 25 of 104) sorted by relevance

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/f-stack/freebsd/contrib/zstd/lib/compress/
H A Dzstd_cwksp.h152 ZSTD_cwksp_alloc_phase_e phase; member
203 assert(phase >= ws->phase); in ZSTD_cwksp_internal_advance_phase()
204 if (phase > ws->phase) { in ZSTD_cwksp_internal_advance_phase()
205 if (ws->phase < ZSTD_cwksp_alloc_buffers && in ZSTD_cwksp_internal_advance_phase()
209 if (ws->phase < ZSTD_cwksp_alloc_aligned && in ZSTD_cwksp_internal_advance_phase()
223 ws->phase = phase; in ZSTD_cwksp_internal_advance_phase()
241 ZSTD_cwksp_internal_advance_phase(ws, phase); in ZSTD_cwksp_reserve_internal()
307 ZSTD_cwksp_internal_advance_phase(ws, phase); in ZSTD_cwksp_reserve_table()
464 if (ws->phase > ZSTD_cwksp_alloc_buffers) { in ZSTD_cwksp_clear()
465 ws->phase = ZSTD_cwksp_alloc_buffers; in ZSTD_cwksp_clear()
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/f-stack/freebsd/kern/
H A Dkern_poll.c239 static uint32_t phase; variable
317 phase = 0; in hardclock_device_poll()
320 if (phase <= 2) { in hardclock_device_poll()
321 if (phase != 0) in hardclock_device_poll()
323 phase = 1; in hardclock_device_poll()
327 phase = 2; in hardclock_device_poll()
388 phase = 5; in netisr_pollmore()
412 phase = 0; in netisr_pollmore()
425 phase = 6; in netisr_pollmore()
450 phase = 3; in netisr_poll()
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H A Dsubr_vmem.c971 start = VMEM_ALIGNUP(start - phase, align) + phase; in vmem_fit()
976 start = VMEM_ALIGNUP(start - phase, nocross) + phase; in vmem_fit()
979 MPASS((start & (align - 1)) == phase); in vmem_fit()
1139 (error = vmem_fit(bt, size, align, phase, nocross, in vmem_xalloc_nextfit()
1164 (error = vmem_fit(prev, size, align, phase, nocross, in vmem_xalloc_nextfit()
1356 const vmem_size_t phase, const vmem_size_t nocross, in vmem_xalloc() argument
1378 MPASS((phase & vm->vm_quantum_mask) == 0); in vmem_xalloc()
1381 MPASS((align == 0 && phase == 0) || phase < align); in vmem_xalloc()
1384 MPASS(!VMEM_CROSS_P(phase, phase + size - 1, nocross)); in vmem_xalloc()
1396 return (vmem_xalloc_nextfit(vm, size0, align, phase, nocross, in vmem_xalloc()
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/f-stack/freebsd/contrib/device-tree/Bindings/mmc/
H A Dexynos-dw-mshc.txt30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
36 in transmit mode and CIU clock phase shift value in receive mode for double
39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
45 - First Cell: CIU clock phase shift value for tx mode.
46 - Second Cell: CIU clock phase shift value for rx mode.
49 - valid value for tx phase shift and rx phase shift is 0 to 7.
50 - when CIU clock divider value is set to 3, all possible 8 phase shift
53 phase shift clocks should be 0.
H A Dhi3798cv200-dw-mshc.txt19 "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling.
20 "ciu-drive" - Hi3798CV200 extended phase clock for ciu driving.
/f-stack/freebsd/contrib/openzfs/tests/zfs-tests/cmd/xattrtest/
H A Dxattrtest.c95 static int phase = PHASE_ALL; variable
192 phase = strtol(optarg, NULL, 0); in parse_args()
193 if (phase <= PHASE_ALL || phase >= PHASE_INVAL) { in parse_args()
226 fprintf(stdout, "only: %d\n", phase); in parse_args()
296 post_hook(char *phase) in post_hook() argument
298 char *argv[3] = { script, phase, (char *)0 }; in post_hook()
693 if (phase == PHASE_ALL || phase == PHASE_CREATE) { in main()
699 if (phase == PHASE_ALL || phase == PHASE_SETXATTR) { in main()
705 if (phase == PHASE_ALL || phase == PHASE_GETXATTR) { in main()
711 if (!keep_files && (phase == PHASE_ALL || phase == PHASE_UNLINK)) { in main()
/f-stack/freebsd/contrib/device-tree/Bindings/leds/backlight/
H A Dsky81452-backlight.txt14 - skyworks,phase-shift : Enable phase shift mode
27 skyworks,phase-shift;
/f-stack/freebsd/contrib/device-tree/Bindings/sound/
H A Dmax98504.txt20 applied during the "attack hold" and "timed hold" phase, the value must be
22 - maxim,brownout-attack-hold-ms - the brownout attack hold phase time in ms,
24 - maxim,brownout-timed-hold-ms - the brownout timed hold phase time in ms,
26 - maxim,brownout-release-rate-ms - the brownout release phase step time in ms,
/f-stack/tools/libxo/xolint/
H A Dxolint.pl246 my $phase = 0;
269 $phase = 0;
271 } elsif ($phase == 0 && $ch eq ":") {
272 $phase += 1;
275 $phase += 1;
290 $build[$phase] .= $ch;
/f-stack/freebsd/contrib/device-tree/Bindings/mfd/
H A Daxp20x.txt126 DCDC2 : DC-DC buck : vin2-supply : poly-phase capable
127 DCDC3 : DC-DC buck : vin3-supply : poly-phase capable
129 DCDC5 : DC-DC buck : vin5-supply : poly-phase capable
130 DCDC6 : DC-DC buck : vin6-supply : poly-phase capable
153 DCDCA : DC-DC buck : vina-supply : poly-phase capable
154 DCDCB : DC-DC buck : vinb-supply : poly-phase capable
155 DCDCC : DC-DC buck : vinc-supply : poly-phase capable
156 DCDCD : DC-DC buck : vind-supply : poly-phase capable
157 DCDCE : DC-DC buck : vine-supply : poly-phase capable
202 DCDC2 : DC-DC buck : vin2-supply : poly-phase capable
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/power/supply/
H A Drohm,bd99954.yaml35 # First a constant current (5) phase (CC)
36 # Then constant voltage (CV) phase (after the battery voltage has reached
70 # Current used at trickle-charge phase (8 in above chart)
75 # Current used at pre-charge phase (6 in above chart)
80 # Current used at fast charge constant current phase (5 in above chart)
85 # The constant voltage used in fast charging phase (4 in above chart)
/f-stack/freebsd/contrib/openzfs/include/os/freebsd/spl/sys/
H A Dsysmacros.h231 #define P2PHASEUP(x, align, phase) ((phase) - (((phase) - (x)) & -(align))) argument
270 #define P2PHASEUP_TYPED(x, align, phase, type) \ argument
271 ((type)(phase) - (((type)(phase) - (type)(x)) & -(type)(align)))
H A Dccompile.h268 #define P2PHASEUP_TYPED(x, align, phase, type) \ argument
269 ((type)(phase) - (((type)(phase) - (type)(x)) & -(type)(align)))
/f-stack/freebsd/contrib/openzfs/lib/libspl/include/os/linux/sys/
H A Dsysmacros.h88 #define P2PHASEUP_TYPED(x, align, phase, type) \ argument
89 ((type)(phase) - (((type)(phase) - (type)(x)) & -(type)(align)))
/f-stack/freebsd/contrib/device-tree/Bindings/clock/
H A Daltr_socfpga.txt26 - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
28 value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
/f-stack/freebsd/contrib/device-tree/Bindings/spi/
H A Dspi-samsung.txt61 - samsung,spi-feedback-delay: The sampling phase shift to be applied on the
65 - 0: No phase shift.
66 - 1: 90 degree phase shift sampling.
67 - 2: 180 degree phase shift sampling.
68 - 3: 270 degree phase shift sampling.
/f-stack/freebsd/crypto/openssl/arm/
H A Dghashv8-armx.S42 .byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase
48 vext.8 q10,q0,q0,#8 @ 2nd phase
81 .byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase of reduction
87 vext.8 q10,q0,q0,#8 @ 2nd phase of reduction
171 .byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase of reduction
184 vext.8 q10,q0,q0,#8 @ 2nd phase of reduction
211 .byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase of reduction
217 vext.8 q10,q0,q0,#8 @ 2nd phase of reduction
/f-stack/freebsd/contrib/device-tree/Bindings/regulator/
H A Dmps,mpq7920.yaml60 mps,buck-phase-delay:
64 defines the phase delay of this buck, must be one of the following
104 mps,buck-phase-delay = /bits/ 8 <2>;
/f-stack/freebsd/contrib/device-tree/Bindings/memory-controllers/
H A Dst,stm32-fmc2-ebi.yaml132 phase in nanoseconds used for asynchronous read/write transactions.
136 phase in nanoseconds used for asynchronous multiplexed read/write
140 description: This property defines the duration of the data setup phase
148 description: This property defines the duration of the data hold phase
161 phase in nanoseconds used for asynchronous write transactions.
165 phase in nanoseconds used for asynchronous multiplexed write
170 phase in nanoseconds used for asynchronous write transactions.
177 description: This property defines the duration of the data hold phase
/f-stack/freebsd/contrib/openzfs/include/os/linux/spl/sys/
H A Dsysmacros.h185 #define P2PHASEUP_TYPED(x, align, phase, type) \ argument
186 ((type)(phase) - (((type)(phase) - (type)(x)) & -(type)(align)))
/f-stack/dpdk/drivers/net/ena/base/
H A Dena_eth_com.c16 expected_phase = io_cq->phase; in ena_com_get_next_rx_cdesc()
83 io_sq->phase ^= 1; in ena_com_write_bounce_buffer_to_dev()
214 io_sq->phase ^= 1; in ena_com_sq_update_tail()
291 meta_desc->len_ctrl |= ((u32)io_sq->phase << in ena_com_create_meta()
440 desc->len_ctrl |= ((u32)io_sq->phase << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) & in ena_com_prepare_tx()
494 desc->len_ctrl |= ((u32)io_sq->phase << in ena_com_prepare_tx()
605 (io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK) | in ena_com_add_single_rx_desc()
H A Dena_com.h123 u8 phase; member
168 u8 phase; member
180 u8 phase; member
192 u8 phase; member
239 u8 phase; member
/f-stack/freebsd/contrib/ena-com/
H A Dena_eth_com.c44 expected_phase = io_cq->phase; in ena_com_get_next_rx_cdesc()
113 io_sq->phase ^= 1; in ena_com_write_bounce_buffer_to_dev()
249 io_sq->phase ^= 1; in ena_com_sq_update_tail()
327 meta_desc->len_ctrl |= ((u32)io_sq->phase << in ena_com_create_meta()
485 desc->len_ctrl |= ((u32)io_sq->phase << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) & in ena_com_prepare_tx()
540 desc->len_ctrl |= ((u32)io_sq->phase << in ena_com_prepare_tx()
661 (io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK); in ena_com_add_single_rx_desc()
H A Dena_com.h151 u8 phase; member
196 u8 phase; member
208 u8 phase; member
220 u8 phase; member
267 u8 phase; member
/f-stack/freebsd/contrib/octeon-sdk/
H A Dcvmx-smix-defs.h233 uint64_t phase : 8; /**< MDC Clock Phase member
237 uint64_t phase : 8;
271 uint64_t phase : 8; /**< MDC Clock Phase member
275 uint64_t phase : 8;

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