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/f-stack/freebsd/contrib/device-tree/Bindings/pinctrl/
H A Drenesas,pfc-pinctrl.txt13 - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
16 - "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller.
17 - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
18 - "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller.
19 - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
20 - "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller.
88 (drivers/pinctrl/sh-pfc/pfc-*.c)
127 pfc: pin-controller@e6050000 {
128 compatible = "renesas,pfc-sh73a0";
151 gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
[all …]
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Dr8a7740-armadillo800eva.dts49 gpio = <&pfc 75 GPIO_ACTIVE_HIGH>;
62 gpios = <&pfc 17 GPIO_ACTIVE_HIGH>;
81 gpios = <&pfc 99 GPIO_ACTIVE_LOW>;
88 gpios = <&pfc 100 GPIO_ACTIVE_LOW>;
94 gpios = <&pfc 97 GPIO_ACTIVE_LOW>;
100 gpios = <&pfc 98 GPIO_ACTIVE_LOW>;
109 gpios = <&pfc 102 GPIO_ACTIVE_HIGH>;
113 gpios = <&pfc 111 GPIO_ACTIVE_HIGH>;
117 gpios = <&pfc 110 GPIO_ACTIVE_HIGH>;
203 gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
[all …]
H A Dr8a73a4-ape6evm.dts51 gpio = <&pfc 76 GPIO_ACTIVE_HIGH>;
75 gpios = <&pfc 28 GPIO_ACTIVE_HIGH>;
79 gpios = <&pfc 126 GPIO_ACTIVE_HIGH>;
83 gpios = <&pfc 132 GPIO_ACTIVE_HIGH>;
107 gpios = <&pfc 324 GPIO_ACTIVE_LOW>;
114 gpios = <&pfc 325 GPIO_ACTIVE_LOW>;
120 gpios = <&pfc 326 GPIO_ACTIVE_LOW>;
126 gpios = <&pfc 327 GPIO_ACTIVE_LOW>;
132 gpios = <&pfc 328 GPIO_ACTIVE_LOW>;
138 gpios = <&pfc 329 GPIO_ACTIVE_LOW>;
[all …]
H A Demev2.dtsi198 pfc: pin-controller@e0140200 { label
199 compatible = "renesas,pfc-emev2";
209 gpio-ranges = <&pfc 0 0 32>;
222 gpio-ranges = <&pfc 0 32 32>;
235 gpio-ranges = <&pfc 0 64 32>;
248 gpio-ranges = <&pfc 0 96 32>;
261 gpio-ranges = <&pfc 0 128 31>;
H A Dsh73a0-kzm9g.dts68 gpio = <&pfc 15 GPIO_ACTIVE_HIGH>;
77 gpio = <&pfc 14 GPIO_ACTIVE_HIGH>;
84 gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
88 gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
92 gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
96 gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
148 gpios = <&pfc 159 GPIO_ACTIVE_LOW>;
331 &pfc {
H A Dr8a73a4.dtsi224 pfc: pin-controller@e6050000 { label
225 compatible = "renesas,pfc-r8a73a4";
230 <&pfc 0 0 31>, <&pfc 32 32 9>,
231 <&pfc 64 64 22>, <&pfc 96 96 31>,
232 <&pfc 128 128 7>, <&pfc 160 160 19>,
233 <&pfc 192 192 31>, <&pfc 224 224 27>,
234 <&pfc 256 256 28>, <&pfc 288 288 21>,
235 <&pfc 320 320 10>;
H A Dr8a7792.dtsi126 gpio-ranges = <&pfc 0 0 29>;
141 gpio-ranges = <&pfc 0 32 23>;
156 gpio-ranges = <&pfc 0 64 32>;
171 gpio-ranges = <&pfc 0 96 28>;
186 gpio-ranges = <&pfc 0 128 17>;
201 gpio-ranges = <&pfc 0 160 17>;
216 gpio-ranges = <&pfc 0 192 17>;
231 gpio-ranges = <&pfc 0 224 17>;
246 gpio-ranges = <&pfc 0 256 17>;
261 gpio-ranges = <&pfc 0 288 17>;
[all …]
H A Dr8a7779.dtsi93 gpio-ranges = <&pfc 0 0 32>;
104 gpio-ranges = <&pfc 0 32 32>;
115 gpio-ranges = <&pfc 0 64 32>;
126 gpio-ranges = <&pfc 0 96 32>;
137 gpio-ranges = <&pfc 0 128 32>;
148 gpio-ranges = <&pfc 0 160 32>;
159 gpio-ranges = <&pfc 0 192 9>;
324 pfc: pin-controller@fffc0000 { label
325 compatible = "renesas,pfc-r8a7779";
H A Dr8a7778.dtsi96 gpio-ranges = <&pfc 0 0 32>;
107 gpio-ranges = <&pfc 0 32 32>;
118 gpio-ranges = <&pfc 0 64 32>;
129 gpio-ranges = <&pfc 0 96 32>;
140 gpio-ranges = <&pfc 0 128 27>;
145 pfc: pin-controller@fffc0000 { label
146 compatible = "renesas,pfc-r8a7778";
H A Dr8a7742-iwg21m.dtsi38 &pfc {
H A Dr8a7745-sk-rzg1e.dts34 &pfc {
H A Dr8a7743-sk-rzg1m.dts39 &pfc {
H A Dr8a7744-iwg20m.dtsi33 &pfc {
/f-stack/dpdk/drivers/net/qede/base/
H A Decore_dcbx.c507 p_params->pfc.willing = GET_MFW_FIELD(pfc, DCBX_PFC_WILLING); in ecore_dcbx_get_pfc_data()
508 p_params->pfc.max_tc = GET_MFW_FIELD(pfc, DCBX_PFC_CAPS); in ecore_dcbx_get_pfc_data()
509 p_params->pfc.enabled = GET_MFW_FIELD(pfc, DCBX_PFC_ENABLED); in ecore_dcbx_get_pfc_data()
522 p_params->pfc.willing, pfc_map, p_params->pfc.max_tc, in ecore_dcbx_get_pfc_data()
523 p_params->pfc.enabled); in ecore_dcbx_get_pfc_data()
1011 if (p_params->pfc.willing) in ecore_dcbx_set_pfc_data()
1012 *pfc |= DCBX_PFC_WILLING_MASK; in ecore_dcbx_set_pfc_data()
1016 if (p_params->pfc.enabled) in ecore_dcbx_set_pfc_data()
1021 *pfc &= ~DCBX_PFC_CAPS_MASK; in ecore_dcbx_set_pfc_data()
1022 *pfc |= (u32)p_params->pfc.max_tc << DCBX_PFC_CAPS_OFFSET; in ecore_dcbx_set_pfc_data()
[all …]
/f-stack/freebsd/contrib/octeon-sdk/
H A Dcvmx-profiler.c220 uint64_t pfc; in cvmx_reset_perf_counter() local
221 pfc = (1ull << 63) - events; in cvmx_reset_perf_counter()
224 CVMX_MT_COP0(pfc, COP0_PERFVALUE0); in cvmx_reset_perf_counter()
226 CVMX_MT_COP0(pfc, COP0_PERFVALUE1); in cvmx_reset_perf_counter()
/f-stack/dpdk/drivers/net/i40e/base/
H A Di40e_dcb.c180 dcbcfg->pfc.pfcenable = buf[1]; in i40e_parse_ieee_pfccfg_tlv()
338 dcbcfg->pfc.willing = 1; in i40e_parse_cee_pfccfg_tlv()
345 dcbcfg->pfc.pfcenable = buf[0]; in i40e_parse_cee_pfccfg_tlv()
346 dcbcfg->pfc.pfccap = buf[1]; in i40e_parse_cee_pfccfg_tlv()
629 dcbcfg->pfc.pfcenable = cee_cfg->oper_pfc_en; in i40e_cee_to_dcb_v1_config()
630 dcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS; in i40e_cee_to_dcb_v1_config()
711 dcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS; in i40e_cee_to_dcb_config()
1145 if (dcbcfg->pfc.willing) in i40e_add_ieee_pfc_tlv()
1148 if (dcbcfg->pfc.mbc) in i40e_add_ieee_pfc_tlv()
1151 buf[0] |= dcbcfg->pfc.pfccap & 0xF; in i40e_add_ieee_pfc_tlv()
[all …]
/f-stack/dpdk/drivers/net/ice/base/
H A Dice_dcb.c273 dcbcfg->pfc.pfccap = ((buf[0] & ICE_IEEE_PFC_CAP_M) >> in ice_parse_ieee_pfccfg_tlv()
275 dcbcfg->pfc.pfcena = buf[1]; in ice_parse_ieee_pfccfg_tlv()
442 dcbcfg->pfc.willing = 1; in ice_parse_cee_pfccfg_tlv()
449 dcbcfg->pfc.pfcena = buf[0]; in ice_parse_cee_pfccfg_tlv()
450 dcbcfg->pfc.pfccap = buf[1]; in ice_parse_cee_pfccfg_tlv()
789 dcbcfg->pfc.pfcena = cee_cfg->oper_pfc_en; in ice_cee_to_dcb_cfg()
790 dcbcfg->pfc.pfccap = ICE_MAX_TRAFFIC_CLASS; in ice_cee_to_dcb_cfg()
1148 if (dcbcfg->pfc.willing) in ice_add_ieee_pfc_tlv()
1151 if (dcbcfg->pfc.mbc) in ice_add_ieee_pfc_tlv()
1154 buf[0] |= dcbcfg->pfc.pfccap & 0xF; in ice_add_ieee_pfc_tlv()
[all …]
/f-stack/freebsd/contrib/device-tree/src/arm64/renesas/
H A Dhihope-rzg2-ex-lvds.dtsi40 &pfc {
H A Dcat875.dtsi48 &pfc {
H A Dhihope-rzg2-ex.dtsi50 &pfc {
H A Dr8a77995.dtsi93 gpio-ranges = <&pfc 0 0 9>;
108 gpio-ranges = <&pfc 0 32 32>;
123 gpio-ranges = <&pfc 0 64 32>;
138 gpio-ranges = <&pfc 0 96 10>;
153 gpio-ranges = <&pfc 0 128 32>;
168 gpio-ranges = <&pfc 0 160 21>;
183 gpio-ranges = <&pfc 0 192 14>;
191 pfc: pin-controller@e6060000 { label
192 compatible = "renesas,pfc-r8a77995";
H A Dhihope-rev2.dtsi59 &pfc {
/f-stack/dpdk/doc/guides/sample_app_ug/
H A Dqos_scheduler.rst64 * --pfc "RX PORT, TX PORT, RX LCORE, WT LCORE, TX CORE": Packet flow configuration.
65 Multiple pfc entities can be configured in the command line,
98 * --msz M: Mempool size (in number of mbufs) for each pfc (default 2097152)
322 ./<build_dir>/examples/dpdk-qos_sched -l 1,5,7 -n 4 -- --pfc "3,2,5,7" --cfg ./profile.cfg
331 …./<build_dir>/examples/dpdk-qos_sched -l 1,2,6,7 -n 4 -- --pfc "3,2,2,6,7" --pfc "1,0,2,6,7" --cfg…
/f-stack/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_dcb.h63 enum txgbe_dcb_pfc pfc; /* Class based flow control setting */ member
/f-stack/freebsd/contrib/device-tree/Bindings/gpio/
H A Drenesas,em-gio.yaml66 gpio-ranges = <&pfc 0 0 32>;

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