1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
4 */
5
6 #include "axgbe_ethdev.h"
7 #include "axgbe_common.h"
8 #include "axgbe_phy.h"
9
10 #define AXGBE_PHY_PORT_SPEED_100 BIT(0)
11 #define AXGBE_PHY_PORT_SPEED_1000 BIT(1)
12 #define AXGBE_PHY_PORT_SPEED_2500 BIT(2)
13 #define AXGBE_PHY_PORT_SPEED_10000 BIT(3)
14
15 #define AXGBE_MUTEX_RELEASE 0x80000000
16
17 #define AXGBE_SFP_DIRECT 7
18
19 /* I2C target addresses */
20 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50
21 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51
22 #define AXGBE_SFP_PHY_ADDRESS 0x56
23 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20
24
25 /* SFP sideband signal indicators */
26 #define AXGBE_GPIO_NO_TX_FAULT BIT(0)
27 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1)
28 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2)
29 #define AXGBE_GPIO_NO_RX_LOS BIT(3)
30
31 /* Rate-change complete wait/retry count */
32 #define AXGBE_RATECHANGE_COUNT 500
33
34 /* CDR delay values for KR support (in usec) */
35 #define AXGBE_CDR_DELAY_INIT 10000
36 #define AXGBE_CDR_DELAY_INC 10000
37 #define AXGBE_CDR_DELAY_MAX 100000
38
39 enum axgbe_port_mode {
40 AXGBE_PORT_MODE_RSVD = 0,
41 AXGBE_PORT_MODE_BACKPLANE,
42 AXGBE_PORT_MODE_BACKPLANE_2500,
43 AXGBE_PORT_MODE_1000BASE_T,
44 AXGBE_PORT_MODE_1000BASE_X,
45 AXGBE_PORT_MODE_NBASE_T,
46 AXGBE_PORT_MODE_10GBASE_T,
47 AXGBE_PORT_MODE_10GBASE_R,
48 AXGBE_PORT_MODE_SFP,
49 AXGBE_PORT_MODE_MAX,
50 };
51
52 enum axgbe_conn_type {
53 AXGBE_CONN_TYPE_NONE = 0,
54 AXGBE_CONN_TYPE_SFP,
55 AXGBE_CONN_TYPE_MDIO,
56 AXGBE_CONN_TYPE_RSVD1,
57 AXGBE_CONN_TYPE_BACKPLANE,
58 AXGBE_CONN_TYPE_MAX,
59 };
60
61 /* SFP/SFP+ related definitions */
62 enum axgbe_sfp_comm {
63 AXGBE_SFP_COMM_DIRECT = 0,
64 AXGBE_SFP_COMM_PCA9545,
65 };
66
67 enum axgbe_sfp_cable {
68 AXGBE_SFP_CABLE_UNKNOWN = 0,
69 AXGBE_SFP_CABLE_ACTIVE,
70 AXGBE_SFP_CABLE_PASSIVE,
71 };
72
73 enum axgbe_sfp_base {
74 AXGBE_SFP_BASE_UNKNOWN = 0,
75 AXGBE_SFP_BASE_1000_T,
76 AXGBE_SFP_BASE_1000_SX,
77 AXGBE_SFP_BASE_1000_LX,
78 AXGBE_SFP_BASE_1000_CX,
79 AXGBE_SFP_BASE_10000_SR,
80 AXGBE_SFP_BASE_10000_LR,
81 AXGBE_SFP_BASE_10000_LRM,
82 AXGBE_SFP_BASE_10000_ER,
83 AXGBE_SFP_BASE_10000_CR,
84 };
85
86 enum axgbe_sfp_speed {
87 AXGBE_SFP_SPEED_UNKNOWN = 0,
88 AXGBE_SFP_SPEED_100_1000,
89 AXGBE_SFP_SPEED_1000,
90 AXGBE_SFP_SPEED_10000,
91 };
92
93 /* SFP Serial ID Base ID values relative to an offset of 0 */
94 #define AXGBE_SFP_BASE_ID 0
95 #define AXGBE_SFP_ID_SFP 0x03
96
97 #define AXGBE_SFP_BASE_EXT_ID 1
98 #define AXGBE_SFP_EXT_ID_SFP 0x04
99
100 #define AXGBE_SFP_BASE_10GBE_CC 3
101 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4)
102 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5)
103 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
104 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7)
105
106 #define AXGBE_SFP_BASE_1GBE_CC 6
107 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0)
108 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1)
109 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2)
110 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3)
111
112 #define AXGBE_SFP_BASE_CABLE 8
113 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
114 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
115
116 #define AXGBE_SFP_BASE_BR 12
117 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a
118 #define AXGBE_SFP_BASE_BR_1GBE_MAX 0x0d
119 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64
120 #define AXGBE_SFP_BASE_BR_10GBE_MAX 0x68
121
122 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18
123
124 #define AXGBE_SFP_BASE_VENDOR_NAME 20
125 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16
126 #define AXGBE_SFP_BASE_VENDOR_PN 40
127 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16
128 #define AXGBE_SFP_BASE_VENDOR_REV 56
129 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4
130
131 #define AXGBE_SFP_BASE_CC 63
132
133 /* SFP Serial ID Extended ID values relative to an offset of 64 */
134 #define AXGBE_SFP_BASE_VENDOR_SN 4
135 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16
136
137 #define AXGBE_SFP_EXTD_DIAG 28
138 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
139
140 #define AXGBE_SFP_EXTD_SFF_8472 30
141
142 #define AXGBE_SFP_EXTD_CC 31
143
144 struct axgbe_sfp_eeprom {
145 u8 base[64];
146 u8 extd[32];
147 u8 vendor[32];
148 };
149
150 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE"
151 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06"
152
153 struct axgbe_sfp_ascii {
154 union {
155 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
156 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1];
157 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1];
158 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1];
159 } u;
160 };
161
162 /* MDIO PHY reset types */
163 enum axgbe_mdio_reset {
164 AXGBE_MDIO_RESET_NONE = 0,
165 AXGBE_MDIO_RESET_I2C_GPIO,
166 AXGBE_MDIO_RESET_INT_GPIO,
167 AXGBE_MDIO_RESET_MAX,
168 };
169
170 /* Re-driver related definitions */
171 enum axgbe_phy_redrv_if {
172 AXGBE_PHY_REDRV_IF_MDIO = 0,
173 AXGBE_PHY_REDRV_IF_I2C,
174 AXGBE_PHY_REDRV_IF_MAX,
175 };
176
177 enum axgbe_phy_redrv_model {
178 AXGBE_PHY_REDRV_MODEL_4223 = 0,
179 AXGBE_PHY_REDRV_MODEL_4227,
180 AXGBE_PHY_REDRV_MODEL_MAX,
181 };
182
183 enum axgbe_phy_redrv_mode {
184 AXGBE_PHY_REDRV_MODE_CX = 5,
185 AXGBE_PHY_REDRV_MODE_SR = 9,
186 };
187
188 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0
189
190 /* PHY related configuration information */
191 struct axgbe_phy_data {
192 enum axgbe_port_mode port_mode;
193
194 unsigned int port_id;
195
196 unsigned int port_speeds;
197
198 enum axgbe_conn_type conn_type;
199
200 enum axgbe_mode cur_mode;
201 enum axgbe_mode start_mode;
202
203 unsigned int rrc_count;
204
205 unsigned int mdio_addr;
206
207 unsigned int comm_owned;
208
209 /* SFP Support */
210 enum axgbe_sfp_comm sfp_comm;
211 unsigned int sfp_mux_address;
212 unsigned int sfp_mux_channel;
213
214 unsigned int sfp_gpio_address;
215 unsigned int sfp_gpio_mask;
216 unsigned int sfp_gpio_rx_los;
217 unsigned int sfp_gpio_tx_fault;
218 unsigned int sfp_gpio_mod_absent;
219 unsigned int sfp_gpio_rate_select;
220
221 unsigned int sfp_rx_los;
222 unsigned int sfp_tx_fault;
223 unsigned int sfp_mod_absent;
224 unsigned int sfp_diags;
225 unsigned int sfp_changed;
226 unsigned int sfp_phy_avail;
227 unsigned int sfp_cable_len;
228 enum axgbe_sfp_base sfp_base;
229 enum axgbe_sfp_cable sfp_cable;
230 enum axgbe_sfp_speed sfp_speed;
231 struct axgbe_sfp_eeprom sfp_eeprom;
232
233 /* External PHY support */
234 enum axgbe_mdio_mode phydev_mode;
235 enum axgbe_mdio_reset mdio_reset;
236 unsigned int mdio_reset_addr;
237 unsigned int mdio_reset_gpio;
238
239 /* Re-driver support */
240 unsigned int redrv;
241 unsigned int redrv_if;
242 unsigned int redrv_addr;
243 unsigned int redrv_lane;
244 unsigned int redrv_model;
245
246 /* KR AN support */
247 unsigned int phy_cdr_notrack;
248 unsigned int phy_cdr_delay;
249 };
250
251 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata);
252
axgbe_phy_i2c_xfer(struct axgbe_port * pdata,struct axgbe_i2c_op * i2c_op)253 static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata,
254 struct axgbe_i2c_op *i2c_op)
255 {
256 struct axgbe_phy_data *phy_data = pdata->phy_data;
257
258 /* Be sure we own the bus */
259 if (!phy_data->comm_owned)
260 return -EIO;
261
262 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
263 }
264
axgbe_phy_redrv_write(struct axgbe_port * pdata,unsigned int reg,unsigned int val)265 static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg,
266 unsigned int val)
267 {
268 struct axgbe_phy_data *phy_data = pdata->phy_data;
269 struct axgbe_i2c_op i2c_op;
270 uint16_t *redrv_val;
271 u8 redrv_data[5], csum;
272 unsigned int i, retry;
273 int ret;
274
275 /* High byte of register contains read/write indicator */
276 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
277 redrv_data[1] = reg & 0xff;
278 redrv_val = (uint16_t *)&redrv_data[2];
279 *redrv_val = rte_cpu_to_be_16(val);
280
281 /* Calculate 1 byte checksum */
282 csum = 0;
283 for (i = 0; i < 4; i++) {
284 csum += redrv_data[i];
285 if (redrv_data[i] > csum)
286 csum++;
287 }
288 redrv_data[4] = ~csum;
289
290 retry = 1;
291 again1:
292 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
293 i2c_op.target = phy_data->redrv_addr;
294 i2c_op.len = sizeof(redrv_data);
295 i2c_op.buf = redrv_data;
296 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
297 if (ret) {
298 if ((ret == -EAGAIN) && retry--)
299 goto again1;
300
301 return ret;
302 }
303
304 retry = 1;
305 again2:
306 i2c_op.cmd = AXGBE_I2C_CMD_READ;
307 i2c_op.target = phy_data->redrv_addr;
308 i2c_op.len = 1;
309 i2c_op.buf = redrv_data;
310 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
311 if (ret) {
312 if ((ret == -EAGAIN) && retry--)
313 goto again2;
314
315 return ret;
316 }
317
318 if (redrv_data[0] != 0xff) {
319 PMD_DRV_LOG(ERR, "Redriver write checksum error\n");
320 ret = -EIO;
321 }
322
323 return ret;
324 }
325
axgbe_phy_i2c_read(struct axgbe_port * pdata,unsigned int target,void * reg,unsigned int reg_len,void * val,unsigned int val_len)326 static int axgbe_phy_i2c_read(struct axgbe_port *pdata, unsigned int target,
327 void *reg, unsigned int reg_len,
328 void *val, unsigned int val_len)
329 {
330 struct axgbe_i2c_op i2c_op;
331 int retry, ret;
332
333 retry = 1;
334 again1:
335 /* Set the specified register to read */
336 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
337 i2c_op.target = target;
338 i2c_op.len = reg_len;
339 i2c_op.buf = reg;
340 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
341 if (ret) {
342 if ((ret == -EAGAIN) && retry--)
343 goto again1;
344
345 return ret;
346 }
347
348 retry = 1;
349 again2:
350 /* Read the specfied register */
351 i2c_op.cmd = AXGBE_I2C_CMD_READ;
352 i2c_op.target = target;
353 i2c_op.len = val_len;
354 i2c_op.buf = val;
355 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op);
356 if ((ret == -EAGAIN) && retry--)
357 goto again2;
358
359 return ret;
360 }
361
axgbe_phy_sfp_put_mux(struct axgbe_port * pdata)362 static int axgbe_phy_sfp_put_mux(struct axgbe_port *pdata)
363 {
364 struct axgbe_phy_data *phy_data = pdata->phy_data;
365 struct axgbe_i2c_op i2c_op;
366 uint8_t mux_channel;
367
368 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT)
369 return 0;
370
371 /* Select no mux channels */
372 mux_channel = 0;
373 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
374 i2c_op.target = phy_data->sfp_mux_address;
375 i2c_op.len = sizeof(mux_channel);
376 i2c_op.buf = &mux_channel;
377
378 return axgbe_phy_i2c_xfer(pdata, &i2c_op);
379 }
380
axgbe_phy_sfp_get_mux(struct axgbe_port * pdata)381 static int axgbe_phy_sfp_get_mux(struct axgbe_port *pdata)
382 {
383 struct axgbe_phy_data *phy_data = pdata->phy_data;
384 struct axgbe_i2c_op i2c_op;
385 u8 mux_channel;
386
387 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT)
388 return 0;
389
390 /* Select desired mux channel */
391 mux_channel = 1 << phy_data->sfp_mux_channel;
392 i2c_op.cmd = AXGBE_I2C_CMD_WRITE;
393 i2c_op.target = phy_data->sfp_mux_address;
394 i2c_op.len = sizeof(mux_channel);
395 i2c_op.buf = &mux_channel;
396
397 return axgbe_phy_i2c_xfer(pdata, &i2c_op);
398 }
399
axgbe_phy_put_comm_ownership(struct axgbe_port * pdata)400 static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata)
401 {
402 struct axgbe_phy_data *phy_data = pdata->phy_data;
403
404 phy_data->comm_owned = 0;
405
406 pthread_mutex_unlock(&pdata->phy_mutex);
407 }
408
axgbe_phy_get_comm_ownership(struct axgbe_port * pdata)409 static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata)
410 {
411 struct axgbe_phy_data *phy_data = pdata->phy_data;
412 uint64_t timeout;
413 unsigned int mutex_id;
414
415 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
416 * the driver needs to take the software mutex and then the hardware
417 * mutexes before being able to use the busses.
418 */
419 pthread_mutex_lock(&pdata->phy_mutex);
420
421 if (phy_data->comm_owned)
422 return 0;
423
424 /* Clear the mutexes */
425 XP_IOWRITE(pdata, XP_I2C_MUTEX, AXGBE_MUTEX_RELEASE);
426 XP_IOWRITE(pdata, XP_MDIO_MUTEX, AXGBE_MUTEX_RELEASE);
427
428 /* Mutex formats are the same for I2C and MDIO/GPIO */
429 mutex_id = 0;
430 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
431 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
432
433 timeout = rte_get_timer_cycles() + (rte_get_timer_hz() * 5);
434 while (time_before(rte_get_timer_cycles(), timeout)) {
435 /* Must be all zeroes in order to obtain the mutex */
436 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
437 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
438 rte_delay_us(100);
439 continue;
440 }
441
442 /* Obtain the mutex */
443 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
444 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
445
446 phy_data->comm_owned = 1;
447 return 0;
448 }
449
450 pthread_mutex_unlock(&pdata->phy_mutex);
451
452 PMD_DRV_LOG(ERR, "unable to obtain hardware mutexes\n");
453
454 return -ETIMEDOUT;
455 }
456
axgbe_phy_sfp_phy_settings(struct axgbe_port * pdata)457 static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata)
458 {
459 struct axgbe_phy_data *phy_data = pdata->phy_data;
460
461 if (phy_data->sfp_mod_absent) {
462 pdata->phy.speed = SPEED_UNKNOWN;
463 pdata->phy.duplex = DUPLEX_UNKNOWN;
464 pdata->phy.autoneg = AUTONEG_ENABLE;
465 pdata->phy.advertising = pdata->phy.supported;
466 }
467
468 pdata->phy.advertising &= ~ADVERTISED_Autoneg;
469 pdata->phy.advertising &= ~ADVERTISED_TP;
470 pdata->phy.advertising &= ~ADVERTISED_FIBRE;
471 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full;
472 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full;
473 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full;
474 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC;
475
476 switch (phy_data->sfp_base) {
477 case AXGBE_SFP_BASE_1000_T:
478 case AXGBE_SFP_BASE_1000_SX:
479 case AXGBE_SFP_BASE_1000_LX:
480 case AXGBE_SFP_BASE_1000_CX:
481 pdata->phy.speed = SPEED_UNKNOWN;
482 pdata->phy.duplex = DUPLEX_UNKNOWN;
483 pdata->phy.autoneg = AUTONEG_ENABLE;
484 pdata->phy.advertising |= ADVERTISED_Autoneg;
485 break;
486 case AXGBE_SFP_BASE_10000_SR:
487 case AXGBE_SFP_BASE_10000_LR:
488 case AXGBE_SFP_BASE_10000_LRM:
489 case AXGBE_SFP_BASE_10000_ER:
490 case AXGBE_SFP_BASE_10000_CR:
491 default:
492 pdata->phy.speed = SPEED_10000;
493 pdata->phy.duplex = DUPLEX_FULL;
494 pdata->phy.autoneg = AUTONEG_DISABLE;
495 break;
496 }
497
498 switch (phy_data->sfp_base) {
499 case AXGBE_SFP_BASE_1000_T:
500 case AXGBE_SFP_BASE_1000_CX:
501 case AXGBE_SFP_BASE_10000_CR:
502 pdata->phy.advertising |= ADVERTISED_TP;
503 break;
504 default:
505 pdata->phy.advertising |= ADVERTISED_FIBRE;
506 }
507
508 switch (phy_data->sfp_speed) {
509 case AXGBE_SFP_SPEED_100_1000:
510 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100)
511 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
512 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
513 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
514 break;
515 case AXGBE_SFP_SPEED_1000:
516 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
517 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
518 break;
519 case AXGBE_SFP_SPEED_10000:
520 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
521 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
522 break;
523 default:
524 /* Choose the fastest supported speed */
525 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
526 pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
527 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
528 pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
529 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100)
530 pdata->phy.advertising |= ADVERTISED_100baseT_Full;
531 }
532 }
533
axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom * sfp_eeprom,enum axgbe_sfp_speed sfp_speed)534 static bool axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom *sfp_eeprom,
535 enum axgbe_sfp_speed sfp_speed)
536 {
537 u8 *sfp_base, min, max;
538
539 sfp_base = sfp_eeprom->base;
540
541 switch (sfp_speed) {
542 case AXGBE_SFP_SPEED_1000:
543 min = AXGBE_SFP_BASE_BR_1GBE_MIN;
544 max = AXGBE_SFP_BASE_BR_1GBE_MAX;
545 break;
546 case AXGBE_SFP_SPEED_10000:
547 min = AXGBE_SFP_BASE_BR_10GBE_MIN;
548 max = AXGBE_SFP_BASE_BR_10GBE_MAX;
549 break;
550 default:
551 return false;
552 }
553
554 return ((sfp_base[AXGBE_SFP_BASE_BR] >= min) &&
555 (sfp_base[AXGBE_SFP_BASE_BR] <= max));
556 }
557
axgbe_phy_sfp_external_phy(struct axgbe_port * pdata)558 static void axgbe_phy_sfp_external_phy(struct axgbe_port *pdata)
559 {
560 struct axgbe_phy_data *phy_data = pdata->phy_data;
561
562 if (!phy_data->sfp_changed)
563 return;
564
565 phy_data->sfp_phy_avail = 0;
566
567 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
568 return;
569 }
570
axgbe_phy_belfuse_parse_quirks(struct axgbe_port * pdata)571 static bool axgbe_phy_belfuse_parse_quirks(struct axgbe_port *pdata)
572 {
573 struct axgbe_phy_data *phy_data = pdata->phy_data;
574 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
575
576 if (memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_NAME],
577 AXGBE_BEL_FUSE_VENDOR, strlen(AXGBE_BEL_FUSE_VENDOR)))
578 return false;
579
580 if (!memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_PN],
581 AXGBE_BEL_FUSE_PARTNO, strlen(AXGBE_BEL_FUSE_PARTNO))) {
582 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX;
583 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE;
584 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000;
585 return true;
586 }
587
588 return false;
589 }
590
axgbe_phy_sfp_parse_quirks(struct axgbe_port * pdata)591 static bool axgbe_phy_sfp_parse_quirks(struct axgbe_port *pdata)
592 {
593 if (axgbe_phy_belfuse_parse_quirks(pdata))
594 return true;
595
596 return false;
597 }
598
axgbe_phy_sfp_parse_eeprom(struct axgbe_port * pdata)599 static void axgbe_phy_sfp_parse_eeprom(struct axgbe_port *pdata)
600 {
601 struct axgbe_phy_data *phy_data = pdata->phy_data;
602 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
603 uint8_t *sfp_base;
604
605 sfp_base = sfp_eeprom->base;
606
607 if (sfp_base[AXGBE_SFP_BASE_ID] != AXGBE_SFP_ID_SFP)
608 return;
609
610 if (sfp_base[AXGBE_SFP_BASE_EXT_ID] != AXGBE_SFP_EXT_ID_SFP)
611 return;
612
613 axgbe_phy_sfp_parse_quirks(pdata);
614
615 /* Assume ACTIVE cable unless told it is PASSIVE */
616 if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_PASSIVE) {
617 phy_data->sfp_cable = AXGBE_SFP_CABLE_PASSIVE;
618 phy_data->sfp_cable_len = sfp_base[AXGBE_SFP_BASE_CU_CABLE_LEN];
619 } else {
620 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE;
621 }
622
623 /* Determine the type of SFP */
624 if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_SR)
625 phy_data->sfp_base = AXGBE_SFP_BASE_10000_SR;
626 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_LR)
627 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LR;
628 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] &
629 AXGBE_SFP_BASE_10GBE_CC_LRM)
630 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LRM;
631 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_ER)
632 phy_data->sfp_base = AXGBE_SFP_BASE_10000_ER;
633 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_SX)
634 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX;
635 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_LX)
636 phy_data->sfp_base = AXGBE_SFP_BASE_1000_LX;
637 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_CX)
638 phy_data->sfp_base = AXGBE_SFP_BASE_1000_CX;
639 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_T)
640 phy_data->sfp_base = AXGBE_SFP_BASE_1000_T;
641 else if ((phy_data->sfp_cable == AXGBE_SFP_CABLE_PASSIVE) &&
642 axgbe_phy_sfp_bit_rate(sfp_eeprom, AXGBE_SFP_SPEED_10000))
643 phy_data->sfp_base = AXGBE_SFP_BASE_10000_CR;
644
645 switch (phy_data->sfp_base) {
646 case AXGBE_SFP_BASE_1000_T:
647 phy_data->sfp_speed = AXGBE_SFP_SPEED_100_1000;
648 break;
649 case AXGBE_SFP_BASE_1000_SX:
650 case AXGBE_SFP_BASE_1000_LX:
651 case AXGBE_SFP_BASE_1000_CX:
652 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000;
653 break;
654 case AXGBE_SFP_BASE_10000_SR:
655 case AXGBE_SFP_BASE_10000_LR:
656 case AXGBE_SFP_BASE_10000_LRM:
657 case AXGBE_SFP_BASE_10000_ER:
658 case AXGBE_SFP_BASE_10000_CR:
659 phy_data->sfp_speed = AXGBE_SFP_SPEED_10000;
660 break;
661 default:
662 break;
663 }
664 }
665
axgbe_phy_sfp_verify_eeprom(uint8_t cc_in,uint8_t * buf,unsigned int len)666 static bool axgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf,
667 unsigned int len)
668 {
669 uint8_t cc;
670
671 for (cc = 0; len; buf++, len--)
672 cc += *buf;
673
674 return (cc == cc_in) ? true : false;
675 }
676
axgbe_phy_sfp_read_eeprom(struct axgbe_port * pdata)677 static int axgbe_phy_sfp_read_eeprom(struct axgbe_port *pdata)
678 {
679 struct axgbe_phy_data *phy_data = pdata->phy_data;
680 struct axgbe_sfp_eeprom sfp_eeprom;
681 uint8_t eeprom_addr;
682 int ret;
683
684 ret = axgbe_phy_sfp_get_mux(pdata);
685 if (ret) {
686 PMD_DRV_LOG(ERR, "I2C error setting SFP MUX\n");
687 return ret;
688 }
689
690 /* Read the SFP serial ID eeprom */
691 eeprom_addr = 0;
692 ret = axgbe_phy_i2c_read(pdata, AXGBE_SFP_SERIAL_ID_ADDRESS,
693 &eeprom_addr, sizeof(eeprom_addr),
694 &sfp_eeprom, sizeof(sfp_eeprom));
695 if (ret) {
696 PMD_DRV_LOG(ERR, "I2C error reading SFP EEPROM\n");
697 goto put;
698 }
699
700 /* Validate the contents read */
701 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[AXGBE_SFP_BASE_CC],
702 sfp_eeprom.base,
703 sizeof(sfp_eeprom.base) - 1)) {
704 ret = -EINVAL;
705 goto put;
706 }
707
708 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[AXGBE_SFP_EXTD_CC],
709 sfp_eeprom.extd,
710 sizeof(sfp_eeprom.extd) - 1)) {
711 ret = -EINVAL;
712 goto put;
713 }
714
715 /* Check for an added or changed SFP */
716 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
717 phy_data->sfp_changed = 1;
718 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
719
720 if (sfp_eeprom.extd[AXGBE_SFP_EXTD_SFF_8472]) {
721 uint8_t diag_type;
722 diag_type = sfp_eeprom.extd[AXGBE_SFP_EXTD_DIAG];
723
724 if (!(diag_type & AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
725 phy_data->sfp_diags = 1;
726 }
727 } else {
728 phy_data->sfp_changed = 0;
729 }
730
731 put:
732 axgbe_phy_sfp_put_mux(pdata);
733
734 return ret;
735 }
736
axgbe_phy_sfp_signals(struct axgbe_port * pdata)737 static void axgbe_phy_sfp_signals(struct axgbe_port *pdata)
738 {
739 struct axgbe_phy_data *phy_data = pdata->phy_data;
740 unsigned int gpio_input;
741 u8 gpio_reg, gpio_ports[2];
742 int ret;
743
744 /* Read the input port registers */
745 gpio_reg = 0;
746 ret = axgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
747 &gpio_reg, sizeof(gpio_reg),
748 gpio_ports, sizeof(gpio_ports));
749 if (ret) {
750 PMD_DRV_LOG(ERR, "I2C error reading SFP GPIOs\n");
751 return;
752 }
753
754 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0];
755
756 if (phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_MOD_ABSENT) {
757 /* No GPIO, just assume the module is present for now */
758 phy_data->sfp_mod_absent = 0;
759 } else {
760 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent)))
761 phy_data->sfp_mod_absent = 0;
762 }
763
764 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_RX_LOS) &&
765 (gpio_input & (1 << phy_data->sfp_gpio_rx_los)))
766 phy_data->sfp_rx_los = 1;
767
768 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_TX_FAULT) &&
769 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault)))
770 phy_data->sfp_tx_fault = 1;
771 }
772
axgbe_phy_sfp_mod_absent(struct axgbe_port * pdata)773 static void axgbe_phy_sfp_mod_absent(struct axgbe_port *pdata)
774 {
775 struct axgbe_phy_data *phy_data = pdata->phy_data;
776
777 phy_data->sfp_mod_absent = 1;
778 phy_data->sfp_phy_avail = 0;
779 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
780 }
781
axgbe_phy_sfp_reset(struct axgbe_phy_data * phy_data)782 static void axgbe_phy_sfp_reset(struct axgbe_phy_data *phy_data)
783 {
784 phy_data->sfp_rx_los = 0;
785 phy_data->sfp_tx_fault = 0;
786 phy_data->sfp_mod_absent = 1;
787 phy_data->sfp_diags = 0;
788 phy_data->sfp_base = AXGBE_SFP_BASE_UNKNOWN;
789 phy_data->sfp_cable = AXGBE_SFP_CABLE_UNKNOWN;
790 phy_data->sfp_speed = AXGBE_SFP_SPEED_UNKNOWN;
791 }
792
axgbe_base_as_string(enum axgbe_sfp_base sfp_base)793 static const char *axgbe_base_as_string(enum axgbe_sfp_base sfp_base)
794 {
795 switch (sfp_base) {
796 case AXGBE_SFP_BASE_1000_T:
797 return "1G_T";
798 case AXGBE_SFP_BASE_1000_SX:
799 return "1G_SX";
800 case AXGBE_SFP_BASE_1000_LX:
801 return "1G_LX";
802 case AXGBE_SFP_BASE_1000_CX:
803 return "1G_CX";
804 case AXGBE_SFP_BASE_10000_SR:
805 return "10G_SR";
806 case AXGBE_SFP_BASE_10000_LR:
807 return "10G_LR";
808 case AXGBE_SFP_BASE_10000_LRM:
809 return "10G_LRM";
810 case AXGBE_SFP_BASE_10000_ER:
811 return "10G_ER";
812 case AXGBE_SFP_BASE_10000_CR:
813 return "10G_CR";
814 default:
815 return "Unknown";
816 }
817 }
818
axgbe_phy_sfp_detect(struct axgbe_port * pdata)819 static void axgbe_phy_sfp_detect(struct axgbe_port *pdata)
820 {
821 struct axgbe_phy_data *phy_data = pdata->phy_data;
822 int ret;
823
824 /* Reset the SFP signals and info */
825 axgbe_phy_sfp_reset(phy_data);
826
827 ret = axgbe_phy_get_comm_ownership(pdata);
828 if (ret)
829 return;
830
831 /* Read the SFP signals and check for module presence */
832 axgbe_phy_sfp_signals(pdata);
833 if (phy_data->sfp_mod_absent) {
834 axgbe_phy_sfp_mod_absent(pdata);
835 goto put;
836 }
837
838 ret = axgbe_phy_sfp_read_eeprom(pdata);
839 if (ret) {
840 /* Treat any error as if there isn't an SFP plugged in */
841 axgbe_phy_sfp_reset(phy_data);
842 axgbe_phy_sfp_mod_absent(pdata);
843 goto put;
844 }
845
846 axgbe_phy_sfp_parse_eeprom(pdata);
847 axgbe_phy_sfp_external_phy(pdata);
848
849 PMD_DRV_LOG(DEBUG, "SFP Base: %s\n",
850 axgbe_base_as_string(phy_data->sfp_base));
851
852 put:
853 axgbe_phy_sfp_phy_settings(pdata);
854 axgbe_phy_put_comm_ownership(pdata);
855 }
856
axgbe_phy_phydev_flowctrl(struct axgbe_port * pdata)857 static void axgbe_phy_phydev_flowctrl(struct axgbe_port *pdata)
858 {
859 pdata->phy.tx_pause = 0;
860 pdata->phy.rx_pause = 0;
861 }
862
axgbe_phy_an73_redrv_outcome(struct axgbe_port * pdata)863 static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata)
864 {
865 struct axgbe_phy_data *phy_data = pdata->phy_data;
866 enum axgbe_mode mode;
867 unsigned int ad_reg, lp_reg;
868
869 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
870 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
871
872 /* Use external PHY to determine flow control */
873 if (pdata->phy.pause_autoneg)
874 axgbe_phy_phydev_flowctrl(pdata);
875
876 /* Compare Advertisement and Link Partner register 2 */
877 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
878 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
879 if (lp_reg & 0x80)
880 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
881 if (lp_reg & 0x20)
882 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
883
884 ad_reg &= lp_reg;
885 if (ad_reg & 0x80) {
886 switch (phy_data->port_mode) {
887 case AXGBE_PORT_MODE_BACKPLANE:
888 mode = AXGBE_MODE_KR;
889 break;
890 default:
891 mode = AXGBE_MODE_SFI;
892 break;
893 }
894 } else if (ad_reg & 0x20) {
895 switch (phy_data->port_mode) {
896 case AXGBE_PORT_MODE_BACKPLANE:
897 mode = AXGBE_MODE_KX_1000;
898 break;
899 case AXGBE_PORT_MODE_1000BASE_X:
900 mode = AXGBE_MODE_X;
901 break;
902 case AXGBE_PORT_MODE_SFP:
903 switch (phy_data->sfp_base) {
904 case AXGBE_SFP_BASE_1000_T:
905 mode = AXGBE_MODE_SGMII_1000;
906 break;
907 case AXGBE_SFP_BASE_1000_SX:
908 case AXGBE_SFP_BASE_1000_LX:
909 case AXGBE_SFP_BASE_1000_CX:
910 default:
911 mode = AXGBE_MODE_X;
912 break;
913 }
914 break;
915 default:
916 mode = AXGBE_MODE_SGMII_1000;
917 break;
918 }
919 } else {
920 mode = AXGBE_MODE_UNKNOWN;
921 }
922
923 /* Compare Advertisement and Link Partner register 3 */
924 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
925 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
926 if (lp_reg & 0xc000)
927 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
928
929 return mode;
930 }
931
axgbe_phy_an73_outcome(struct axgbe_port * pdata)932 static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata)
933 {
934 enum axgbe_mode mode;
935 unsigned int ad_reg, lp_reg;
936
937 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
938 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
939
940 /* Compare Advertisement and Link Partner register 1 */
941 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
942 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
943 if (lp_reg & 0x400)
944 pdata->phy.lp_advertising |= ADVERTISED_Pause;
945 if (lp_reg & 0x800)
946 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
947
948 if (pdata->phy.pause_autoneg) {
949 /* Set flow control based on auto-negotiation result */
950 pdata->phy.tx_pause = 0;
951 pdata->phy.rx_pause = 0;
952
953 if (ad_reg & lp_reg & 0x400) {
954 pdata->phy.tx_pause = 1;
955 pdata->phy.rx_pause = 1;
956 } else if (ad_reg & lp_reg & 0x800) {
957 if (ad_reg & 0x400)
958 pdata->phy.rx_pause = 1;
959 else if (lp_reg & 0x400)
960 pdata->phy.tx_pause = 1;
961 }
962 }
963
964 /* Compare Advertisement and Link Partner register 2 */
965 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
966 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
967 if (lp_reg & 0x80)
968 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
969 if (lp_reg & 0x20)
970 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
971
972 ad_reg &= lp_reg;
973 if (ad_reg & 0x80)
974 mode = AXGBE_MODE_KR;
975 else if (ad_reg & 0x20)
976 mode = AXGBE_MODE_KX_1000;
977 else
978 mode = AXGBE_MODE_UNKNOWN;
979
980 /* Compare Advertisement and Link Partner register 3 */
981 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
982 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
983 if (lp_reg & 0xc000)
984 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
985
986 return mode;
987 }
988
axgbe_phy_an37_sgmii_outcome(struct axgbe_port * pdata)989 static enum axgbe_mode axgbe_phy_an37_sgmii_outcome(struct axgbe_port *pdata)
990 {
991 enum axgbe_mode mode;
992
993 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
994 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
995
996 if (pdata->phy.pause_autoneg)
997 axgbe_phy_phydev_flowctrl(pdata);
998
999 switch (pdata->an_status & AXGBE_SGMII_AN_LINK_SPEED) {
1000 case AXGBE_SGMII_AN_LINK_SPEED_100:
1001 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) {
1002 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full;
1003 mode = AXGBE_MODE_SGMII_100;
1004 } else {
1005 mode = AXGBE_MODE_UNKNOWN;
1006 }
1007 break;
1008 case AXGBE_SGMII_AN_LINK_SPEED_1000:
1009 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) {
1010 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
1011 mode = AXGBE_MODE_SGMII_1000;
1012 } else {
1013 /* Half-duplex not supported */
1014 mode = AXGBE_MODE_UNKNOWN;
1015 }
1016 break;
1017 default:
1018 mode = AXGBE_MODE_UNKNOWN;
1019 break;
1020 }
1021 return mode;
1022 }
1023
axgbe_phy_an_outcome(struct axgbe_port * pdata)1024 static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata)
1025 {
1026 switch (pdata->an_mode) {
1027 case AXGBE_AN_MODE_CL73:
1028 return axgbe_phy_an73_outcome(pdata);
1029 case AXGBE_AN_MODE_CL73_REDRV:
1030 return axgbe_phy_an73_redrv_outcome(pdata);
1031 case AXGBE_AN_MODE_CL37:
1032 case AXGBE_AN_MODE_CL37_SGMII:
1033 return axgbe_phy_an37_sgmii_outcome(pdata);
1034 default:
1035 return AXGBE_MODE_UNKNOWN;
1036 }
1037 }
1038
axgbe_phy_an_advertising(struct axgbe_port * pdata)1039 static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata)
1040 {
1041 struct axgbe_phy_data *phy_data = pdata->phy_data;
1042 unsigned int advertising;
1043
1044 /* Without a re-driver, just return current advertising */
1045 if (!phy_data->redrv)
1046 return pdata->phy.advertising;
1047
1048 /* With the KR re-driver we need to advertise a single speed */
1049 advertising = pdata->phy.advertising;
1050 advertising &= ~ADVERTISED_1000baseKX_Full;
1051 advertising &= ~ADVERTISED_10000baseKR_Full;
1052
1053 switch (phy_data->port_mode) {
1054 case AXGBE_PORT_MODE_BACKPLANE:
1055 advertising |= ADVERTISED_10000baseKR_Full;
1056 break;
1057 case AXGBE_PORT_MODE_BACKPLANE_2500:
1058 advertising |= ADVERTISED_1000baseKX_Full;
1059 break;
1060 case AXGBE_PORT_MODE_1000BASE_T:
1061 case AXGBE_PORT_MODE_1000BASE_X:
1062 case AXGBE_PORT_MODE_NBASE_T:
1063 advertising |= ADVERTISED_1000baseKX_Full;
1064 break;
1065 case AXGBE_PORT_MODE_10GBASE_T:
1066 PMD_DRV_LOG(ERR, "10GBASE_T mode is not supported\n");
1067 break;
1068 case AXGBE_PORT_MODE_10GBASE_R:
1069 advertising |= ADVERTISED_10000baseKR_Full;
1070 break;
1071 case AXGBE_PORT_MODE_SFP:
1072 switch (phy_data->sfp_base) {
1073 case AXGBE_SFP_BASE_1000_T:
1074 case AXGBE_SFP_BASE_1000_SX:
1075 case AXGBE_SFP_BASE_1000_LX:
1076 case AXGBE_SFP_BASE_1000_CX:
1077 advertising |= ADVERTISED_1000baseKX_Full;
1078 break;
1079 default:
1080 advertising |= ADVERTISED_10000baseKR_Full;
1081 break;
1082 }
1083 break;
1084 default:
1085 advertising |= ADVERTISED_10000baseKR_Full;
1086 break;
1087 }
1088
1089 return advertising;
1090 }
1091
axgbe_phy_an_config(struct axgbe_port * pdata __rte_unused)1092 static int axgbe_phy_an_config(struct axgbe_port *pdata __rte_unused)
1093 {
1094 return 0;
1095 /* Dummy API since there is no case to support
1096 * external phy devices registred through kerenl apis
1097 */
1098 }
1099
axgbe_phy_an_sfp_mode(struct axgbe_phy_data * phy_data)1100 static enum axgbe_an_mode axgbe_phy_an_sfp_mode(struct axgbe_phy_data *phy_data)
1101 {
1102 switch (phy_data->sfp_base) {
1103 case AXGBE_SFP_BASE_1000_T:
1104 return AXGBE_AN_MODE_CL37_SGMII;
1105 case AXGBE_SFP_BASE_1000_SX:
1106 case AXGBE_SFP_BASE_1000_LX:
1107 case AXGBE_SFP_BASE_1000_CX:
1108 return AXGBE_AN_MODE_CL37;
1109 default:
1110 return AXGBE_AN_MODE_NONE;
1111 }
1112 }
1113
axgbe_phy_an_mode(struct axgbe_port * pdata)1114 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata)
1115 {
1116 struct axgbe_phy_data *phy_data = pdata->phy_data;
1117
1118 /* A KR re-driver will always require CL73 AN */
1119 if (phy_data->redrv)
1120 return AXGBE_AN_MODE_CL73_REDRV;
1121
1122 switch (phy_data->port_mode) {
1123 case AXGBE_PORT_MODE_BACKPLANE:
1124 return AXGBE_AN_MODE_CL73;
1125 case AXGBE_PORT_MODE_BACKPLANE_2500:
1126 return AXGBE_AN_MODE_NONE;
1127 case AXGBE_PORT_MODE_1000BASE_T:
1128 return AXGBE_AN_MODE_CL37_SGMII;
1129 case AXGBE_PORT_MODE_1000BASE_X:
1130 return AXGBE_AN_MODE_CL37;
1131 case AXGBE_PORT_MODE_NBASE_T:
1132 return AXGBE_AN_MODE_CL37_SGMII;
1133 case AXGBE_PORT_MODE_10GBASE_T:
1134 return AXGBE_AN_MODE_CL73;
1135 case AXGBE_PORT_MODE_10GBASE_R:
1136 return AXGBE_AN_MODE_NONE;
1137 case AXGBE_PORT_MODE_SFP:
1138 return axgbe_phy_an_sfp_mode(phy_data);
1139 default:
1140 return AXGBE_AN_MODE_NONE;
1141 }
1142 }
1143
axgbe_phy_set_redrv_mode_mdio(struct axgbe_port * pdata,enum axgbe_phy_redrv_mode mode)1144 static int axgbe_phy_set_redrv_mode_mdio(struct axgbe_port *pdata,
1145 enum axgbe_phy_redrv_mode mode)
1146 {
1147 struct axgbe_phy_data *phy_data = pdata->phy_data;
1148 u16 redrv_reg, redrv_val;
1149
1150 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1151 redrv_val = (u16)mode;
1152
1153 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1154 redrv_reg, redrv_val);
1155 }
1156
axgbe_phy_set_redrv_mode_i2c(struct axgbe_port * pdata,enum axgbe_phy_redrv_mode mode)1157 static int axgbe_phy_set_redrv_mode_i2c(struct axgbe_port *pdata,
1158 enum axgbe_phy_redrv_mode mode)
1159 {
1160 struct axgbe_phy_data *phy_data = pdata->phy_data;
1161 unsigned int redrv_reg;
1162 int ret;
1163
1164 /* Calculate the register to write */
1165 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1166
1167 ret = axgbe_phy_redrv_write(pdata, redrv_reg, mode);
1168
1169 return ret;
1170 }
1171
axgbe_phy_set_redrv_mode(struct axgbe_port * pdata)1172 static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata)
1173 {
1174 struct axgbe_phy_data *phy_data = pdata->phy_data;
1175 enum axgbe_phy_redrv_mode mode;
1176 int ret;
1177
1178 if (!phy_data->redrv)
1179 return;
1180
1181 mode = AXGBE_PHY_REDRV_MODE_CX;
1182 if ((phy_data->port_mode == AXGBE_PORT_MODE_SFP) &&
1183 (phy_data->sfp_base != AXGBE_SFP_BASE_1000_CX) &&
1184 (phy_data->sfp_base != AXGBE_SFP_BASE_10000_CR))
1185 mode = AXGBE_PHY_REDRV_MODE_SR;
1186
1187 ret = axgbe_phy_get_comm_ownership(pdata);
1188 if (ret)
1189 return;
1190
1191 if (phy_data->redrv_if)
1192 axgbe_phy_set_redrv_mode_i2c(pdata, mode);
1193 else
1194 axgbe_phy_set_redrv_mode_mdio(pdata, mode);
1195
1196 axgbe_phy_put_comm_ownership(pdata);
1197 }
1198
axgbe_phy_start_ratechange(struct axgbe_port * pdata)1199 static void axgbe_phy_start_ratechange(struct axgbe_port *pdata)
1200 {
1201 /* Log if a previous command did not complete */
1202 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1203 PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
1204 else
1205 return;
1206 }
1207
axgbe_phy_complete_ratechange(struct axgbe_port * pdata)1208 static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata)
1209 {
1210 unsigned int wait;
1211
1212 /* Wait for command to complete */
1213 wait = AXGBE_RATECHANGE_COUNT;
1214 while (wait--) {
1215 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1216 return;
1217
1218 rte_delay_us(1500);
1219 }
1220 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
1221 }
1222
axgbe_phy_rrc(struct axgbe_port * pdata)1223 static void axgbe_phy_rrc(struct axgbe_port *pdata)
1224 {
1225 unsigned int s0;
1226
1227 axgbe_phy_start_ratechange(pdata);
1228
1229 /* Receiver Reset Cycle */
1230 s0 = 0;
1231 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5);
1232 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1233
1234 /* Call FW to make the change */
1235 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1236 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1237 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1238
1239 axgbe_phy_complete_ratechange(pdata);
1240
1241 PMD_DRV_LOG(DEBUG, "receiver reset complete\n");
1242 }
1243
axgbe_phy_power_off(struct axgbe_port * pdata)1244 static void axgbe_phy_power_off(struct axgbe_port *pdata)
1245 {
1246 struct axgbe_phy_data *phy_data = pdata->phy_data;
1247
1248 axgbe_phy_start_ratechange(pdata);
1249
1250 /* Call FW to make the change */
1251 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0);
1252 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1253 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1254 axgbe_phy_complete_ratechange(pdata);
1255 phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
1256
1257 PMD_DRV_LOG(DEBUG, "phy powered off\n");
1258 }
1259
axgbe_phy_sfi_mode(struct axgbe_port * pdata)1260 static void axgbe_phy_sfi_mode(struct axgbe_port *pdata)
1261 {
1262 struct axgbe_phy_data *phy_data = pdata->phy_data;
1263 unsigned int s0;
1264
1265 axgbe_phy_set_redrv_mode(pdata);
1266
1267 axgbe_phy_start_ratechange(pdata);
1268
1269 /* 10G/SFI */
1270 s0 = 0;
1271 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3);
1272 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) {
1273 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1274 } else {
1275 if (phy_data->sfp_cable_len <= 1)
1276 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
1277 else if (phy_data->sfp_cable_len <= 3)
1278 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
1279 else
1280 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
1281 }
1282
1283 /* Call FW to make the change */
1284 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1285 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1286 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1287 axgbe_phy_complete_ratechange(pdata);
1288 phy_data->cur_mode = AXGBE_MODE_SFI;
1289
1290 PMD_DRV_LOG(DEBUG, "10GbE SFI mode set\n");
1291 }
1292
axgbe_phy_kr_mode(struct axgbe_port * pdata)1293 static void axgbe_phy_kr_mode(struct axgbe_port *pdata)
1294 {
1295 struct axgbe_phy_data *phy_data = pdata->phy_data;
1296 unsigned int s0;
1297
1298 axgbe_phy_set_redrv_mode(pdata);
1299
1300 axgbe_phy_start_ratechange(pdata);
1301
1302 /* 10G/KR */
1303 s0 = 0;
1304 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 4);
1305 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1306
1307 /* Call FW to make the change */
1308 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1309 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1310 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1311 axgbe_phy_complete_ratechange(pdata);
1312 phy_data->cur_mode = AXGBE_MODE_KR;
1313
1314 PMD_DRV_LOG(DEBUG, "10GbE KR mode set\n");
1315 }
1316
axgbe_phy_kx_2500_mode(struct axgbe_port * pdata)1317 static void axgbe_phy_kx_2500_mode(struct axgbe_port *pdata)
1318 {
1319 struct axgbe_phy_data *phy_data = pdata->phy_data;
1320 unsigned int s0;
1321
1322 axgbe_phy_set_redrv_mode(pdata);
1323 /* 2.5G/KX */
1324 axgbe_phy_start_ratechange(pdata);
1325 s0 = 0;
1326 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 2);
1327 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
1328
1329 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1330 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1331
1332 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1333
1334 phy_data->cur_mode = AXGBE_MODE_KX_2500;
1335 }
1336
axgbe_phy_sgmii_1000_mode(struct axgbe_port * pdata)1337 static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata)
1338 {
1339 struct axgbe_phy_data *phy_data = pdata->phy_data;
1340 unsigned int s0;
1341
1342 axgbe_phy_set_redrv_mode(pdata);
1343
1344 /* 1G/SGMII */
1345 axgbe_phy_start_ratechange(pdata);
1346 s0 = 0;
1347 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
1348 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
1349
1350 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1351 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1352
1353 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1354
1355 phy_data->cur_mode = AXGBE_MODE_SGMII_1000;
1356 }
1357
axgbe_phy_cur_mode(struct axgbe_port * pdata)1358 static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata)
1359 {
1360 struct axgbe_phy_data *phy_data = pdata->phy_data;
1361
1362 return phy_data->cur_mode;
1363 }
1364
axgbe_phy_switch_baset_mode(struct axgbe_port * pdata)1365 static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata)
1366 {
1367 struct axgbe_phy_data *phy_data = pdata->phy_data;
1368
1369 /* No switching if not 10GBase-T */
1370 if (phy_data->port_mode != AXGBE_PORT_MODE_10GBASE_T)
1371 return axgbe_phy_cur_mode(pdata);
1372
1373 switch (axgbe_phy_cur_mode(pdata)) {
1374 case AXGBE_MODE_SGMII_100:
1375 case AXGBE_MODE_SGMII_1000:
1376 return AXGBE_MODE_KR;
1377 case AXGBE_MODE_KR:
1378 default:
1379 return AXGBE_MODE_SGMII_1000;
1380 }
1381 }
1382
axgbe_phy_switch_bp_2500_mode(struct axgbe_port * pdata __rte_unused)1383 static enum axgbe_mode axgbe_phy_switch_bp_2500_mode(struct axgbe_port *pdata
1384 __rte_unused)
1385 {
1386 return AXGBE_MODE_KX_2500;
1387 }
1388
axgbe_phy_switch_bp_mode(struct axgbe_port * pdata)1389 static enum axgbe_mode axgbe_phy_switch_bp_mode(struct axgbe_port *pdata)
1390 {
1391 /* If we are in KR switch to KX, and vice-versa */
1392 switch (axgbe_phy_cur_mode(pdata)) {
1393 case AXGBE_MODE_KX_1000:
1394 return AXGBE_MODE_KR;
1395 case AXGBE_MODE_KR:
1396 default:
1397 return AXGBE_MODE_KX_1000;
1398 }
1399 }
1400
axgbe_phy_switch_mode(struct axgbe_port * pdata)1401 static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata)
1402 {
1403 struct axgbe_phy_data *phy_data = pdata->phy_data;
1404
1405 switch (phy_data->port_mode) {
1406 case AXGBE_PORT_MODE_BACKPLANE:
1407 return axgbe_phy_switch_bp_mode(pdata);
1408 case AXGBE_PORT_MODE_BACKPLANE_2500:
1409 return axgbe_phy_switch_bp_2500_mode(pdata);
1410 case AXGBE_PORT_MODE_1000BASE_T:
1411 case AXGBE_PORT_MODE_NBASE_T:
1412 case AXGBE_PORT_MODE_10GBASE_T:
1413 return axgbe_phy_switch_baset_mode(pdata);
1414 case AXGBE_PORT_MODE_1000BASE_X:
1415 case AXGBE_PORT_MODE_10GBASE_R:
1416 case AXGBE_PORT_MODE_SFP:
1417 /* No switching, so just return current mode */
1418 return axgbe_phy_cur_mode(pdata);
1419 default:
1420 return AXGBE_MODE_UNKNOWN;
1421 }
1422 }
1423
axgbe_phy_get_basex_mode(struct axgbe_phy_data * phy_data __rte_unused,int speed)1424 static enum axgbe_mode axgbe_phy_get_basex_mode(struct axgbe_phy_data *phy_data
1425 __rte_unused,
1426 int speed)
1427 {
1428 switch (speed) {
1429 case SPEED_1000:
1430 return AXGBE_MODE_X;
1431 case SPEED_10000:
1432 return AXGBE_MODE_KR;
1433 default:
1434 return AXGBE_MODE_UNKNOWN;
1435 }
1436 }
1437
axgbe_phy_get_baset_mode(struct axgbe_phy_data * phy_data __rte_unused,int speed)1438 static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data
1439 __rte_unused,
1440 int speed)
1441 {
1442 switch (speed) {
1443 case SPEED_100:
1444 return AXGBE_MODE_SGMII_100;
1445 case SPEED_1000:
1446 return AXGBE_MODE_SGMII_1000;
1447 case SPEED_10000:
1448 return AXGBE_MODE_KR;
1449 default:
1450 return AXGBE_MODE_UNKNOWN;
1451 }
1452 }
1453
axgbe_phy_get_sfp_mode(struct axgbe_phy_data * phy_data,int speed)1454 static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data,
1455 int speed)
1456 {
1457 switch (speed) {
1458 case SPEED_100:
1459 return AXGBE_MODE_SGMII_100;
1460 case SPEED_1000:
1461 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T)
1462 return AXGBE_MODE_SGMII_1000;
1463 else
1464 return AXGBE_MODE_X;
1465 case SPEED_10000:
1466 case SPEED_UNKNOWN:
1467 return AXGBE_MODE_SFI;
1468 default:
1469 return AXGBE_MODE_UNKNOWN;
1470 }
1471 }
1472
axgbe_phy_get_bp_2500_mode(int speed)1473 static enum axgbe_mode axgbe_phy_get_bp_2500_mode(int speed)
1474 {
1475 switch (speed) {
1476 case SPEED_2500:
1477 return AXGBE_MODE_KX_2500;
1478 default:
1479 return AXGBE_MODE_UNKNOWN;
1480 }
1481 }
1482
axgbe_phy_get_bp_mode(int speed)1483 static enum axgbe_mode axgbe_phy_get_bp_mode(int speed)
1484 {
1485 switch (speed) {
1486 case SPEED_1000:
1487 return AXGBE_MODE_KX_1000;
1488 case SPEED_10000:
1489 return AXGBE_MODE_KR;
1490 default:
1491 return AXGBE_MODE_UNKNOWN;
1492 }
1493 }
1494
axgbe_phy_get_mode(struct axgbe_port * pdata,int speed)1495 static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata,
1496 int speed)
1497 {
1498 struct axgbe_phy_data *phy_data = pdata->phy_data;
1499
1500 switch (phy_data->port_mode) {
1501 case AXGBE_PORT_MODE_BACKPLANE:
1502 return axgbe_phy_get_bp_mode(speed);
1503 case AXGBE_PORT_MODE_BACKPLANE_2500:
1504 return axgbe_phy_get_bp_2500_mode(speed);
1505 case AXGBE_PORT_MODE_1000BASE_T:
1506 case AXGBE_PORT_MODE_NBASE_T:
1507 case AXGBE_PORT_MODE_10GBASE_T:
1508 return axgbe_phy_get_baset_mode(phy_data, speed);
1509 case AXGBE_PORT_MODE_1000BASE_X:
1510 case AXGBE_PORT_MODE_10GBASE_R:
1511 return axgbe_phy_get_basex_mode(phy_data, speed);
1512 case AXGBE_PORT_MODE_SFP:
1513 return axgbe_phy_get_sfp_mode(phy_data, speed);
1514 default:
1515 return AXGBE_MODE_UNKNOWN;
1516 }
1517 }
1518
axgbe_phy_set_mode(struct axgbe_port * pdata,enum axgbe_mode mode)1519 static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode)
1520 {
1521 switch (mode) {
1522 case AXGBE_MODE_KR:
1523 axgbe_phy_kr_mode(pdata);
1524 break;
1525 case AXGBE_MODE_SFI:
1526 axgbe_phy_sfi_mode(pdata);
1527 break;
1528 case AXGBE_MODE_KX_2500:
1529 axgbe_phy_kx_2500_mode(pdata);
1530 break;
1531 case AXGBE_MODE_SGMII_1000:
1532 axgbe_phy_sgmii_1000_mode(pdata);
1533 break;
1534 default:
1535 break;
1536 }
1537 }
1538
axgbe_phy_check_mode(struct axgbe_port * pdata,enum axgbe_mode mode,u32 advert)1539 static bool axgbe_phy_check_mode(struct axgbe_port *pdata,
1540 enum axgbe_mode mode, u32 advert)
1541 {
1542 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
1543 if (pdata->phy.advertising & advert)
1544 return true;
1545 } else {
1546 enum axgbe_mode cur_mode;
1547
1548 cur_mode = axgbe_phy_get_mode(pdata, pdata->phy.speed);
1549 if (cur_mode == mode)
1550 return true;
1551 }
1552
1553 return false;
1554 }
1555
axgbe_phy_use_basex_mode(struct axgbe_port * pdata,enum axgbe_mode mode)1556 static bool axgbe_phy_use_basex_mode(struct axgbe_port *pdata,
1557 enum axgbe_mode mode)
1558 {
1559 switch (mode) {
1560 case AXGBE_MODE_X:
1561 return axgbe_phy_check_mode(pdata, mode,
1562 ADVERTISED_1000baseT_Full);
1563 case AXGBE_MODE_KR:
1564 return axgbe_phy_check_mode(pdata, mode,
1565 ADVERTISED_10000baseT_Full);
1566 default:
1567 return false;
1568 }
1569 }
1570
axgbe_phy_use_baset_mode(struct axgbe_port * pdata,enum axgbe_mode mode)1571 static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata,
1572 enum axgbe_mode mode)
1573 {
1574 switch (mode) {
1575 case AXGBE_MODE_SGMII_100:
1576 return axgbe_phy_check_mode(pdata, mode,
1577 ADVERTISED_100baseT_Full);
1578 case AXGBE_MODE_SGMII_1000:
1579 return axgbe_phy_check_mode(pdata, mode,
1580 ADVERTISED_1000baseT_Full);
1581 case AXGBE_MODE_KR:
1582 return axgbe_phy_check_mode(pdata, mode,
1583 ADVERTISED_10000baseT_Full);
1584 default:
1585 return false;
1586 }
1587 }
1588
axgbe_phy_use_sfp_mode(struct axgbe_port * pdata,enum axgbe_mode mode)1589 static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata,
1590 enum axgbe_mode mode)
1591 {
1592 struct axgbe_phy_data *phy_data = pdata->phy_data;
1593
1594 switch (mode) {
1595 case AXGBE_MODE_X:
1596 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T)
1597 return false;
1598 return axgbe_phy_check_mode(pdata, mode,
1599 ADVERTISED_1000baseT_Full);
1600 case AXGBE_MODE_SGMII_100:
1601 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
1602 return false;
1603 return axgbe_phy_check_mode(pdata, mode,
1604 ADVERTISED_100baseT_Full);
1605 case AXGBE_MODE_SGMII_1000:
1606 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)
1607 return false;
1608 return axgbe_phy_check_mode(pdata, mode,
1609 ADVERTISED_1000baseT_Full);
1610 case AXGBE_MODE_SFI:
1611 return axgbe_phy_check_mode(pdata, mode,
1612 ADVERTISED_10000baseT_Full);
1613 default:
1614 return false;
1615 }
1616 }
1617
axgbe_phy_use_bp_2500_mode(struct axgbe_port * pdata,enum axgbe_mode mode)1618 static bool axgbe_phy_use_bp_2500_mode(struct axgbe_port *pdata,
1619 enum axgbe_mode mode)
1620 {
1621 switch (mode) {
1622 case AXGBE_MODE_KX_2500:
1623 return axgbe_phy_check_mode(pdata, mode,
1624 ADVERTISED_2500baseX_Full);
1625 default:
1626 return false;
1627 }
1628 }
1629
axgbe_phy_use_bp_mode(struct axgbe_port * pdata,enum axgbe_mode mode)1630 static bool axgbe_phy_use_bp_mode(struct axgbe_port *pdata,
1631 enum axgbe_mode mode)
1632 {
1633 switch (mode) {
1634 case AXGBE_MODE_KX_1000:
1635 return axgbe_phy_check_mode(pdata, mode,
1636 ADVERTISED_1000baseKX_Full);
1637 case AXGBE_MODE_KR:
1638 return axgbe_phy_check_mode(pdata, mode,
1639 ADVERTISED_10000baseKR_Full);
1640 default:
1641 return false;
1642 }
1643 }
1644
axgbe_phy_use_mode(struct axgbe_port * pdata,enum axgbe_mode mode)1645 static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode)
1646 {
1647 struct axgbe_phy_data *phy_data = pdata->phy_data;
1648
1649 switch (phy_data->port_mode) {
1650 case AXGBE_PORT_MODE_BACKPLANE:
1651 return axgbe_phy_use_bp_mode(pdata, mode);
1652 case AXGBE_PORT_MODE_BACKPLANE_2500:
1653 return axgbe_phy_use_bp_2500_mode(pdata, mode);
1654 case AXGBE_PORT_MODE_1000BASE_T:
1655 case AXGBE_PORT_MODE_NBASE_T:
1656 case AXGBE_PORT_MODE_10GBASE_T:
1657 return axgbe_phy_use_baset_mode(pdata, mode);
1658 case AXGBE_PORT_MODE_1000BASE_X:
1659 case AXGBE_PORT_MODE_10GBASE_R:
1660 return axgbe_phy_use_basex_mode(pdata, mode);
1661 case AXGBE_PORT_MODE_SFP:
1662 return axgbe_phy_use_sfp_mode(pdata, mode);
1663 default:
1664 return false;
1665 }
1666 }
1667
axgbe_phy_link_status(struct axgbe_port * pdata,int * an_restart)1668 static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart)
1669 {
1670 struct axgbe_phy_data *phy_data = pdata->phy_data;
1671 unsigned int reg;
1672
1673 *an_restart = 0;
1674
1675 if (phy_data->port_mode == AXGBE_PORT_MODE_SFP) {
1676 /* Check SFP signals */
1677 axgbe_phy_sfp_detect(pdata);
1678
1679 if (phy_data->sfp_changed) {
1680 *an_restart = 1;
1681 return 0;
1682 }
1683
1684 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
1685 return 0;
1686 }
1687
1688 /* Link status is latched low, so read once to clear
1689 * and then read again to get current state
1690 */
1691 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1692 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1693 if (reg & MDIO_STAT1_LSTATUS)
1694 return 1;
1695
1696 /* No link, attempt a receiver reset cycle */
1697 if (phy_data->rrc_count++) {
1698 phy_data->rrc_count = 0;
1699 axgbe_phy_rrc(pdata);
1700 }
1701
1702 return 0;
1703 }
1704
axgbe_phy_sfp_gpio_setup(struct axgbe_port * pdata)1705 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata)
1706 {
1707 struct axgbe_phy_data *phy_data = pdata->phy_data;
1708 unsigned int reg;
1709
1710 reg = XP_IOREAD(pdata, XP_PROP_3);
1711
1712 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 +
1713 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR);
1714
1715 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK);
1716
1717 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3,
1718 GPIO_RX_LOS);
1719 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3,
1720 GPIO_TX_FAULT);
1721 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3,
1722 GPIO_MOD_ABS);
1723 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3,
1724 GPIO_RATE_SELECT);
1725 }
1726
axgbe_phy_sfp_comm_setup(struct axgbe_port * pdata)1727 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata)
1728 {
1729 struct axgbe_phy_data *phy_data = pdata->phy_data;
1730 unsigned int reg, mux_addr_hi, mux_addr_lo;
1731
1732 reg = XP_IOREAD(pdata, XP_PROP_4);
1733
1734 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI);
1735 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO);
1736 if (mux_addr_lo == AXGBE_SFP_DIRECT)
1737 return;
1738
1739 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545;
1740 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
1741 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN);
1742 }
1743
axgbe_phy_sfp_setup(struct axgbe_port * pdata)1744 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata)
1745 {
1746 axgbe_phy_sfp_comm_setup(pdata);
1747 axgbe_phy_sfp_gpio_setup(pdata);
1748 }
1749
axgbe_phy_redrv_error(struct axgbe_phy_data * phy_data)1750 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data)
1751 {
1752 if (!phy_data->redrv)
1753 return false;
1754
1755 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX)
1756 return true;
1757
1758 switch (phy_data->redrv_model) {
1759 case AXGBE_PHY_REDRV_MODEL_4223:
1760 if (phy_data->redrv_lane > 3)
1761 return true;
1762 break;
1763 case AXGBE_PHY_REDRV_MODEL_4227:
1764 if (phy_data->redrv_lane > 1)
1765 return true;
1766 break;
1767 default:
1768 return true;
1769 }
1770
1771 return false;
1772 }
1773
axgbe_phy_mdio_reset_setup(struct axgbe_port * pdata)1774 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata)
1775 {
1776 struct axgbe_phy_data *phy_data = pdata->phy_data;
1777 unsigned int reg;
1778
1779 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO)
1780 return 0;
1781 reg = XP_IOREAD(pdata, XP_PROP_3);
1782 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET);
1783 switch (phy_data->mdio_reset) {
1784 case AXGBE_MDIO_RESET_NONE:
1785 case AXGBE_MDIO_RESET_I2C_GPIO:
1786 case AXGBE_MDIO_RESET_INT_GPIO:
1787 break;
1788 default:
1789 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n",
1790 phy_data->mdio_reset);
1791 return -EINVAL;
1792 }
1793 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) {
1794 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 +
1795 XP_GET_BITS(reg, XP_PROP_3,
1796 MDIO_RESET_I2C_ADDR);
1797 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
1798 MDIO_RESET_I2C_GPIO);
1799 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) {
1800 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
1801 MDIO_RESET_INT_GPIO);
1802 }
1803
1804 return 0;
1805 }
1806
axgbe_phy_port_mode_mismatch(struct axgbe_port * pdata)1807 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata)
1808 {
1809 struct axgbe_phy_data *phy_data = pdata->phy_data;
1810
1811 switch (phy_data->port_mode) {
1812 case AXGBE_PORT_MODE_BACKPLANE:
1813 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1814 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1815 return false;
1816 break;
1817 case AXGBE_PORT_MODE_BACKPLANE_2500:
1818 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)
1819 return false;
1820 break;
1821 case AXGBE_PORT_MODE_1000BASE_T:
1822 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1823 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000))
1824 return false;
1825 break;
1826 case AXGBE_PORT_MODE_1000BASE_X:
1827 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)
1828 return false;
1829 break;
1830 case AXGBE_PORT_MODE_NBASE_T:
1831 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1832 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1833 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500))
1834 return false;
1835 break;
1836 case AXGBE_PORT_MODE_10GBASE_T:
1837 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1838 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1839 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1840 return false;
1841 break;
1842 case AXGBE_PORT_MODE_10GBASE_R:
1843 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)
1844 return false;
1845 break;
1846 case AXGBE_PORT_MODE_SFP:
1847 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||
1848 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
1849 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
1850 return false;
1851 break;
1852 default:
1853 break;
1854 }
1855
1856 return true;
1857 }
1858
axgbe_phy_conn_type_mismatch(struct axgbe_port * pdata)1859 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata)
1860 {
1861 struct axgbe_phy_data *phy_data = pdata->phy_data;
1862
1863 switch (phy_data->port_mode) {
1864 case AXGBE_PORT_MODE_BACKPLANE:
1865 case AXGBE_PORT_MODE_BACKPLANE_2500:
1866 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE)
1867 return false;
1868 break;
1869 case AXGBE_PORT_MODE_1000BASE_T:
1870 case AXGBE_PORT_MODE_1000BASE_X:
1871 case AXGBE_PORT_MODE_NBASE_T:
1872 case AXGBE_PORT_MODE_10GBASE_T:
1873 case AXGBE_PORT_MODE_10GBASE_R:
1874 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO)
1875 return false;
1876 break;
1877 case AXGBE_PORT_MODE_SFP:
1878 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP)
1879 return false;
1880 break;
1881 default:
1882 break;
1883 }
1884
1885 return true;
1886 }
1887
axgbe_phy_port_enabled(struct axgbe_port * pdata)1888 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata)
1889 {
1890 unsigned int reg;
1891
1892 reg = XP_IOREAD(pdata, XP_PROP_0);
1893 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS))
1894 return false;
1895 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE))
1896 return false;
1897
1898 return true;
1899 }
1900
axgbe_phy_cdr_track(struct axgbe_port * pdata)1901 static void axgbe_phy_cdr_track(struct axgbe_port *pdata)
1902 {
1903 struct axgbe_phy_data *phy_data = pdata->phy_data;
1904
1905 if (!pdata->vdata->an_cdr_workaround)
1906 return;
1907
1908 if (!phy_data->phy_cdr_notrack)
1909 return;
1910
1911 rte_delay_us(phy_data->phy_cdr_delay + 400);
1912
1913 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
1914 AXGBE_PMA_CDR_TRACK_EN_MASK,
1915 AXGBE_PMA_CDR_TRACK_EN_ON);
1916
1917 phy_data->phy_cdr_notrack = 0;
1918 }
1919
axgbe_phy_cdr_notrack(struct axgbe_port * pdata)1920 static void axgbe_phy_cdr_notrack(struct axgbe_port *pdata)
1921 {
1922 struct axgbe_phy_data *phy_data = pdata->phy_data;
1923
1924 if (!pdata->vdata->an_cdr_workaround)
1925 return;
1926
1927 if (phy_data->phy_cdr_notrack)
1928 return;
1929
1930 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
1931 AXGBE_PMA_CDR_TRACK_EN_MASK,
1932 AXGBE_PMA_CDR_TRACK_EN_OFF);
1933
1934 axgbe_phy_rrc(pdata);
1935
1936 phy_data->phy_cdr_notrack = 1;
1937 }
1938
axgbe_phy_kr_training_post(struct axgbe_port * pdata)1939 static void axgbe_phy_kr_training_post(struct axgbe_port *pdata)
1940 {
1941 if (!pdata->cdr_track_early)
1942 axgbe_phy_cdr_track(pdata);
1943 }
1944
axgbe_phy_kr_training_pre(struct axgbe_port * pdata)1945 static void axgbe_phy_kr_training_pre(struct axgbe_port *pdata)
1946 {
1947 if (pdata->cdr_track_early)
1948 axgbe_phy_cdr_track(pdata);
1949 }
1950
axgbe_phy_an_post(struct axgbe_port * pdata)1951 static void axgbe_phy_an_post(struct axgbe_port *pdata)
1952 {
1953 struct axgbe_phy_data *phy_data = pdata->phy_data;
1954
1955 switch (pdata->an_mode) {
1956 case AXGBE_AN_MODE_CL73:
1957 case AXGBE_AN_MODE_CL73_REDRV:
1958 if (phy_data->cur_mode != AXGBE_MODE_KR)
1959 break;
1960
1961 axgbe_phy_cdr_track(pdata);
1962
1963 switch (pdata->an_result) {
1964 case AXGBE_AN_READY:
1965 case AXGBE_AN_COMPLETE:
1966 break;
1967 default:
1968 if (phy_data->phy_cdr_delay < AXGBE_CDR_DELAY_MAX)
1969 phy_data->phy_cdr_delay += AXGBE_CDR_DELAY_INC;
1970 break;
1971 }
1972 break;
1973 default:
1974 break;
1975 }
1976 }
1977
axgbe_phy_an_pre(struct axgbe_port * pdata)1978 static void axgbe_phy_an_pre(struct axgbe_port *pdata)
1979 {
1980 struct axgbe_phy_data *phy_data = pdata->phy_data;
1981
1982 switch (pdata->an_mode) {
1983 case AXGBE_AN_MODE_CL73:
1984 case AXGBE_AN_MODE_CL73_REDRV:
1985 if (phy_data->cur_mode != AXGBE_MODE_KR)
1986 break;
1987
1988 axgbe_phy_cdr_notrack(pdata);
1989 break;
1990 default:
1991 break;
1992 }
1993 }
1994
axgbe_phy_stop(struct axgbe_port * pdata)1995 static void axgbe_phy_stop(struct axgbe_port *pdata)
1996 {
1997 struct axgbe_phy_data *phy_data = pdata->phy_data;
1998
1999 /* Reset SFP data */
2000 axgbe_phy_sfp_reset(phy_data);
2001 axgbe_phy_sfp_mod_absent(pdata);
2002
2003 /* Reset CDR support */
2004 axgbe_phy_cdr_track(pdata);
2005
2006 /* Power off the PHY */
2007 axgbe_phy_power_off(pdata);
2008
2009 /* Stop the I2C controller */
2010 pdata->i2c_if.i2c_stop(pdata);
2011 }
2012
axgbe_phy_start(struct axgbe_port * pdata)2013 static int axgbe_phy_start(struct axgbe_port *pdata)
2014 {
2015 struct axgbe_phy_data *phy_data = pdata->phy_data;
2016 int ret;
2017
2018 /* Start the I2C controller */
2019 ret = pdata->i2c_if.i2c_start(pdata);
2020 if (ret)
2021 return ret;
2022
2023 /* Start in highest supported mode */
2024 axgbe_phy_set_mode(pdata, phy_data->start_mode);
2025
2026 /* Reset CDR support */
2027 axgbe_phy_cdr_track(pdata);
2028
2029 /* After starting the I2C controller, we can check for an SFP */
2030 switch (phy_data->port_mode) {
2031 case AXGBE_PORT_MODE_SFP:
2032 axgbe_phy_sfp_detect(pdata);
2033 break;
2034 default:
2035 break;
2036 }
2037 pdata->phy.advertising &= axgbe_phy_an_advertising(pdata);
2038
2039 return ret;
2040 }
2041
axgbe_phy_reset(struct axgbe_port * pdata)2042 static int axgbe_phy_reset(struct axgbe_port *pdata)
2043 {
2044 struct axgbe_phy_data *phy_data = pdata->phy_data;
2045 enum axgbe_mode cur_mode;
2046
2047 /* Reset by power cycling the PHY */
2048 cur_mode = phy_data->cur_mode;
2049 axgbe_phy_power_off(pdata);
2050 /* First time reset is done with passed unknown mode*/
2051 axgbe_phy_set_mode(pdata, cur_mode);
2052 return 0;
2053 }
2054
axgbe_phy_init(struct axgbe_port * pdata)2055 static int axgbe_phy_init(struct axgbe_port *pdata)
2056 {
2057 struct axgbe_phy_data *phy_data;
2058 unsigned int reg;
2059 int ret;
2060
2061 /* Check if enabled */
2062 if (!axgbe_phy_port_enabled(pdata)) {
2063 PMD_DRV_LOG(ERR, "device is not enabled\n");
2064 return -ENODEV;
2065 }
2066
2067 /* Initialize the I2C controller */
2068 ret = pdata->i2c_if.i2c_init(pdata);
2069 if (ret)
2070 return ret;
2071
2072 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0);
2073 if (!phy_data) {
2074 PMD_DRV_LOG(ERR, "phy_data allocation failed\n");
2075 return -ENOMEM;
2076 }
2077 pdata->phy_data = phy_data;
2078
2079 reg = XP_IOREAD(pdata, XP_PROP_0);
2080 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE);
2081 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
2082 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS);
2083 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE);
2084 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR);
2085
2086 reg = XP_IOREAD(pdata, XP_PROP_4);
2087 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT);
2088 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF);
2089 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR);
2090 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE);
2091 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL);
2092
2093 /* Validate the connection requested */
2094 if (axgbe_phy_conn_type_mismatch(pdata)) {
2095 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n",
2096 phy_data->port_mode, phy_data->conn_type);
2097 return -EINVAL;
2098 }
2099
2100 /* Validate the mode requested */
2101 if (axgbe_phy_port_mode_mismatch(pdata)) {
2102 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n",
2103 phy_data->port_mode, phy_data->port_speeds);
2104 return -EINVAL;
2105 }
2106
2107 /* Check for and validate MDIO reset support */
2108 ret = axgbe_phy_mdio_reset_setup(pdata);
2109 if (ret)
2110 return ret;
2111
2112 /* Validate the re-driver information */
2113 if (axgbe_phy_redrv_error(phy_data)) {
2114 PMD_DRV_LOG(ERR, "phy re-driver settings error\n");
2115 return -EINVAL;
2116 }
2117 pdata->kr_redrv = phy_data->redrv;
2118
2119 /* Indicate current mode is unknown */
2120 phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
2121
2122 /* Initialize supported features */
2123 pdata->phy.supported = 0;
2124
2125 switch (phy_data->port_mode) {
2126 /* Backplane support */
2127 case AXGBE_PORT_MODE_BACKPLANE:
2128 pdata->phy.supported |= SUPPORTED_Autoneg;
2129 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2130 pdata->phy.supported |= SUPPORTED_Backplane;
2131 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2132 pdata->phy.supported |= SUPPORTED_1000baseKX_Full;
2133 phy_data->start_mode = AXGBE_MODE_KX_1000;
2134 }
2135 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2136 pdata->phy.supported |= SUPPORTED_10000baseKR_Full;
2137 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2138 pdata->phy.supported |=
2139 SUPPORTED_10000baseR_FEC;
2140 phy_data->start_mode = AXGBE_MODE_KR;
2141 }
2142
2143 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2144 break;
2145 case AXGBE_PORT_MODE_BACKPLANE_2500:
2146 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2147 pdata->phy.supported |= SUPPORTED_Backplane;
2148 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
2149 phy_data->start_mode = AXGBE_MODE_KX_2500;
2150
2151 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2152 break;
2153
2154 /* MDIO 1GBase-T support */
2155 case AXGBE_PORT_MODE_1000BASE_T:
2156 pdata->phy.supported |= SUPPORTED_Autoneg;
2157 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2158 pdata->phy.supported |= SUPPORTED_TP;
2159 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2160 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2161 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2162 }
2163 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2164 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2165 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2166 }
2167
2168 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2169 break;
2170
2171 /* MDIO Base-X support */
2172 case AXGBE_PORT_MODE_1000BASE_X:
2173 pdata->phy.supported |= SUPPORTED_Autoneg;
2174 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2175 pdata->phy.supported |= SUPPORTED_FIBRE;
2176 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2177 phy_data->start_mode = AXGBE_MODE_X;
2178
2179 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2180 break;
2181
2182 /* MDIO NBase-T support */
2183 case AXGBE_PORT_MODE_NBASE_T:
2184 pdata->phy.supported |= SUPPORTED_Autoneg;
2185 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2186 pdata->phy.supported |= SUPPORTED_TP;
2187 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2188 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2189 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2190 }
2191 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2192 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2193 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2194 }
2195 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) {
2196 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
2197 phy_data->start_mode = AXGBE_MODE_KX_2500;
2198 }
2199
2200 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45;
2201 break;
2202
2203 /* 10GBase-T support */
2204 case AXGBE_PORT_MODE_10GBASE_T:
2205 pdata->phy.supported |= SUPPORTED_Autoneg;
2206 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2207 pdata->phy.supported |= SUPPORTED_TP;
2208 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2209 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2210 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2211 }
2212 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2213 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2214 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2215 }
2216 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2217 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2218 phy_data->start_mode = AXGBE_MODE_KR;
2219 }
2220
2221 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2222 break;
2223
2224 /* 10GBase-R support */
2225 case AXGBE_PORT_MODE_10GBASE_R:
2226 pdata->phy.supported |= SUPPORTED_Autoneg;
2227 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2228 pdata->phy.supported |= SUPPORTED_TP;
2229 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2230 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2231 pdata->phy.supported |= SUPPORTED_10000baseR_FEC;
2232 phy_data->start_mode = AXGBE_MODE_SFI;
2233
2234 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE;
2235 break;
2236
2237 /* SFP support */
2238 case AXGBE_PORT_MODE_SFP:
2239 pdata->phy.supported |= SUPPORTED_Autoneg;
2240 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
2241 pdata->phy.supported |= SUPPORTED_TP;
2242 pdata->phy.supported |= SUPPORTED_FIBRE;
2243 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {
2244 pdata->phy.supported |= SUPPORTED_100baseT_Full;
2245 phy_data->start_mode = AXGBE_MODE_SGMII_100;
2246 }
2247 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
2248 pdata->phy.supported |= SUPPORTED_1000baseT_Full;
2249 phy_data->start_mode = AXGBE_MODE_SGMII_1000;
2250 }
2251 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) {
2252 pdata->phy.supported |= SUPPORTED_10000baseT_Full;
2253 phy_data->start_mode = AXGBE_MODE_SFI;
2254 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2255 pdata->phy.supported |=
2256 SUPPORTED_10000baseR_FEC;
2257 }
2258
2259 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22;
2260
2261 axgbe_phy_sfp_setup(pdata);
2262 break;
2263 default:
2264 return -EINVAL;
2265 }
2266
2267 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) &&
2268 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) {
2269 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
2270 phy_data->phydev_mode);
2271 if (ret) {
2272 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n",
2273 phy_data->mdio_addr, phy_data->phydev_mode);
2274 return -EINVAL;
2275 }
2276 }
2277
2278 if (phy_data->redrv && !phy_data->redrv_if) {
2279 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
2280 AXGBE_MDIO_MODE_CL22);
2281 if (ret) {
2282 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n",
2283 phy_data->redrv_addr);
2284 return -EINVAL;
2285 }
2286 }
2287
2288 phy_data->phy_cdr_delay = AXGBE_CDR_DELAY_INIT;
2289 return 0;
2290 }
axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if * phy_if)2291 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if)
2292 {
2293 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
2294
2295 phy_impl->init = axgbe_phy_init;
2296 phy_impl->reset = axgbe_phy_reset;
2297 phy_impl->start = axgbe_phy_start;
2298 phy_impl->stop = axgbe_phy_stop;
2299 phy_impl->link_status = axgbe_phy_link_status;
2300 phy_impl->use_mode = axgbe_phy_use_mode;
2301 phy_impl->set_mode = axgbe_phy_set_mode;
2302 phy_impl->get_mode = axgbe_phy_get_mode;
2303 phy_impl->switch_mode = axgbe_phy_switch_mode;
2304 phy_impl->cur_mode = axgbe_phy_cur_mode;
2305 phy_impl->an_mode = axgbe_phy_an_mode;
2306 phy_impl->an_config = axgbe_phy_an_config;
2307 phy_impl->an_advertising = axgbe_phy_an_advertising;
2308 phy_impl->an_outcome = axgbe_phy_an_outcome;
2309
2310 phy_impl->an_pre = axgbe_phy_an_pre;
2311 phy_impl->an_post = axgbe_phy_an_post;
2312
2313 phy_impl->kr_training_pre = axgbe_phy_kr_training_pre;
2314 phy_impl->kr_training_post = axgbe_phy_kr_training_post;
2315 }
2316