| /f-stack/dpdk/drivers/raw/octeontx2_ep/ |
| H A D | otx2_ep_vf.c | 23 otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no)); in sdp_vf_reset_iq() 32 otx2_write64(d64, sdpvf->hw_addr + in sdp_vf_reset_iq() 44 otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no)); in sdp_vf_reset_iq() 53 otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_PKT_CNT(q_no)); in sdp_vf_reset_iq() 76 otx2_write64(d64, sdpvf->hw_addr + in sdp_vf_reset_oq() 88 otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no)); in sdp_vf_reset_oq() 223 otx2_write64(iq->base_addr_dma, sdpvf->hw_addr + in sdp_vf_setup_iq_regs() 225 otx2_write64(iq->nb_desc, sdpvf->hw_addr + in sdp_vf_setup_iq_regs() 270 otx2_write64(droq->desc_ring_dma, sdpvf->hw_addr + in sdp_vf_setup_oq_regs() 272 otx2_write64(droq->nb_desc, sdpvf->hw_addr + in sdp_vf_setup_oq_regs() [all …]
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| H A D | otx2_ep_enqdeq.c | 475 otx2_write64(iq->fill_cnt, iq->doorbell_reg); in sdp_ring_doorbell()
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| /f-stack/dpdk/drivers/mempool/octeontx2/ |
| H A D | otx2_mempool_irq.c | 27 otx2_write64(intr, lf->base + NPA_LF_ERR_INT); in npa_lf_err_irq() 75 otx2_write64(intr, lf->base + NPA_LF_RAS); in npa_lf_ras_irq() 87 otx2_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1C); in npa_lf_register_ras_irq() 91 otx2_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1S); in npa_lf_register_ras_irq() 105 otx2_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1C); in npa_lf_unregister_ras_irq() 126 otx2_write64(wdata | qint, lf->base + off); in npa_lf_q_irq_get_and_clear() 218 otx2_write64(0, lf->base + NPA_LF_QINTX_CNT(q)); in npa_lf_register_queue_irqs() 237 otx2_write64(0, lf->base + NPA_LF_QINTX_CNT(q)); in npa_lf_register_queue_irqs() 238 otx2_write64(0, lf->base + NPA_LF_QINTX_INT(q)); in npa_lf_register_queue_irqs() 259 otx2_write64(0, lf->base + NPA_LF_QINTX_CNT(q)); in npa_lf_unregister_queue_irqs() [all …]
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| H A D | otx2_mempool.h | 138 otx2_write64(reg, in npa_lf_aura_op_cnt_set() 167 otx2_write64(reg, in npa_lf_aura_op_limit_set()
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| /f-stack/dpdk/drivers/net/octeontx2/ |
| H A D | otx2_ethdev_irq.c | 26 otx2_write64(intr, dev->base + NIX_LF_ERR_INT); in nix_lf_err_irq() 82 otx2_write64(intr, dev->base + NIX_LF_RAS); in nix_lf_ras_irq() 141 otx2_write64(wdata | qint, dev->base + off); in nix_lf_q_irq_get_and_clear() 281 otx2_write64(0, dev->base + NIX_LF_QINTX_CNT(q)); in oxt2_nix_register_queue_irqs() 298 otx2_write64(0, dev->base + NIX_LF_QINTX_CNT(q)); in oxt2_nix_register_queue_irqs() 299 otx2_write64(0, dev->base + NIX_LF_QINTX_INT(q)); in oxt2_nix_register_queue_irqs() 319 otx2_write64(0, dev->base + NIX_LF_QINTX_CNT(q)); in oxt2_nix_unregister_queue_irqs() 381 otx2_write64(((CQ_CQE_THRESH_DEFAULT) | in oxt2_nix_register_cq_irqs() 451 otx2_write64(BIT_ULL(0), dev->base + in otx2_nix_rx_queue_intr_enable() 464 otx2_write64(BIT_ULL(0), dev->base + in otx2_nix_rx_queue_intr_disable() [all …]
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| H A D | otx2_rx.c | 84 otx2_write64((wdata | nb_pkts), rxq->cq_door); in nix_recv_pkts() 308 otx2_write64((rxq->wdata | packets), rxq->cq_door); in nix_recv_pkts_vector()
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| H A D | otx2_rss.c | 161 otx2_write64(val, dev->base + NIX_LF_RX_SECRETX(idx)); in otx2_nix_rss_set_key()
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| /f-stack/dpdk/drivers/event/octeontx2/ |
| H A D | otx2_evdev_irq.c | 24 otx2_write64(intr, base + SSO_LF_GGRP_INT); in sso_lf_irq() 38 otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1C); in sso_lf_register_irq() 42 otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1S); in sso_lf_register_irq() 61 otx2_write64(intr, base + SSOW_LF_GWS_INT); in ssow_lf_irq() 75 otx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1C); in ssow_lf_register_irq() 79 otx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1S); in ssow_lf_register_irq() 95 otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1C); in sso_lf_unregister_irq() 193 otx2_write64(intr, base + TIM_LF_NRSPERR_INT); in tim_lf_irq() 194 otx2_write64(intr, base + TIM_LF_RAS_INT); in tim_lf_irq() 207 otx2_write64(~0ull, base + TIM_LF_NRSPERR_INT); in tim_lf_register_irq() [all …]
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| H A D | otx2_worker.h | 27 otx2_write64(BIT_ULL(16) | /* wait for work. */ in otx2_ssogws_get_work() 178 otx2_write64(val, ws->swtag_desched_op); in otx2_ssogws_swtag_desched() 187 otx2_write64(val, ws->swtag_norm_op); in otx2_ssogws_swtag_norm() 193 otx2_write64(0, OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op) + in otx2_ssogws_swtag_untag() 205 otx2_write64(0, ws->swtag_flush_op); in otx2_ssogws_swtag_flush() 212 otx2_write64(0, OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op) + in otx2_ssogws_desched()
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| H A D | otx2_worker.c | 55 otx2_write64(ev->u64, OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op) + in otx2_ssogws_fwd_group() 333 otx2_write64(val, ws->getwrk_op); in ssogws_flush_events() 347 otx2_write64(0, OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op) + in ssogws_flush_events()
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| H A D | otx2_worker_dual.h | 55 otx2_write64(set_gw, ws_pair->getwrk_op); in otx2_ssogws_dual_get_work()
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| H A D | otx2_evdev.c | 519 otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG); in sso_port_link_modify() 1283 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR( in otx2_sso_port_setup() 1285 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR( in otx2_sso_port_setup() 1296 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM); in otx2_sso_port_setup() 1479 otx2_write64(enable, ws->grps_base[i] + in sso_cleanup() 1492 otx2_write64(enable, ws->grps_base[i] + in sso_cleanup()
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| H A D | otx2_tim_evdev.c | 371 otx2_write64((uint64_t)tim_ring->bkt, in otx2_tim_ring_create() 373 otx2_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA); in otx2_tim_ring_create()
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| H A D | otx2_worker_dual.c | 55 otx2_write64(ev->u64, OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op) + in otx2_ssogws_dual_fwd_group()
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| /f-stack/dpdk/drivers/crypto/octeontx2/ |
| H A D | otx2_cryptodev_hw_access.c | 31 otx2_write64(intr, base + OTX2_CPT_LF_MISC_INT); in otx2_cpt_lf_err_intr_handler() 42 otx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1C); in otx2_cpt_lf_err_intr_unregister() 72 otx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1C); in otx2_cpt_lf_err_intr_register() 81 otx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1S); in otx2_cpt_lf_err_intr_register() 163 otx2_write64(base.u, qp->base + OTX2_CPT_LF_Q_BASE); in otx2_cpt_iq_enable() 169 otx2_write64(size.u, qp->base + OTX2_CPT_LF_Q_SIZE); in otx2_cpt_iq_enable() 175 otx2_write64(lf_ctl.u, qp->base + OTX2_CPT_LF_CTL); in otx2_cpt_iq_enable() 181 otx2_write64(inprog.u, qp->base + OTX2_CPT_LF_INPROG); in otx2_cpt_iq_enable() 197 otx2_write64(inprog.u, qp->base + OTX2_CPT_LF_INPROG); in otx2_cpt_iq_disable() 202 otx2_write64(ctl.u, qp->base + OTX2_CPT_LF_CTL); in otx2_cpt_iq_disable()
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| /f-stack/dpdk/drivers/regex/octeontx2/ |
| H A D | otx2_regexdev_hw_access.c | 26 otx2_write64(intr, base + OTX2_REE_LF_MISC_INT); in ree_lf_err_intr_handler() 37 otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1C); in ree_lf_err_intr_unregister() 68 otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1C); in ree_lf_err_intr_register() 77 otx2_write64(~0ull, base + OTX2_REE_LF_MISC_INT_ENA_W1S); in ree_lf_err_intr_register() 132 otx2_write64(base.u, qp->base + OTX2_REE_LF_SBUF_ADDR); in otx2_ree_iq_enable() 138 otx2_write64(lf_ena.u, qp->base + OTX2_REE_LF_ENA); in otx2_ree_iq_enable() 151 otx2_write64(lf_ena.u, qp->base + OTX2_REE_LF_ENA); in otx2_ree_iq_disable()
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| H A D | otx2_regexdev.c | 395 otx2_write64(count, qp->base + OTX2_REE_LF_DOORBELL); in otx2_ree_enqueue_burst()
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| /f-stack/dpdk/drivers/common/octeontx2/ |
| H A D | otx2_dev.c | 84 otx2_write64(int_status, dev->bar2 + RVU_PF_INT); in pf_af_sync_msg() 133 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT); in af_pf_wait_msg() 584 otx2_write64(intr, dev->bar2 + RVU_VF_INT); in otx2_pf_vf_mbox_irq() 604 otx2_write64(intr, dev->bar2 + RVU_PF_INT); in otx2_af_pf_mbox_irq() 622 otx2_write64(~0ull, dev->bar2 + in mbox_register_pf_irq() 655 otx2_write64(~0ull, dev->bar2 + in mbox_register_pf_irq() 658 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT); in mbox_register_pf_irq() 682 otx2_write64(~0ull, dev->bar2 + RVU_VF_INT); in mbox_register_vf_irq() 705 otx2_write64(~0ull, dev->bar2 + in mbox_unregister_pf_irq() 798 otx2_write64(BIT_ULL(vf), in otx2_pf_vf_flr_irq() [all …]
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| H A D | otx2_common.h | 164 #define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr)) macro
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| H A D | otx2_mbox.c | 277 otx2_write64(rsp_reg, reg_addr); in mbox_poll()
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| /f-stack/dpdk/drivers/raw/octeontx2_dma/ |
| H A D | otx2_dpi_rawdev.c | 37 otx2_write64(0x1, dpivf->vf_bar0 + DPI_VDMA_EN); in dma_engine_enb_dis() 39 otx2_write64(0x0, dpivf->vf_bar0 + DPI_VDMA_EN); in dma_engine_enb_dis() 145 otx2_write64((uint64_t)cmd_count, in dma_queue_submit() 319 otx2_write64(0x0, dpivf->vf_bar0 + DPI_VDMA_EN); in otx2_dpi_rawdev_configure() 323 otx2_write64(0, dpivf->vf_bar0 + DPI_VDMA_REQQ_CTL); in otx2_dpi_rawdev_configure() 324 otx2_write64(((uint64_t)buf >> 7) << 7, in otx2_dpi_rawdev_configure()
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