Searched refs:nlw (Results 1 – 3 of 3) sorted by relevance
443 switch (pciercx_cfg032.s.nlw) in __cvmx_pcie_rc_initialize_link_gen1()831 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw); in __cvmx_pcie_rc_initialize_gen1()874 switch (pciercx_cfg032.s.nlw) in __cvmx_pcie_rc_initialize_link_gen2()1181 …Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.l… in __cvmx_pcie_rc_initialize_gen2()
3080 uint32_t nlw : 6; /**< Negotiated Link Width member3122 uint32_t nlw : 6;3146 uint32_t nlw : 6; /**< Negotiated Link Width member3179 uint32_t nlw : 6;3210 uint32_t nlw : 6; /**< Negotiated Link Width member3251 uint32_t nlw : 6;
2743 uint32_t nlw : 6; /**< Negotiated Link Width member2785 uint32_t nlw : 6;