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Searched refs:mux_reg (Results 1 – 13 of 13) sorted by relevance

/f-stack/freebsd/arm/freescale/imx/
H A Dimx_iomux.c94 uint32_t mux_reg; member
165 WR4(sc, cfg->mux_reg, cfg->mux_val | sion); in iomux_configure_pins()
175 name, cfg->mux_reg, cfg->mux_val | sion, in iomux_configure_pins()
/f-stack/freebsd/contrib/device-tree/Bindings/pinctrl/
H A Dfsl,imx8mp-pinctrl.yaml35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
44 "mux_reg" indicates the offset of mux register.
H A Dfsl,imx8mm-pinctrl.yaml35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
44 "mux_reg" indicates the offset of mux register.
H A Dfsl,imx8mn-pinctrl.yaml35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
44 "mux_reg" indicates the offset of mux register.
H A Dfsl,imx8mq-pinctrl.yaml35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
44 "mux_reg" indicates the offset of mux register.
H A Dfsl,imx6sx-pinctrl.txt9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
H A Dfsl,imx6sll-pinctrl.txt9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
H A Dfsl,imx6ul-pinctrl.txt10 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
H A Dfsl,imx7d-pinctrl.txt32 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
H A Dfsl,imx-pinctrl.txt26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
/f-stack/freebsd/mips/ingenic/
H A Djz4780_clk_gen.c116 reg = CLK_RD_4(sc, sc->clk_descr->clk_mux.mux_reg); in jz4780_clk_gen_init()
252 reg = CLK_RD_4(sc, sc->clk_descr->clk_mux.mux_reg); in jz4780_clk_gen_set_mux()
255 CLK_WR_4(sc, sc->clk_descr->clk_mux.mux_reg, reg); in jz4780_clk_gen_set_mux()
H A Djz4780_clk.h50 uint16_t mux_reg; member
H A Djz4780_clock.c104 .clk_mux.mux_reg = (reg), \