1 /* $NetBSD: uart.c,v 1.2 2007/03/23 20:05:47 dogcow Exp $ */
2
3 /*-
4 * Copyright (c) 2013, Alexander A. Mityaev <[email protected]>
5 * Copyright (c) 2010 Aleksandr Rybalko.
6 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
7 * Copyright (c) 2007 Oleksandr Tymoshenko.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer in the documentation and/or other materials provided
18 * with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
31 * OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36
37 #include "opt_ddb.h"
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/bus.h>
42 #include <sys/conf.h>
43 #include <sys/kdb.h>
44 #include <sys/reboot.h>
45 #include <sys/sysctl.h>
46 #include <sys/kernel.h>
47 #include <machine/bus.h>
48 #include <machine/fdt.h>
49
50 #include <dev/uart/uart.h>
51 #include <dev/uart/uart_cpu.h>
52 #include <dev/uart/uart_cpu_fdt.h>
53 #include <dev/uart/uart_bus.h>
54
55 #include <mips/mediatek/uart_dev_mtk.h>
56 #include <mips/mediatek/mtk_soc.h>
57 #include <mips/mediatek/mtk_sysctl.h>
58
59 #include "uart_if.h"
60
61 /* Set some reference clock value. Real value will be taken from FDT */
62 #define DEFAULT_RCLK (120 * 1000 * 1000)
63
64 /*
65 * Low-level UART interface.
66 */
67 static int mtk_uart_probe(struct uart_bas *bas);
68 static void mtk_uart_init(struct uart_bas *bas, int, int, int, int);
69 static void mtk_uart_term(struct uart_bas *bas);
70 static void mtk_uart_putc(struct uart_bas *bas, int);
71 static int mtk_uart_rxready(struct uart_bas *bas);
72 static int mtk_uart_getc(struct uart_bas *bas, struct mtx *);
73
74 static struct uart_ops uart_mtk_ops = {
75 .probe = mtk_uart_probe,
76 .init = mtk_uart_init,
77 .term = mtk_uart_term,
78 .putc = mtk_uart_putc,
79 .rxready = mtk_uart_rxready,
80 .getc = mtk_uart_getc,
81 };
82
83 static int uart_output = 1;
84 TUNABLE_INT("kern.uart_output", &uart_output);
85 SYSCTL_INT(_kern, OID_AUTO, uart_output, CTLFLAG_RW,
86 &uart_output, 0, "UART output enabled.");
87
88 static int
mtk_uart_probe(struct uart_bas * bas)89 mtk_uart_probe(struct uart_bas *bas)
90 {
91 return (0);
92 }
93
94 static void
mtk_uart_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)95 mtk_uart_init(struct uart_bas *bas, int baudrate, int databits,
96 int stopbits, int parity)
97 {
98 /* CLKDIV = 384000000/ 3/ 16/ br */
99 /* for 384MHz CLKDIV = 8000000 / baudrate; */
100 switch (databits) {
101 case 5:
102 databits = UART_LCR_5B;
103 break;
104 case 6:
105 databits = UART_LCR_6B;
106 break;
107 case 7:
108 databits = UART_LCR_7B;
109 break;
110 case 8:
111 databits = UART_LCR_8B;
112 break;
113 default:
114 /* Unsupported */
115 return;
116 }
117 switch (parity) {
118 case UART_PARITY_EVEN: parity = (UART_LCR_PEN|UART_LCR_EVEN); break;
119 case UART_PARITY_ODD: parity = (UART_LCR_PEN); break;
120 case UART_PARITY_NONE: parity = 0; break;
121 /* Unsupported */
122 default: return;
123 }
124
125 if (bas->rclk && baudrate) {
126 uart_setreg(bas, UART_CDDL_REG, bas->rclk/16/baudrate);
127 uart_barrier(bas);
128 }
129
130 uart_setreg(bas, UART_LCR_REG, databits |
131 (stopbits==1?0:UART_LCR_STB_15) |
132 parity);
133 uart_barrier(bas);
134 }
135
136 static void
mtk_uart_term(struct uart_bas * bas)137 mtk_uart_term(struct uart_bas *bas)
138 {
139 uart_setreg(bas, UART_MCR_REG, 0);
140 uart_barrier(bas);
141 }
142
143 static void
mtk_uart_putc(struct uart_bas * bas,int c)144 mtk_uart_putc(struct uart_bas *bas, int c)
145 {
146 char chr;
147 if (!uart_output) return;
148 chr = c;
149 while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));
150 uart_setreg(bas, UART_TX_REG, c);
151 uart_barrier(bas);
152 while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));
153 }
154
155 static int
mtk_uart_rxready(struct uart_bas * bas)156 mtk_uart_rxready(struct uart_bas *bas)
157 {
158 if (uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)
159 return (1);
160 return (0);
161 }
162
163 static int
mtk_uart_getc(struct uart_bas * bas,struct mtx * hwmtx)164 mtk_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
165 {
166 int c;
167
168 uart_lock(hwmtx);
169
170 while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)) {
171 uart_unlock(hwmtx);
172 DELAY(10);
173 uart_lock(hwmtx);
174 }
175
176 c = uart_getreg(bas, UART_RX_REG);
177
178 uart_unlock(hwmtx);
179
180 return (c);
181 }
182
183 /*
184 * High-level UART interface.
185 */
186 struct uart_mtk_softc {
187 struct uart_softc base;
188 uint8_t ier_mask;
189 uint8_t ier;
190 };
191
192 static int mtk_uart_bus_attach(struct uart_softc *);
193 static int mtk_uart_bus_detach(struct uart_softc *);
194 static int mtk_uart_bus_flush(struct uart_softc *, int);
195 static int mtk_uart_bus_getsig(struct uart_softc *);
196 static int mtk_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
197 static int mtk_uart_bus_ipend(struct uart_softc *);
198 static int mtk_uart_bus_param(struct uart_softc *, int, int, int, int);
199 static int mtk_uart_bus_probe(struct uart_softc *);
200 static int mtk_uart_bus_receive(struct uart_softc *);
201 static int mtk_uart_bus_setsig(struct uart_softc *, int);
202 static int mtk_uart_bus_transmit(struct uart_softc *);
203 static void mtk_uart_bus_grab(struct uart_softc *);
204 static void mtk_uart_bus_ungrab(struct uart_softc *);
205
206 static kobj_method_t uart_mtk_methods[] = {
207 KOBJMETHOD(uart_attach, mtk_uart_bus_attach),
208 KOBJMETHOD(uart_detach, mtk_uart_bus_detach),
209 KOBJMETHOD(uart_flush, mtk_uart_bus_flush),
210 KOBJMETHOD(uart_getsig, mtk_uart_bus_getsig),
211 KOBJMETHOD(uart_ioctl, mtk_uart_bus_ioctl),
212 KOBJMETHOD(uart_ipend, mtk_uart_bus_ipend),
213 KOBJMETHOD(uart_param, mtk_uart_bus_param),
214 KOBJMETHOD(uart_probe, mtk_uart_bus_probe),
215 KOBJMETHOD(uart_receive, mtk_uart_bus_receive),
216 KOBJMETHOD(uart_setsig, mtk_uart_bus_setsig),
217 KOBJMETHOD(uart_transmit, mtk_uart_bus_transmit),
218 KOBJMETHOD(uart_grab, mtk_uart_bus_grab),
219 KOBJMETHOD(uart_ungrab, mtk_uart_bus_ungrab),
220 { 0, 0 }
221 };
222
223 struct uart_class uart_mtk_class = {
224 "uart_mtk",
225 uart_mtk_methods,
226 sizeof(struct uart_mtk_softc),
227 .uc_ops = &uart_mtk_ops,
228 .uc_range = 1, /* use hinted range */
229 .uc_rclk = 0
230 };
231
232 static struct ofw_compat_data compat_data[] = {
233 { "ralink,rt2880-uart", (uintptr_t)&uart_mtk_class },
234 { "ralink,rt3050-uart", (uintptr_t)&uart_mtk_class },
235 { "ralink,rt3352-uart", (uintptr_t)&uart_mtk_class },
236 { "ralink,rt3883-uart", (uintptr_t)&uart_mtk_class },
237 { "ralink,rt5350-uart", (uintptr_t)&uart_mtk_class },
238 { "ralink,mt7620a-uart", (uintptr_t)&uart_mtk_class },
239 { NULL, (uintptr_t)NULL },
240 };
241 UART_FDT_CLASS_AND_DEVICE(compat_data);
242
243 #define SIGCHG(c, i, s, d) \
244 if (c) { \
245 i |= (i & s) ? s : s | d; \
246 } else { \
247 i = (i & s) ? (i & ~s) | d : i; \
248 }
249
250 /*
251 * Disable TX interrupt. uart should be locked
252 */
253 static __inline void
mtk_uart_disable_txintr(struct uart_softc * sc)254 mtk_uart_disable_txintr(struct uart_softc *sc)
255 {
256 struct uart_bas *bas = &sc->sc_bas;
257 uint8_t cr;
258
259 cr = uart_getreg(bas, UART_IER_REG);
260 cr &= ~UART_IER_ETBEI;
261 uart_setreg(bas, UART_IER_REG, cr);
262 uart_barrier(bas);
263 }
264
265 /*
266 * Enable TX interrupt. uart should be locked
267 */
268 static __inline void
mtk_uart_enable_txintr(struct uart_softc * sc)269 mtk_uart_enable_txintr(struct uart_softc *sc)
270 {
271 struct uart_bas *bas = &sc->sc_bas;
272 uint8_t cr;
273
274 cr = uart_getreg(bas, UART_IER_REG);
275 cr |= UART_IER_ETBEI;
276 uart_setreg(bas, UART_IER_REG, cr);
277 uart_barrier(bas);
278 }
279
280 static int
mtk_uart_bus_attach(struct uart_softc * sc)281 mtk_uart_bus_attach(struct uart_softc *sc)
282 {
283 struct uart_bas *bas;
284 struct uart_devinfo *di;
285 struct uart_mtk_softc *usc = (struct uart_mtk_softc *)sc;
286
287 bas = &sc->sc_bas;
288
289 if (!bas->rclk) {
290 bas->rclk = mtk_soc_get_uartclk();
291 }
292
293 if (sc->sc_sysdev != NULL) {
294 di = sc->sc_sysdev;
295 mtk_uart_init(bas, di->baudrate, di->databits, di->stopbits,
296 di->parity);
297 } else {
298 mtk_uart_init(bas, 57600, 8, 1, 0);
299 }
300
301 sc->sc_rxfifosz = 16;
302 sc->sc_txfifosz = 16;
303
304 (void)mtk_uart_bus_getsig(sc);
305
306 /* Enable FIFO */
307 uart_setreg(bas, UART_FCR_REG,
308 uart_getreg(bas, UART_FCR_REG) |
309 UART_FCR_FIFOEN | UART_FCR_TXTGR_1 | UART_FCR_RXTGR_1);
310 uart_barrier(bas);
311 /* Enable interrupts */
312 usc->ier_mask = 0xf0;
313 uart_setreg(bas, UART_IER_REG,
314 UART_IER_EDSSI | UART_IER_ELSI | UART_IER_ERBFI);
315 uart_barrier(bas);
316
317 return (0);
318 }
319
320 static int
mtk_uart_bus_detach(struct uart_softc * sc)321 mtk_uart_bus_detach(struct uart_softc *sc)
322 {
323 return (0);
324 }
325
326 static int
mtk_uart_bus_flush(struct uart_softc * sc,int what)327 mtk_uart_bus_flush(struct uart_softc *sc, int what)
328 {
329 struct uart_bas *bas = &sc->sc_bas;
330 uint32_t fcr = uart_getreg(bas, UART_FCR_REG);
331
332 if (what & UART_FLUSH_TRANSMITTER) {
333 uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_TXRST);
334 uart_barrier(bas);
335 }
336 if (what & UART_FLUSH_RECEIVER) {
337 uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_RXRST);
338 uart_barrier(bas);
339 }
340 uart_setreg(bas, UART_FCR_REG, fcr);
341 uart_barrier(bas);
342 return (0);
343 }
344
345 static int
mtk_uart_bus_getsig(struct uart_softc * sc)346 mtk_uart_bus_getsig(struct uart_softc *sc)
347 {
348 uint32_t new, old, sig;
349 uint8_t bes;
350
351 return(0);
352 do {
353 old = sc->sc_hwsig;
354 sig = old;
355 uart_lock(sc->sc_hwmtx);
356 bes = uart_getreg(&sc->sc_bas, UART_MSR_REG);
357 uart_unlock(sc->sc_hwmtx);
358 /* XXX: chip can show delta */
359 SIGCHG(bes & UART_MSR_CTS, sig, SER_CTS, SER_DCTS);
360 SIGCHG(bes & UART_MSR_DCD, sig, SER_DCD, SER_DDCD);
361 SIGCHG(bes & UART_MSR_DSR, sig, SER_DSR, SER_DDSR);
362 new = sig & ~SER_MASK_DELTA;
363 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
364
365 return (sig);
366 }
367
368 static int
mtk_uart_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)369 mtk_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
370 {
371 struct uart_bas *bas;
372 int baudrate, divisor, error;
373
374 bas = &sc->sc_bas;
375 error = 0;
376 uart_lock(sc->sc_hwmtx);
377 switch (request) {
378 case UART_IOCTL_BREAK:
379 /* TODO: Send BREAK */
380 break;
381 case UART_IOCTL_BAUD:
382 divisor = uart_getreg(bas, UART_CDDL_REG);
383 baudrate = bas->rclk / (divisor * 16);
384 *(int*)data = baudrate;
385 break;
386 default:
387 error = EINVAL;
388 break;
389 }
390 uart_unlock(sc->sc_hwmtx);
391 return (error);
392 }
393
394 static int
mtk_uart_bus_ipend(struct uart_softc * sc)395 mtk_uart_bus_ipend(struct uart_softc *sc)
396 {
397 struct uart_bas *bas;
398 int ipend;
399 uint8_t iir, lsr, msr;
400
401 // breakpoint();
402
403 bas = &sc->sc_bas;
404 ipend = 0;
405
406 uart_lock(sc->sc_hwmtx);
407 iir = uart_getreg(&sc->sc_bas, UART_IIR_REG);
408 lsr = uart_getreg(&sc->sc_bas, UART_LSR_REG);
409 uart_setreg(&sc->sc_bas, UART_LSR_REG, lsr);
410 msr = uart_getreg(&sc->sc_bas, UART_MSR_REG);
411 uart_setreg(&sc->sc_bas, UART_MSR_REG, msr);
412 if (iir & UART_IIR_INTP) {
413 uart_unlock(sc->sc_hwmtx);
414 return (0);
415 }
416 switch ((iir >> 1) & 0x07) {
417 case UART_IIR_ID_THRE:
418 ipend |= SER_INT_TXIDLE;
419 break;
420 case UART_IIR_ID_DR2:
421 mtk_uart_bus_flush(sc, UART_FLUSH_RECEIVER);
422 /* passthrough */
423 case UART_IIR_ID_DR:
424 ipend |= SER_INT_RXREADY;
425 break;
426 case UART_IIR_ID_MST:
427 case UART_IIR_ID_LINESTATUS:
428 ipend |= SER_INT_SIGCHG;
429 if (lsr & UART_LSR_BI)
430 ipend |= SER_INT_BREAK;
431 if (lsr & UART_LSR_OE)
432 ipend |= SER_INT_OVERRUN;
433 break;
434 default:
435 /* XXX: maybe return error here */
436 break;
437 }
438
439 uart_unlock(sc->sc_hwmtx);
440
441 return (ipend);
442 }
443
444 static int
mtk_uart_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)445 mtk_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
446 int stopbits, int parity)
447 {
448 uart_lock(sc->sc_hwmtx);
449 mtk_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
450 uart_unlock(sc->sc_hwmtx);
451 return (0);
452 }
453
454 static int
mtk_uart_bus_probe(struct uart_softc * sc)455 mtk_uart_bus_probe(struct uart_softc *sc)
456 {
457 int error;
458
459 error = mtk_uart_probe(&sc->sc_bas);
460 if (error)
461 return (error);
462
463 device_set_desc(sc->sc_dev, "MTK UART Controller");
464
465 return (0);
466 }
467
468 static int
mtk_uart_bus_receive(struct uart_softc * sc)469 mtk_uart_bus_receive(struct uart_softc *sc)
470 {
471 struct uart_bas *bas;
472 int xc;
473 uint8_t lsr;
474
475 bas = &sc->sc_bas;
476 uart_lock(sc->sc_hwmtx);
477 lsr = uart_getreg(bas, UART_LSR_REG);
478 while ((lsr & UART_LSR_DR)) {
479 if (uart_rx_full(sc)) {
480 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
481 break;
482 }
483 xc = 0;
484 xc = uart_getreg(bas, UART_RX_REG);
485 if (lsr & UART_LSR_FE)
486 xc |= UART_STAT_FRAMERR;
487 if (lsr & UART_LSR_PE)
488 xc |= UART_STAT_PARERR;
489 if (lsr & UART_LSR_OE)
490 xc |= UART_STAT_OVERRUN;
491 uart_barrier(bas);
492 uart_rx_put(sc, xc);
493 lsr = uart_getreg(bas, UART_LSR_REG);
494 }
495
496 uart_unlock(sc->sc_hwmtx);
497 return (0);
498 }
499
500 static int
mtk_uart_bus_setsig(struct uart_softc * sc,int sig)501 mtk_uart_bus_setsig(struct uart_softc *sc, int sig)
502 {
503 /* TODO: implement (?) */
504 return (sig);
505 }
506
507 static int
mtk_uart_bus_transmit(struct uart_softc * sc)508 mtk_uart_bus_transmit(struct uart_softc *sc)
509 {
510 struct uart_bas *bas = &sc->sc_bas;
511 int i;
512
513 if (!uart_output) return (0);
514
515 bas = &sc->sc_bas;
516 uart_lock(sc->sc_hwmtx);
517 while ((uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE) == 0);
518 mtk_uart_enable_txintr(sc);
519 for (i = 0; i < sc->sc_txdatasz; i++) {
520 uart_setreg(bas, UART_TX_REG, sc->sc_txbuf[i]);
521 uart_barrier(bas);
522 }
523 sc->sc_txbusy = 1;
524 uart_unlock(sc->sc_hwmtx);
525 return (0);
526 }
527
528 void
mtk_uart_bus_grab(struct uart_softc * sc)529 mtk_uart_bus_grab(struct uart_softc *sc)
530 {
531 struct uart_bas *bas = &sc->sc_bas;
532 struct uart_mtk_softc *usc = (struct uart_mtk_softc *)sc;
533
534 uart_lock(sc->sc_hwmtx);
535 usc->ier = uart_getreg(bas, UART_IER_REG);
536 uart_setreg(bas, UART_IER_REG, usc->ier & usc->ier_mask);
537 uart_barrier(bas);
538 uart_unlock(sc->sc_hwmtx);
539 }
540
541 void
mtk_uart_bus_ungrab(struct uart_softc * sc)542 mtk_uart_bus_ungrab(struct uart_softc *sc)
543 {
544 struct uart_mtk_softc *usc = (struct uart_mtk_softc *)sc;
545 struct uart_bas *bas = &sc->sc_bas;
546
547 uart_lock(sc->sc_hwmtx);
548 uart_setreg(bas, UART_IER_REG, usc->ier);
549 uart_barrier(bas);
550 uart_unlock(sc->sc_hwmtx);
551 }
552