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Searched refs:msr (Results 1 – 25 of 41) sorted by relevance

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/f-stack/freebsd/amd64/amd64/
H A Dinitcpu.c69 uint64_t msr; in init_amd() local
133 wrmsr(0xc001102a, msr); in init_amd()
156 msr |= 0x2000; in init_amd()
157 wrmsr(MSR_DE_CFG, msr); in init_amd()
161 msr |= 0x10; in init_amd()
162 wrmsr(MSR_LS_CFG, msr); in init_amd()
166 msr |= 0x10; in init_amd()
167 wrmsr(0xc0011028, msr); in init_amd()
172 wrmsr(MSR_LS_CFG, msr); in init_amd()
256 uint64_t msr; in initializecpu() local
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/f-stack/freebsd/x86/cpufreq/
H A Dhwpstate_amd.c82 #define AMD_10H_11H_GET_PSTATE_LIMIT(msr) (((msr)) & 0x7) argument
84 #define AMD_10H_11H_CUR_VID(msr) (((msr) >> 9) & 0x7F) argument
85 #define AMD_10H_11H_CUR_DID(msr) (((msr) >> 6) & 0x07) argument
86 #define AMD_10H_11H_CUR_FID(msr) ((msr) & 0x3F) argument
88 #define AMD_17H_CUR_VID(msr) (((msr) >> 14) & 0xFF) argument
89 #define AMD_17H_CUR_DID(msr) (((msr) >> 8) & 0x3F) argument
90 #define AMD_17H_CUR_FID(msr) ((msr) & 0xFF) argument
176 uint64_t msr; in hwpstate_goto_pstate() local
268 uint64_t msr; in hwpstate_get() local
353 uint64_t msr; in hwpstate_probe() local
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H A Dp4tcc.c264 uint64_t mask, msr; in p4tcc_set() local
285 msr = rdmsr(MSR_THERM_CONTROL); in p4tcc_set()
287 msr &= ~(mask | TCC_ENABLE_ONDEMAND); in p4tcc_set()
289 msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND; in p4tcc_set()
290 wrmsr(MSR_THERM_CONTROL, msr); in p4tcc_set()
299 if (msr & TCC_ENABLE_ONDEMAND) in p4tcc_set()
311 uint64_t msr; in p4tcc_get() local
327 msr = rdmsr(MSR_THERM_CONTROL); in p4tcc_get()
328 val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1); in p4tcc_get()
H A Dest.c958 uint64_t msr; in est_probe() local
1040 uint64_t msr; in est_get_info() local
1135 id = msr >> 32; in est_table_info()
1185 id = msr >> 32; in est_msr_info()
1190 id = msr >> 48; in est_msr_info()
1197 id = msr >> 32; in est_msr_info()
1219 id = msr >> 48; in est_msr_info()
1249 uint64_t msr; in est_set_id16() local
1254 msr = rdmsr(MSR_PERF_CTL); in est_set_id16()
1255 msr = (msr & ~0xffff) | id16; in est_set_id16()
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/f-stack/freebsd/amd64/vmm/
H A Dvmm_lapic.c141 x2apic_msr(u_int msr) in x2apic_msr() argument
143 return (msr >= 0x800 && msr <= 0xBFF); in x2apic_msr()
147 x2apic_msr_to_regoff(u_int msr) in x2apic_msr_to_regoff() argument
150 return ((msr - 0x800) << 4); in x2apic_msr_to_regoff()
154 lapic_msr(u_int msr) in lapic_msr() argument
157 return (x2apic_msr(msr) || msr == MSR_APICBASE); in lapic_msr()
169 if (msr == MSR_APICBASE) { in lapic_rdmsr()
173 offset = x2apic_msr_to_regoff(msr); in lapic_rdmsr()
181 lapic_wrmsr(struct vm *vm, int cpu, u_int msr, uint64_t val, bool *retu) in lapic_wrmsr() argument
189 if (msr == MSR_APICBASE) { in lapic_wrmsr()
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H A Dvmm_lapic.h37 int lapic_rdmsr(struct vm *vm, int cpu, u_int msr, uint64_t *rval,
39 int lapic_wrmsr(struct vm *vm, int cpu, u_int msr, uint64_t wval,
/f-stack/freebsd/x86/x86/
H A Dx86_mem.c205 int i, j, msr; in x86_mrfetch() local
213 msrv = rdmsr(msr); in x86_mrfetch()
225 msrv = rdmsr(msr); in x86_mrfetch()
237 msrv = rdmsr(msr); in x86_mrfetch()
252 msrv = rdmsr(msr); in x86_mrfetch()
326 int i, j, msr; in x86_mrstoreone() local
359 wrmsr(msr, msrv); in x86_mrstoreone()
371 wrmsr(msr, msrv); in x86_mrstoreone()
383 wrmsr(msr, msrv); in x86_mrstoreone()
392 omsrv = rdmsr(msr); in x86_mrstoreone()
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H A Didentcpu.c1521 uint64_t msr; in fix_cpuid() local
1536 msr &= ~IA32_MISC_EN_LIMCPUID; in fix_cpuid()
1551 msr = rdmsr(MSR_EXTFEATURES); in fix_cpuid()
1553 msr |= (uint64_t)1 << 54; in fix_cpuid()
1554 wrmsr(MSR_EXTFEATURES, msr); in fix_cpuid()
2331 uint64_t msr; in print_svm_info() local
2338 msr = rdmsr(MSR_VM_CR); in print_svm_info()
2467 val = rdmsr(msr); in vmx_settable()
2476 uint64_t basic, msr; in print_vmx_info() local
2626 mask = msr; in print_vmx_info()
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H A Dcpu_machdep.c115 u_int msr; member
129 v = rdmsr(a->msr); in x86_msr_op_one()
131 wrmsr(a->msr, v); in x86_msr_op_one()
134 v = rdmsr(a->msr); in x86_msr_op_one()
136 wrmsr(a->msr, v); in x86_msr_op_one()
139 wrmsr(a->msr, a->arg1); in x86_msr_op_one()
148 x86_msr_op(u_int msr, u_int op, uint64_t arg1) in x86_msr_op() argument
161 a.msr = msr; in x86_msr_op()
597 uint64_t msr; in cpu_idle() local
622 msr = rdmsr(MSR_AMDK8_IPM); in cpu_idle()
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/f-stack/freebsd/arm64/arm64/
H A Dlocore.S68 msr sctlr_el1, x2
171 msr daifset, #2
229 msr hcr_el2, x2
233 msr vpidr_el2, x2
241 msr sctlr_el1, x2
245 msr cptr_el2, x2
248 msr hstr_el2, xzr
261 msr vbar_el2, x2
264 msr spsr_el2, x2
281 msr elr_el2, x30
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H A Dswtch.S44 msr mdscr_el1, \tmp
53 msr mdscr_el1, \tmp
90 msr tpidr_el0, x6
92 msr tpidrro_el0, x6
187 msr tpidr_el0, x6
189 msr tpidrro_el0, x6
236 msr daifset, #2
240 msr sp_el0, x0
245 msr elr_el1, x0
246 msr spsr_el1, x1
H A Dexception.S80 msr daifclr, #8 /* Enable the debug exception */
90 msr daifset, #10
107 msr sp_el0, x18
109 msr spsr_el1, x11
110 msr elr_el1, x10
148 msr daifset, #10
161 msr daif, x19
/f-stack/freebsd/amd64/vmm/intel/
H A Dvmx_msr.h66 int msr_bitmap_change_access(char *bitmap, u_int msr, int access);
68 #define guest_msr_rw(vmx, msr) \ argument
69 msr_bitmap_change_access((vmx)->msr_bitmap, (msr), MSR_BITMAP_ACCESS_RW)
71 #define guest_msr_ro(vmx, msr) \ argument
72 msr_bitmap_change_access((vmx)->msr_bitmap, (msr), MSR_BITMAP_ACCESS_READ)
H A Dvmx_msr.c148 msr_bitmap_change_access(char *bitmap, u_int msr, int access) in msr_bitmap_change_access() argument
152 if (msr <= 0x00001FFF) in msr_bitmap_change_access()
153 byte = msr / 8; in msr_bitmap_change_access()
154 else if (msr >= 0xC0000000 && msr <= 0xC0001FFF) in msr_bitmap_change_access()
155 byte = 1024 + (msr - 0xC0000000) / 8; in msr_bitmap_change_access()
159 bit = msr & 0x7; in msr_bitmap_change_access()
/f-stack/freebsd/contrib/openzfs/include/os/linux/kernel/linux/
H A Dsimd_powerpc.h88 u64 msr; in zfs_altivec_available() local
90 u32 msr; in zfs_altivec_available() local
93 __asm volatile("mfmsr %0" : "=r"(msr)); in zfs_altivec_available()
103 res = (msr & 0x2000000) != 0; in zfs_altivec_available()
/f-stack/freebsd/arm/arm/
H A Dsetstack.s68 msr cpsr_fsxc, r2
72 msr cpsr_fsxc, r3 /* Restore the old mode */
87 msr cpsr_fsxc, r2
91 msr cpsr_fsxc, r3 /* Restore the old mode */
H A Dexception.S99 msr spsr_fsxc, r0; \
122 msr cpsr_c, r2; /* Punch into SVC mode */ \
130 msr spsr_fsxc, r3; /* Restore correct spsr */ \
149 msr spsr_fsxc, r0; /* restore SPSR */ \
172 msr cpsr_c, r1; /* Disable interrupts */ \
182 msr cpsr_c, r4; /* Restore interrupts */ \
186 msr cpsr_c, r0; \
341 msr cpsr_c, r8 /* The r8 we trash here is the */
H A Dfiq_subr.S60 msr cpsr_fsxc, r2
63 msr cpsr_fsxc, r3
H A Dsetcpsr.S64 msr cpsr_fsxc, r2
/f-stack/freebsd/i386/i386/
H A Dinitcpu.c646 uint64_t msr; in initializecpu() local
768 msr = rdmsr(MSR_EFER) | EFER_NXE; in initializecpu()
769 wrmsr(MSR_EFER, msr); in initializecpu()
816 u_int64_t msr; in enable_K5_wt_alloc() local
825 msr = rdmsr(0x83); /* HWCR */ in enable_K5_wt_alloc()
826 wrmsr(0x83, msr & !(0x10)); in enable_K5_wt_alloc()
834 msr = Maxmem / 16; in enable_K5_wt_alloc()
836 msr = 0; in enable_K5_wt_alloc()
844 msr |= AMD_WT_ALLOC_PRE; in enable_K5_wt_alloc()
845 wrmsr(0x85, msr); in enable_K5_wt_alloc()
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H A Dlongrun.c75 u_int64_t msr; member
96 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN); in tmx86_get_longrun_mode()
144 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN); in tmx86_set_longrun_mode()
149 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr); in tmx86_set_longrun_mode()
152 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS); in tmx86_set_longrun_mode()
154 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr); in tmx86_set_longrun_mode()
/f-stack/dpdk/lib/librte_eal/x86/
H A Drte_cycles.c30 rdmsr(int msr, uint64_t *val) in rdmsr() argument
40 ret = pread(fd, val, sizeof(uint64_t), msr); in rdmsr()
46 RTE_SET_USED(msr); in rdmsr()
/f-stack/freebsd/i386/include/
H A Dcpufunc.h362 rdmsr(u_int msr) in rdmsr() argument
366 __asm __volatile("rdmsr" : "=A" (rv) : "c" (msr)); in rdmsr()
371 rdmsr32(u_int msr) in rdmsr32() argument
375 __asm __volatile("rdmsr" : "=a" (low) : "c" (msr) : "edx"); in rdmsr32()
437 wrmsr(u_int msr, uint64_t newval) in wrmsr() argument
439 __asm __volatile("wrmsr" : : "A" (newval), "c" (msr)); in wrmsr()
802 uint64_t rdmsr(u_int msr);
822 void wrmsr(u_int msr, uint64_t newval);
829 int rdmsr_safe(u_int msr, uint64_t *val);
830 int wrmsr_safe(u_int msr, uint64_t newval);
/f-stack/freebsd/amd64/include/
H A Dcpufunc.h323 rdmsr(u_int msr) in rdmsr() argument
327 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr)); in rdmsr()
332 rdmsr32(u_int msr) in rdmsr32() argument
336 __asm __volatile("rdmsr" : "=a" (low) : "c" (msr) : "rdx"); in rdmsr32()
398 wrmsr(u_int msr, uint64_t newval) in wrmsr() argument
404 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr)); in wrmsr()
992 uint64_t rdmsr(u_int msr);
993 uint32_t rdmsr32(u_int msr);
1007 void wrmsr(u_int msr, uint64_t newval);
1014 int rdmsr_safe(u_int msr, uint64_t *val);
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/f-stack/freebsd/amd64/vmm/amd/
H A Dsvm.c226 uint64_t msr; in svm_available() local
234 msr = rdmsr(MSR_VM_CR); in svm_available()
235 if ((msr & VM_CR_SVMDIS) != 0) { in svm_available()
323 *bit = (msr % 4) * 2; in svm_msr_index()
326 if (msr >= MSR_PENTIUM_START && msr <= MSR_PENTIUM_END) { in svm_msr_index()
327 *index = msr / 4; in svm_msr_index()
332 if (msr >= MSR_AMD6TH_START && msr <= MSR_AMD6TH_END) { in svm_msr_index()
339 if (msr >= MSR_AMD7TH_START && msr <= MSR_AMD7TH_END) { in svm_msr_index()
1473 vmexit->u.msr.code = ecx; in svm_vmexit()
1474 vmexit->u.msr.wval = val; in svm_vmexit()
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