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Searched refs:mmio_base (Results 1 – 5 of 5) sorted by relevance

/f-stack/dpdk/drivers/baseband/fpga_5gnr_fec/
H A Dfpga_5gnr_fec.h234 void *mmio_base; member
299 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_8()
307 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_16()
315 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_32()
323 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_64()
351 fpga_reg_read_32(void *mmio_base, uint32_t offset) in fpga_reg_read_32() argument
353 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_32()
364 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_16()
373 fpga_reg_read_8(void *mmio_base, uint32_t offset) in fpga_reg_read_8() argument
375 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_8()
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H A Drte_fpga_5gnr_fec.c40 PRIx32, mmio_base, offset); in print_ring_reg_debug_info()
43 fpga_reg_read_64(mmio_base, offset)); in print_ring_reg_debug_info()
46 fpga_reg_read_64(mmio_base, offset + in print_ring_reg_debug_info()
50 fpga_reg_read_16(mmio_base, offset + in print_ring_reg_debug_info()
54 fpga_reg_read_8(mmio_base, offset + in print_ring_reg_debug_info()
58 fpga_reg_read_8(mmio_base, offset + in print_ring_reg_debug_info()
62 fpga_reg_read_8(mmio_base, offset + in print_ring_reg_debug_info()
66 fpga_reg_read_16(mmio_base, offset + in print_ring_reg_debug_info()
70 fpga_reg_read_16(mmio_base, offset + in print_ring_reg_debug_info()
546 fpga_reg_write_8(d->mmio_base, in fpga_queue_release()
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/f-stack/dpdk/drivers/baseband/fpga_lte_fec/
H A Dfpga_lte_fec.c227 void *mmio_base; member
384 PRIx32, mmio_base, offset); in print_ring_reg_debug_info()
390 fpga_reg_read_64(mmio_base, offset + in print_ring_reg_debug_info()
394 fpga_reg_read_16(mmio_base, offset + in print_ring_reg_debug_info()
398 fpga_reg_read_8(mmio_base, offset + in print_ring_reg_debug_info()
402 fpga_reg_read_8(mmio_base, offset + in print_ring_reg_debug_info()
406 fpga_reg_read_8(mmio_base, offset + in print_ring_reg_debug_info()
410 fpga_reg_read_16(mmio_base, offset + in print_ring_reg_debug_info()
414 fpga_reg_read_16(mmio_base, offset + in print_ring_reg_debug_info()
818 fpga_reg_write_8(d->mmio_base, in fpga_queue_release()
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/f-stack/dpdk/drivers/baseband/acc100/
H A Drte_acc100_pmd.h563 void *mmio_base; /**< Base address of MMIO registers (BAR0) */ member
H A Drte_acc100_pmd.c43 void *reg_addr = RTE_PTR_ADD(d->mmio_base, offset); in acc100_reg_write()
53 void *reg_addr = RTE_PTR_ADD(d->mmio_base, offset); in acc100_reg_read()
930 q->mmio_reg_enqueue = RTE_PTR_ADD(d->mmio_base, in acc100_queue_setup()
4139 ((struct acc100_device *) dev->data->dev_private)->mmio_base = in acc100_bbdev_init()