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Searched refs:misses (Results 1 – 17 of 17) sorted by relevance

/f-stack/freebsd/contrib/device-tree/Bindings/perf/
H A Dnds32v3-pmu.txt3 NDS32 core have a PMU for counting cpu and cache events like cache misses.
/f-stack/freebsd/contrib/device-tree/Bindings/arc/
H A Darchs-pct.txt4 CPU and cache events like cache misses and hits. Like conventional PCT there
H A Dpct.txt4 CPU and cache events like cache misses and hits. Like conventional PCT there
/f-stack/dpdk/doc/guides/prog_guide/
H A Dprofile_app.rst23 * Cache misses
27 * DTLB misses
H A Dwriting_efficient_code.rst49 …ccess operations by several lcores to the same memory area can generate a lot of data cache misses,
H A Dring_lib.rst39 … in a table, a dequeue of several objects will not produce as many cache misses as in a linked que…
H A Dgraph_lib.rst36 caches misses.
H A Dqos_framework.rst403 …nt core, thus the above 3 memory accesses would result (on average) in L1 and L2 data cache misses.
404 A number of 3 L1/L2 cache misses per packet is not acceptable for performance reasons.
445 To avoid the cache misses, the above data structures (pipe, queue, queue array, mbufs) are prefetch…
H A Dpacket_framework.rst511 the number of L2 or L3 cache memory misses is greatly reduced, hence one of the main reasons for im…
/f-stack/app/redis-5.0.5/deps/jemalloc/
H A DTUNING.md29 metadata usually reduces TLB misses significantly, especially for programs
121 for frequently accessed data, which reduces TLB misses significantly.
/f-stack/freebsd/contrib/device-tree/Bindings/arm/
H A Dpmu.yaml14 ARM cores often have a PMU for counting cpu and cache events like cache misses
/f-stack/dpdk/doc/guides/sample_app_ug/
H A Dvm_power_management.rst132 branch misses to branch hits is very low, but when the core is
411 Specify the list of cores to monitor the ratio of branch misses
867 between branch hits and misses on a core
/f-stack/app/redis-5.0.5/src/
H A Dredis-cli.c6865 long long hits = 0, misses = 0; in LRUTestMode() local
6890 misses++; in LRUTestMode()
6907 hits+misses, in LRUTestMode()
6908 hits, (double)hits/(hits+misses)*100, in LRUTestMode()
6909 misses, (double)misses/(hits+misses)*100); in LRUTestMode()
/f-stack/freebsd/contrib/zstd/
H A DCONTRIBUTING.md334 if you expect the L1 cache misses to decrease with your change, you can look at the
335 counter `L1-dcache-load-misses`
/f-stack/dpdk/doc/guides/nics/
H A Dvirtio.rst454 this is to improve performance by avoiding cache misses and make it easier
/f-stack/app/redis-5.0.5/
H A D00-RELEASENOTES755 7. "key misses" stats accounting fixed. Many cache misses were not counted.
881 if we read a expired key, misses++
/f-stack/freebsd/contrib/openzfs/module/zfs/
H A Darc.c6299 metadata, misses); in arc_read()