1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation 3 */ 4 5 #ifndef _RTE_ETH_CTRL_H_ 6 #define _RTE_ETH_CTRL_H_ 7 8 #include <stdint.h> 9 #include <rte_common.h> 10 #include <rte_ether.h> 11 #include "rte_flow.h" 12 13 /** 14 * @deprecated Please use rte_flow API instead of this legacy one. 15 * @file 16 * 17 * Ethernet device features and related data structures used 18 * by control APIs should be defined in this file. 19 */ 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 /** 26 * Define all structures for ntuple Filter type. 27 */ 28 29 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001 /**< If set, dst_ip is part of ntuple */ 30 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002 /**< If set, src_ip is part of ntuple */ 31 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004 /**< If set, dst_port is part of ntuple */ 32 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008 /**< If set, src_port is part of ntuple */ 33 #define RTE_NTUPLE_FLAGS_PROTO 0x0010 /**< If set, protocol is part of ntuple */ 34 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020 /**< If set, tcp flag is involved */ 35 36 #define RTE_5TUPLE_FLAGS ( \ 37 RTE_NTUPLE_FLAGS_DST_IP | \ 38 RTE_NTUPLE_FLAGS_SRC_IP | \ 39 RTE_NTUPLE_FLAGS_DST_PORT | \ 40 RTE_NTUPLE_FLAGS_SRC_PORT | \ 41 RTE_NTUPLE_FLAGS_PROTO) 42 43 #define RTE_2TUPLE_FLAGS ( \ 44 RTE_NTUPLE_FLAGS_DST_PORT | \ 45 RTE_NTUPLE_FLAGS_PROTO) 46 47 #define RTE_NTUPLE_TCP_FLAGS_MASK 0x3F /**< TCP flags filter can match. */ 48 49 /** 50 * A structure used to define the ntuple filter entry 51 * to support RTE_ETH_FILTER_NTUPLE data representation. 52 */ 53 struct rte_eth_ntuple_filter { 54 uint16_t flags; /**< Flags from RTE_NTUPLE_FLAGS_* */ 55 uint32_t dst_ip; /**< Destination IP address in big endian. */ 56 uint32_t dst_ip_mask; /**< Mask of destination IP address. */ 57 uint32_t src_ip; /**< Source IP address in big endian. */ 58 uint32_t src_ip_mask; /**< Mask of destination IP address. */ 59 uint16_t dst_port; /**< Destination port in big endian. */ 60 uint16_t dst_port_mask; /**< Mask of destination port. */ 61 uint16_t src_port; /**< Source Port in big endian. */ 62 uint16_t src_port_mask; /**< Mask of source port. */ 63 uint8_t proto; /**< L4 protocol. */ 64 uint8_t proto_mask; /**< Mask of L4 protocol. */ 65 /** tcp_flags only meaningful when the proto is TCP. 66 The packet matched above ntuple fields and contain 67 any set bit in tcp_flags will hit this filter. */ 68 uint8_t tcp_flags; 69 uint16_t priority; /**< seven levels (001b-111b), 111b is highest, 70 used when more than one filter matches. */ 71 uint16_t queue; /**< Queue assigned to when match*/ 72 }; 73 74 #define RTE_ETH_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */ 75 #define RTE_ETH_INSET_SIZE_MAX 128 /**< Max length of input set. */ 76 77 /** 78 * Input set fields for Flow Director and Hash filters 79 */ 80 enum rte_eth_input_set_field { 81 RTE_ETH_INPUT_SET_UNKNOWN = 0, 82 83 /* L2 */ 84 RTE_ETH_INPUT_SET_L2_SRC_MAC = 1, 85 RTE_ETH_INPUT_SET_L2_DST_MAC, 86 RTE_ETH_INPUT_SET_L2_OUTER_VLAN, 87 RTE_ETH_INPUT_SET_L2_INNER_VLAN, 88 RTE_ETH_INPUT_SET_L2_ETHERTYPE, 89 90 /* L3 */ 91 RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129, 92 RTE_ETH_INPUT_SET_L3_DST_IP4, 93 RTE_ETH_INPUT_SET_L3_SRC_IP6, 94 RTE_ETH_INPUT_SET_L3_DST_IP6, 95 RTE_ETH_INPUT_SET_L3_IP4_TOS, 96 RTE_ETH_INPUT_SET_L3_IP4_PROTO, 97 RTE_ETH_INPUT_SET_L3_IP6_TC, 98 RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER, 99 RTE_ETH_INPUT_SET_L3_IP4_TTL, 100 RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS, 101 102 /* L4 */ 103 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257, 104 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, 105 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, 106 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, 107 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, 108 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, 109 RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG, 110 111 /* Tunnel */ 112 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385, 113 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC, 114 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN, 115 RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY, 116 RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, 117 118 /* Flexible Payload */ 119 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641, 120 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD, 121 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD, 122 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD, 123 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD, 124 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD, 125 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD, 126 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD, 127 128 RTE_ETH_INPUT_SET_DEFAULT = 65533, 129 RTE_ETH_INPUT_SET_NONE = 65534, 130 RTE_ETH_INPUT_SET_MAX = 65535, 131 }; 132 133 /** 134 * Filters input set operations 135 */ 136 enum rte_filter_input_set_op { 137 RTE_ETH_INPUT_SET_OP_UNKNOWN, 138 RTE_ETH_INPUT_SET_SELECT, /**< select input set */ 139 RTE_ETH_INPUT_SET_ADD, /**< add input set entry */ 140 RTE_ETH_INPUT_SET_OP_MAX 141 }; 142 143 144 /** 145 * A structure used to define the input set configuration for 146 * flow director and hash filters 147 */ 148 struct rte_eth_input_set_conf { 149 uint16_t flow_type; 150 uint16_t inset_size; 151 enum rte_eth_input_set_field field[RTE_ETH_INSET_SIZE_MAX]; 152 enum rte_filter_input_set_op op; 153 }; 154 155 /** 156 * A structure used to define the input for L2 flow 157 */ 158 struct rte_eth_l2_flow { 159 uint16_t ether_type; /**< Ether type in big endian */ 160 }; 161 162 /** 163 * A structure used to define the input for IPV4 flow 164 */ 165 struct rte_eth_ipv4_flow { 166 uint32_t src_ip; /**< IPv4 source address in big endian. */ 167 uint32_t dst_ip; /**< IPv4 destination address in big endian. */ 168 uint8_t tos; /**< Type of service to match. */ 169 uint8_t ttl; /**< Time to live to match. */ 170 uint8_t proto; /**< Protocol, next header in big endian. */ 171 }; 172 173 /** 174 * A structure used to define the input for IPV4 UDP flow 175 */ 176 struct rte_eth_udpv4_flow { 177 struct rte_eth_ipv4_flow ip; /**< IPv4 fields to match. */ 178 uint16_t src_port; /**< UDP source port in big endian. */ 179 uint16_t dst_port; /**< UDP destination port in big endian. */ 180 }; 181 182 /** 183 * A structure used to define the input for IPV4 TCP flow 184 */ 185 struct rte_eth_tcpv4_flow { 186 struct rte_eth_ipv4_flow ip; /**< IPv4 fields to match. */ 187 uint16_t src_port; /**< TCP source port in big endian. */ 188 uint16_t dst_port; /**< TCP destination port in big endian. */ 189 }; 190 191 /** 192 * A structure used to define the input for IPV4 SCTP flow 193 */ 194 struct rte_eth_sctpv4_flow { 195 struct rte_eth_ipv4_flow ip; /**< IPv4 fields to match. */ 196 uint16_t src_port; /**< SCTP source port in big endian. */ 197 uint16_t dst_port; /**< SCTP destination port in big endian. */ 198 uint32_t verify_tag; /**< Verify tag in big endian */ 199 }; 200 201 /** 202 * A structure used to define the input for IPV6 flow 203 */ 204 struct rte_eth_ipv6_flow { 205 uint32_t src_ip[4]; /**< IPv6 source address in big endian. */ 206 uint32_t dst_ip[4]; /**< IPv6 destination address in big endian. */ 207 uint8_t tc; /**< Traffic class to match. */ 208 uint8_t proto; /**< Protocol, next header to match. */ 209 uint8_t hop_limits; /**< Hop limits to match. */ 210 }; 211 212 /** 213 * A structure used to define the input for IPV6 UDP flow 214 */ 215 struct rte_eth_udpv6_flow { 216 struct rte_eth_ipv6_flow ip; /**< IPv6 fields to match. */ 217 uint16_t src_port; /**< UDP source port in big endian. */ 218 uint16_t dst_port; /**< UDP destination port in big endian. */ 219 }; 220 221 /** 222 * A structure used to define the input for IPV6 TCP flow 223 */ 224 struct rte_eth_tcpv6_flow { 225 struct rte_eth_ipv6_flow ip; /**< IPv6 fields to match. */ 226 uint16_t src_port; /**< TCP source port to in big endian. */ 227 uint16_t dst_port; /**< TCP destination port in big endian. */ 228 }; 229 230 /** 231 * A structure used to define the input for IPV6 SCTP flow 232 */ 233 struct rte_eth_sctpv6_flow { 234 struct rte_eth_ipv6_flow ip; /**< IPv6 fields to match. */ 235 uint16_t src_port; /**< SCTP source port in big endian. */ 236 uint16_t dst_port; /**< SCTP destination port in big endian. */ 237 uint32_t verify_tag; /**< Verify tag in big endian. */ 238 }; 239 240 /** 241 * A structure used to define the input for MAC VLAN flow 242 */ 243 struct rte_eth_mac_vlan_flow { 244 struct rte_ether_addr mac_addr; /**< Mac address to match. */ 245 }; 246 247 /** 248 * Tunnel type for flow director. 249 */ 250 enum rte_eth_fdir_tunnel_type { 251 RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0, 252 RTE_FDIR_TUNNEL_TYPE_NVGRE, 253 RTE_FDIR_TUNNEL_TYPE_VXLAN, 254 }; 255 256 /** 257 * A structure used to define the input for tunnel flow, now it's VxLAN or 258 * NVGRE 259 */ 260 struct rte_eth_tunnel_flow { 261 enum rte_eth_fdir_tunnel_type tunnel_type; /**< Tunnel type to match. */ 262 /** Tunnel ID to match. TNI, VNI... in big endian. */ 263 uint32_t tunnel_id; 264 struct rte_ether_addr mac_addr; /**< Mac address to match. */ 265 }; 266 267 /** 268 * An union contains the inputs for all types of flow 269 * Items in flows need to be in big endian 270 */ 271 union rte_eth_fdir_flow { 272 struct rte_eth_l2_flow l2_flow; 273 struct rte_eth_udpv4_flow udp4_flow; 274 struct rte_eth_tcpv4_flow tcp4_flow; 275 struct rte_eth_sctpv4_flow sctp4_flow; 276 struct rte_eth_ipv4_flow ip4_flow; 277 struct rte_eth_udpv6_flow udp6_flow; 278 struct rte_eth_tcpv6_flow tcp6_flow; 279 struct rte_eth_sctpv6_flow sctp6_flow; 280 struct rte_eth_ipv6_flow ipv6_flow; 281 struct rte_eth_mac_vlan_flow mac_vlan_flow; 282 struct rte_eth_tunnel_flow tunnel_flow; 283 }; 284 285 /** 286 * A structure used to contain extend input of flow 287 */ 288 struct rte_eth_fdir_flow_ext { 289 uint16_t vlan_tci; 290 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]; 291 /**< It is filled by the flexible payload to match. */ 292 uint8_t is_vf; /**< 1 for VF, 0 for port dev */ 293 uint16_t dst_id; /**< VF ID, available when is_vf is 1*/ 294 }; 295 296 /** 297 * A structure used to define the input for a flow director filter entry 298 */ 299 struct rte_eth_fdir_input { 300 uint16_t flow_type; 301 union rte_eth_fdir_flow flow; 302 /**< Flow fields to match, dependent on flow_type */ 303 struct rte_eth_fdir_flow_ext flow_ext; 304 /**< Additional fields to match */ 305 }; 306 307 /** 308 * Behavior will be taken if FDIR match 309 */ 310 enum rte_eth_fdir_behavior { 311 RTE_ETH_FDIR_ACCEPT = 0, 312 RTE_ETH_FDIR_REJECT, 313 RTE_ETH_FDIR_PASSTHRU, 314 }; 315 316 /** 317 * Flow director report status 318 * It defines what will be reported if FDIR entry is matched. 319 */ 320 enum rte_eth_fdir_status { 321 RTE_ETH_FDIR_NO_REPORT_STATUS = 0, /**< Report nothing. */ 322 RTE_ETH_FDIR_REPORT_ID, /**< Only report FD ID. */ 323 RTE_ETH_FDIR_REPORT_ID_FLEX_4, /**< Report FD ID and 4 flex bytes. */ 324 RTE_ETH_FDIR_REPORT_FLEX_8, /**< Report 8 flex bytes. */ 325 }; 326 327 /** 328 * A structure used to define an action when match FDIR packet filter. 329 */ 330 struct rte_eth_fdir_action { 331 uint16_t rx_queue; /**< Queue assigned to if FDIR match. */ 332 enum rte_eth_fdir_behavior behavior; /**< Behavior will be taken */ 333 enum rte_eth_fdir_status report_status; /**< Status report option */ 334 uint8_t flex_off; 335 /**< If report_status is RTE_ETH_FDIR_REPORT_ID_FLEX_4 or 336 RTE_ETH_FDIR_REPORT_FLEX_8, flex_off specifies where the reported 337 flex bytes start from in flexible payload. */ 338 }; 339 340 /** 341 * A structure used to define the flow director filter entry by filter_ctrl API. 342 */ 343 struct rte_eth_fdir_filter { 344 uint32_t soft_id; 345 /**< ID, an unique value is required when deal with FDIR entry */ 346 struct rte_eth_fdir_input input; /**< Input set */ 347 struct rte_eth_fdir_action action; /**< Action taken when match */ 348 }; 349 350 /** 351 * A structure used to configure FDIR masks that are used by the device 352 * to match the various fields of RX packet headers. 353 */ 354 struct rte_eth_fdir_masks { 355 uint16_t vlan_tci_mask; /**< Bit mask for vlan_tci in big endian */ 356 /** Bit mask for ipv4 flow in big endian. */ 357 struct rte_eth_ipv4_flow ipv4_mask; 358 /** Bit mask for ipv6 flow in big endian. */ 359 struct rte_eth_ipv6_flow ipv6_mask; 360 /** Bit mask for L4 source port in big endian. */ 361 uint16_t src_port_mask; 362 /** Bit mask for L4 destination port in big endian. */ 363 uint16_t dst_port_mask; 364 /** 6 bit mask for proper 6 bytes of Mac address, bit 0 matches the 365 first byte on the wire */ 366 uint8_t mac_addr_byte_mask; 367 /** Bit mask for tunnel ID in big endian. */ 368 uint32_t tunnel_id_mask; 369 uint8_t tunnel_type_mask; /**< 1 - Match tunnel type, 370 0 - Ignore tunnel type. */ 371 }; 372 373 /** 374 * Payload type 375 */ 376 enum rte_eth_payload_type { 377 RTE_ETH_PAYLOAD_UNKNOWN = 0, 378 RTE_ETH_RAW_PAYLOAD, 379 RTE_ETH_L2_PAYLOAD, 380 RTE_ETH_L3_PAYLOAD, 381 RTE_ETH_L4_PAYLOAD, 382 RTE_ETH_PAYLOAD_MAX = 8, 383 }; 384 385 /** 386 * A structure used to select bytes extracted from the protocol layers to 387 * flexible payload for filter 388 */ 389 struct rte_eth_flex_payload_cfg { 390 enum rte_eth_payload_type type; /**< Payload type */ 391 uint16_t src_offset[RTE_ETH_FDIR_MAX_FLEXLEN]; 392 /**< Offset in bytes from the beginning of packet's payload 393 src_offset[i] indicates the flexbyte i's offset in original 394 packet payload. This value should be less than 395 flex_payload_limit in struct rte_eth_fdir_info.*/ 396 }; 397 398 /** 399 * A structure used to define FDIR masks for flexible payload 400 * for each flow type 401 */ 402 struct rte_eth_fdir_flex_mask { 403 uint16_t flow_type; 404 uint8_t mask[RTE_ETH_FDIR_MAX_FLEXLEN]; 405 /**< Mask for the whole flexible payload */ 406 }; 407 408 /** 409 * A structure used to define all flexible payload related setting 410 * include flex payload and flex mask 411 */ 412 struct rte_eth_fdir_flex_conf { 413 uint16_t nb_payloads; /**< The number of following payload cfg */ 414 uint16_t nb_flexmasks; /**< The number of following mask */ 415 struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX]; 416 /**< Flex payload configuration for each payload type */ 417 struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX]; 418 /**< Flex mask configuration for each flow type */ 419 }; 420 421 /** 422 * Flow Director setting modes: none, signature or perfect. 423 */ 424 enum rte_fdir_mode { 425 RTE_FDIR_MODE_NONE = 0, /**< Disable FDIR support. */ 426 RTE_FDIR_MODE_SIGNATURE, /**< Enable FDIR signature filter mode. */ 427 RTE_FDIR_MODE_PERFECT, /**< Enable FDIR perfect filter mode. */ 428 RTE_FDIR_MODE_PERFECT_MAC_VLAN, /**< Enable FDIR filter mode - MAC VLAN. */ 429 RTE_FDIR_MODE_PERFECT_TUNNEL, /**< Enable FDIR filter mode - tunnel. */ 430 }; 431 432 #define UINT64_BIT (CHAR_BIT * sizeof(uint64_t)) 433 #define RTE_FLOW_MASK_ARRAY_SIZE \ 434 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT) 435 436 /** 437 * A structure used to get the information of flow director filter. 438 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_INFO operation. 439 * It includes the mode, flexible payload configuration information, 440 * capabilities and supported flow types, flexible payload characters. 441 * It can be gotten to help taking specific configurations per device. 442 */ 443 struct rte_eth_fdir_info { 444 enum rte_fdir_mode mode; /**< Flow director mode */ 445 struct rte_eth_fdir_masks mask; 446 /** Flex payload configuration information */ 447 struct rte_eth_fdir_flex_conf flex_conf; 448 uint32_t guarant_spc; /**< Guaranteed spaces.*/ 449 uint32_t best_spc; /**< Best effort spaces.*/ 450 /** Bit mask for every supported flow type. */ 451 uint64_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE]; 452 uint32_t max_flexpayload; /**< Total flex payload in bytes. */ 453 /** Flexible payload unit in bytes. Size and alignments of all flex 454 payload segments should be multiplies of this value. */ 455 uint32_t flex_payload_unit; 456 /** Max number of flexible payload continuous segments. 457 Each segment should be a multiple of flex_payload_unit.*/ 458 uint32_t max_flex_payload_segment_num; 459 /** Maximum src_offset in bytes allowed. It indicates that 460 src_offset[i] in struct rte_eth_flex_payload_cfg should be less 461 than this value. */ 462 uint16_t flex_payload_limit; 463 /** Flex bitmask unit in bytes. Size of flex bitmasks should be a 464 multiply of this value. */ 465 uint32_t flex_bitmask_unit; 466 /** Max supported size of flex bitmasks in flex_bitmask_unit */ 467 uint32_t max_flex_bitmask_num; 468 }; 469 470 /** 471 * A structure used to define the statistics of flow director. 472 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_STATS operation. 473 */ 474 struct rte_eth_fdir_stats { 475 uint32_t collision; /**< Number of filters with collision. */ 476 uint32_t free; /**< Number of free filters. */ 477 uint32_t maxhash; 478 /**< The lookup hash value of the added filter that updated the value 479 of the MAXLEN field */ 480 uint32_t maxlen; /**< Longest linked list of filters. */ 481 uint64_t add; /**< Number of added filters. */ 482 uint64_t remove; /**< Number of removed filters. */ 483 uint64_t f_add; /**< Number of failed added filters. */ 484 uint64_t f_remove; /**< Number of failed removed filters. */ 485 uint32_t guarant_cnt; /**< Number of filters in guaranteed spaces. */ 486 uint32_t best_cnt; /**< Number of filters in best effort spaces. */ 487 }; 488 489 #ifdef __cplusplus 490 } 491 #endif 492 493 #endif /* _RTE_ETH_CTRL_H_ */ 494