Searched refs:m_width (Results 1 – 2 of 2) sorted by relevance
| /f-stack/freebsd/arm/nvidia/tegra124/ |
| H A D | tegra124_clk_pll.c | 99 uint32_t m_width; member
497 *m = get_masked(val, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in get_divisors()
509 val = set_masked(val, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in set_divisors()
700 if (m >= (1 << mnp_bits->m_width)) in pll_set_std()
724 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in pll_set_std()
818 for (m = 1; m < (1 << mnp_bits->m_width); m++) { in plld2_set_freq()
889 if (m >= (1 << mnp_bits->m_width)) in pllx_set_freq()
911 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in pllx_set_freq()
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| /f-stack/freebsd/arm64/nvidia/tegra210/ |
| H A D | tegra210_clk_pll.c | 124 uint32_t m_width; member
690 *m = get_masked(val, mnp_bits->m_shift, mnp_bits->m_width); in get_divisors()
702 val = set_masked(val, m, mnp_bits->m_shift, mnp_bits->m_width); in set_divisors()
898 if (m >= (1 << mnp_bits->m_width)) in pll_set_std()
922 reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width); in pll_set_std()
1041 for (m = 1; m < (1 << mnp_bits->m_width); m++) { in plld2_set_freq()
1127 if (m >= (1 << mnp_bits->m_width)) in pllx_set_freq()
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