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/f-stack/freebsd/contrib/device-tree/src/arm64/renesas/
H A Dr8a774c0-ek874-mipi-2.1.dts37 clock-lanes = <0>;
38 data-lanes = <1 2>;
51 clock-lanes = <0>;
52 data-lanes = <1 2>;
61 clock-lanes = <0>;
62 data-lanes = <1 2>;
/f-stack/freebsd/contrib/device-tree/Bindings/phy/
H A Dphy-cadence-sierra.txt22 the clock to the lanes. "phy_clk" is deprecated.
29 Each group of PHY lanes with a single master lane should be represented as
42 - cdns,num-lanes: Number of lanes in this group. From 1 to 4. The
43 group is made up of consecutive lanes.
45 configuration of lanes.
60 cdns,num-lanes = <2>;
67 cdns,num-lanes = <1>;
H A Dnvidia,tegra124-xusb-padctl.txt283 lanes {
304 lanes {
315 lanes {
331 lanes {
362 lanes {
415 lanes {
436 lanes {
457 lanes {
513 lanes {
541 lanes {
[all …]
H A Dphy-cadence-torrent.yaml61 Each group of PHY lanes with a single master lane should be represented as a sub-node.
71 Contains list of resets, one per lane, to get all the link lanes out of reset.
78 Specifies the type of PHY for which the group of PHY lanes is used.
83 cdns,num-lanes:
85 Number of DisplayPort lanes.
141 cdns,num-lanes = <4>;
/f-stack/freebsd/contrib/device-tree/Bindings/media/xilinx/
H A Dxlnx,csi2rxss.yaml88 xlnx,en-active-lanes:
91 Present if the number of active lanes can be re-configured at
92 runtime in the Protocol Configuration Register. Otherwise all lanes,
118 data-lanes:
124 1 2 - For 2 lanes enabled in IP.
125 1 2 3 - For 3 lanes enabled in IP.
126 1 2 3 4 - For 4 lanes enabled in IP.
136 - data-lanes
207 xlnx,en-active-lanes;
222 data-lanes = <1 2 3 4>;
/f-stack/freebsd/contrib/device-tree/Bindings/media/
H A Dti,cal.yaml97 clock-lanes:
100 data-lanes:
124 clock-lanes:
127 data-lanes:
173 clock-lanes = <0>;
174 data-lanes = <1 2>;
195 clock-lanes = <0>;
196 data-lanes = <1 2>;
H A Drenesas,csi2.yaml68 clock-lanes:
71 data-lanes:
77 - clock-lanes
78 - data-lanes
152 clock-lanes = <0>;
153 data-lanes = <1>;
H A Dsamsung-mipi-csis.txt13 - bus-width : maximum number of data lanes supported (SoC specific);
42 - data-lanes : (required) an array specifying active physical MIPI-CSI2
43 data input lanes and their mapping to logical lanes; the
77 data-lanes = <1>, <2>;
/f-stack/freebsd/contrib/device-tree/src/arm64/marvell/
H A Dcn9132-db.dts67 * lanes not being connected. Prevent the port for being
108 /* Generic PHY, providing serdes lanes */
156 num-lanes = <2>;
158 /* Generic PHY, providing serdes lanes */
166 num-lanes = <1>;
168 /* Generic PHY, providing serdes lanes */
177 /* Generic PHY, providing serdes lanes */
219 /* Generic PHY, providing serdes lanes */
H A Dcn9131-db.dts49 * lanes not being connected. Prevent the port for being
90 /* Generic PHY, providing serdes lanes */
115 num-lanes = <2>;
119 /* Generic PHY, providing serdes lanes */
129 /* Generic PHY, providing serdes lanes */
199 /* Generic PHY, providing serdes lanes */
/f-stack/freebsd/contrib/device-tree/Bindings/pci/
H A Dnvidia,tegra20-pcie.txt148 - nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
157 number of lanes in the nvidia,num-lanes property. Entries are of the form
210 nvidia,num-lanes = <2>;
224 nvidia,num-lanes = <2>;
316 nvidia,num-lanes = <2>;
329 nvidia,num-lanes = <2>;
342 nvidia,num-lanes = <2>;
420 nvidia,num-lanes = <2>;
433 nvidia,num-lanes = <1>;
516 nvidia,num-lanes = <4>;
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/display/panel/
H A Draydium,rm67191.yaml25 dsi-lanes:
26 description: Number of DSI lanes to be used must be <3> or <4>
45 - dsi-lanes
62 dsi-lanes = <4>;
/f-stack/freebsd/contrib/device-tree/Bindings/media/i2c/
H A Dadv748x.txt52 endpoint. Each of those endpoints shall contain the data-lanes property as
56 - data-lanes: an array of physical data lane indexes
58 sources are described. For TXA 1, 2 or 4 data lanes can be described
101 clock-lanes = <0>;
102 data-lanes = <1 2 3 4>;
111 clock-lanes = <0>;
112 data-lanes = <1>;
H A Dov2680.txt22 - clock-lanes: should be set to <0> (clock lane on hardware lane 0).
23 - data-lanes: should be set to <1> (one CSI-2 lane supported).
41 clock-lanes = <0>;
42 data-lanes = <1>;
H A Dtc358743.txt16 - data-lanes: should be <1 2 3 4> for four-lane operation,
18 - clock-lanes: should be <0>
42 data-lanes = <1 2 3 4>;
43 clock-lanes = <0>;
H A Dov5640.txt29 - clock-lanes: should be set to <0> (clock lane on hardware lane 0)
30 - data-lanes: should be set to <1> or <1 2> (one or two CSI-2 lanes supported)
64 clock-lanes = <0>;
65 data-lanes = <1 2>;
/f-stack/freebsd/contrib/device-tree/src/arm64/nvidia/
H A Dtegra210-p2371-2180.dts22 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
23 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
24 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
25 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
31 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
H A Dtegra186-p2771-0000.dts129 lanes {
150 lanes {
206 phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>,
207 <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>,
208 <&{/padctl@3520000/pads/usb3/lanes/usb3-0}>;
242 nvidia,num-lanes = <4>;
247 nvidia,num-lanes = <0>;
252 nvidia,num-lanes = <1>;
H A Dtegra194-p2972-0000.dts45 lanes {
57 lanes {
96 phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
97 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
98 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
99 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-3}>;
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Domap3-n9.dts31 clock-lanes = <0>;
32 data-lanes = <1 2>;
54 clock-lanes = <2>;
55 data-lanes = <1 3>;
H A Dimx6dl-sabresd.dts16 clock-lanes = <0>;
17 data-lanes = <1 2>;
H A Dimx6q-sabresd.dts21 clock-lanes = <0>;
22 data-lanes = <1 2>;
/f-stack/freebsd/contrib/libsodium/src/libsodium/crypto_pwhash/argon2/
H A Dargon2.c47 if (memory_blocks < 2 * ARGON2_SYNC_POINTS * context->lanes) { in argon2_ctx()
48 memory_blocks = 2 * ARGON2_SYNC_POINTS * context->lanes; in argon2_ctx()
51 segment_length = memory_blocks / (context->lanes * ARGON2_SYNC_POINTS); in argon2_ctx()
53 memory_blocks = segment_length * (context->lanes * ARGON2_SYNC_POINTS); in argon2_ctx()
61 instance.lanes = context->lanes; in argon2_ctx()
125 context.lanes = parallelism; in argon2_hash()
H A Dargon2-core.c197 for (l = 1; l < instance->lanes; ++l) { in finalize()
227 if (instance == NULL || instance->lanes == 0) { in fill_memory_blocks()
234 for (l = 0; l < instance->lanes; ++l) { in fill_memory_blocks()
332 if (context->m_cost < 8 * context->lanes) { in validate_inputs()
346 if (ARGON2_MIN_LANES > context->lanes) { in validate_inputs()
350 if (ARGON2_MAX_LANES < context->lanes) { in validate_inputs()
374 for (l = 0; l < instance->lanes; ++l) { in fill_first_blocks()
404 STORE32_LE(value, context->lanes); in initial_hash()
/f-stack/freebsd/contrib/device-tree/Bindings/pinctrl/
H A Dnvidia,tegra124-xusb-padctl.txt10 The Tegra XUSB pad controller manages a set of lanes, each of which can be
40 Each subnode describes groups of lanes along with parameters and pads that
54 - nvidia,lanes: An array of strings. Each string is the name of a lane.
62 Note that not all of these properties are valid for all lanes. Lanes can be
117 nvidia,lanes = "pcie-0", "pcie-1";
123 nvidia,lanes = "pcie-2", "pcie-3",
130 nvidia,lanes = "sata-0";

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