Home
last modified time | relevance | path

Searched refs:lane (Results 1 – 25 of 116) sorted by relevance

12345

/f-stack/freebsd/contrib/alpine-hal/
H A Dal_hal_serdes_25g.c405 for (lane = AL_SRDS_LANE_0; lane <= AL_SRDS_LANE_1; lane++) { in al_serdes_25g_bist_pattern_select()
1514 lane, in al_serdes_25g_tx_diag_info_get()
1533 lane, in al_serdes_25g_tx_diag_info_get()
1655 lane, in al_serdes_25g_rx_diag_info_get()
1702 lane, in al_serdes_25g_rx_diag_info_get()
1715 lane, in al_serdes_25g_rx_diag_info_get()
1728 lane, in al_serdes_25g_rx_diag_info_get()
1741 lane, in al_serdes_25g_rx_diag_info_get()
1754 lane, in al_serdes_25g_rx_diag_info_get()
1766 lane, in al_serdes_25g_rx_diag_info_get()
[all …]
H A Dal_hal_serdes_hssp.c115 enum al_serdes_lane lane);
128 enum al_serdes_lane lane);
508 enum al_serdes_lane lane) in al_serdes_lane_rx_rate_change_sw_flow_en() argument
522 enum al_serdes_lane lane) in al_serdes_lane_rx_rate_change_sw_flow_dis() argument
531 enum al_serdes_lane lane, in al_serdes_lane_pcie_rate_override_enable_set() argument
547 enum al_serdes_lane lane) in al_serdes_lane_pcie_rate_override_is_enabled() argument
1048 int lane; in al_serdes_group_rx_rate_change_sw_flow_dis() local
1050 for (lane = AL_SRDS_LANE_0; lane < AL_SRDS_NUM_LANES; lane++) in al_serdes_group_rx_rate_change_sw_flow_dis()
1137 int lane; in al_serdes_group_rx_rate_change_sw_flow_en_cond() local
1139 for (lane = AL_SRDS_LANE_0; lane < AL_SRDS_NUM_LANES; lane++) in al_serdes_group_rx_rate_change_sw_flow_en_cond()
[all …]
/f-stack/freebsd/arm64/rockchip/
H A Drk_typec_phy.c90 #define TX_PSC_A0(lane) ((0x4100 | ((lane) << 9)) << 2) argument
91 #define TX_PSC_A1(lane) ((0x4101 | ((lane) << 9)) << 2) argument
92 #define TX_PSC_A2(lane) ((0x4102 | ((lane) << 9)) << 2) argument
93 #define TX_PSC_A3(lane) ((0x4103 | ((lane) << 9)) << 2) argument
94 #define TX_RCVDET_EN_TMR(lane) ((0x4122 | ((lane) << 9)) << 2) argument
97 #define RX_PSC_A0(lane) ((0x8000 | ((lane) << 9)) << 2) argument
98 #define RX_PSC_A1(lane) ((0x8001 | ((lane) << 9)) << 2) argument
99 #define RX_PSC_A2(lane) ((0x8002 | ((lane) << 9)) << 2) argument
100 #define RX_PSC_A3(lane) ((0x8003 | ((lane) << 9)) << 2) argument
101 #define RX_PSC_CAL(lane) ((0x8006 | ((lane) << 9)) << 2) argument
[all …]
/f-stack/freebsd/arm/nvidia/tegra124/
H A Dtegra124_xusbpadctl.c557 lane->name); in usb2_powerup()
625 lane->name); in usb2_powerdown()
712 pad = lane->pad; in xusbpadctl_phy_enable()
765 if (ports_tbl[i].lane == lane) in search_lane_port()
803 lane = NULL; in search_usb3_pad_lane()
818 lane = tmp; in search_usb3_pad_lane()
820 return (lane); in search_usb3_pad_lane()
853 reg &= ~(lane->mask << lane->shift); in config_lane()
854 reg |= (lane->mux_idx & lane->mask) << lane->shift; in config_lane()
892 lane->mux_idx = search_mux(sc, lane, function); in process_lane()
[all …]
/f-stack/freebsd/contrib/alpine-hal/eth/
H A Dal_hal_eth_kr.h160 enum al_eth_an_lt_lane lane,
173 enum al_eth_an_lt_lane lane,
186 enum al_eth_an_lt_lane lane,
199 enum al_eth_an_lt_lane lane,
211 enum al_eth_an_lt_lane lane);
222 enum al_eth_an_lt_lane lane);
243 enum al_eth_an_lt_lane lane);
269 enum al_eth_an_lt_lane lane,
332 enum al_eth_an_lt_lane lane);
344 enum al_eth_an_lt_lane lane,
[all …]
H A Dal_hal_eth_kr.c212 enum al_eth_an_lt_lane lane) in al_eth_an_lt_reg_read() argument
233 switch (lane) { in al_eth_an_lt_reg_read()
291 enum al_eth_an_lt_lane lane, in al_eth_an_lt_reg_write() argument
310 switch (lane) { in al_eth_an_lt_reg_write()
499 enum al_eth_an_lt_lane lane, in al_eth_lp_coeff_up_get() argument
529 enum al_eth_an_lt_lane lane, in al_eth_lp_status_report_get() argument
556 enum al_eth_an_lt_lane lane, in al_eth_ld_coeff_up_set() argument
587 enum al_eth_an_lt_lane lane, in al_eth_ld_status_report_set() argument
626 enum al_eth_an_lt_lane lane) in al_eth_kr_startup_proto_prog_get() argument
914 lane, control); in al_eth_kr_an_start()
[all …]
/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c1148 pad = lane->pad; in hsic_enable()
1270 pad = lane->pad; in usb2_enable()
1351 pad = lane->pad; in usb2_disable()
1449 pad = lane->pad; in xusbpadctl_phy_enable()
1502 if (ports_tbl[i].lane == lane) in search_lane_port()
1540 lane = NULL; in search_usb3_pad_lane()
1555 lane = tmp; in search_usb3_pad_lane()
1557 return (lane); in search_usb3_pad_lane()
1590 reg &= ~(lane->mask << lane->shift); in config_lane()
1591 reg |= (lane->mux_idx & lane->mask) << lane->shift; in config_lane()
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/media/i2c/
H A Dst,st-mipid02.txt6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
37 - data-lanes: shall be <1> for Port 1. for Port 0 dual-lane operation shall be
38 <1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>.
40 - lane-polarities: any lane can be inverted or not.
H A Dimx219.yaml56 The sensor supports either two-lane, or four-lane operation.
57 If this property is omitted four-lane operation is assumed.
58 For two-lane operation the property must be set to <1 2>.
H A Dov2680.txt22 - clock-lanes: should be set to <0> (clock lane on hardware lane 0).
23 - data-lanes: should be set to <1> (one CSI-2 lane supported).
H A Dtc358743.txt16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
23 is half of the bps per lane due to DDR transmission.
/f-stack/freebsd/contrib/device-tree/Bindings/phy/
H A Dphy-cadence-sierra.txt29 Each group of PHY lanes with a single master lane should be represented as
30 a sub-node. Note that the actual configuration of each lane is determined by
35 - reg: The master lane number. This is the lowest numbered lane
36 in the lane group.
38 master lane of the sub-node.
H A Dphy-cadence-torrent.yaml61 Each group of PHY lanes with a single master lane should be represented as a sub-node.
65 The master lane number. This is the lowest numbered lane in the lane group.
71 Contains list of resets, one per lane, to get all the link lanes out of reset.
H A Dphy-armada38x-comphy.txt22 A sub-node is required for each comphy lane provided by the comphy.
26 - reg: comphy lane number.
28 input port to use for a given comphy lane.
/f-stack/freebsd/contrib/device-tree/Bindings/pci/
H A Dmvebu-pci.txt77 - marvell,pcie-lane: the physical PCIe lane number, for ports having
143 marvell,pcie-lane = <0>;
163 marvell,pcie-lane = <1>;
179 marvell,pcie-lane = <2>;
195 marvell,pcie-lane = <3>;
211 marvell,pcie-lane = <0>;
227 marvell,pcie-lane = <1>;
243 marvell,pcie-lane = <2>;
259 marvell,pcie-lane = <3>;
275 marvell,pcie-lane = <0>;
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/media/
H A Dqcom,camss.txt126 Definition: The physical clock lane index. On 8916
128 clock lane is lane 1. On 8996 the value must
131 D-PHY physical clock lane is labeled as 7.
137 lane number, while the value of an entry
138 indicates physical lane index. Lane swapping
139 is supported. Physical lane indexes for
H A Dvideo-interfaces.txt489 - data-lanes: an array of physical data lane indexes. Position of an entry
490 determines the logical lane number, while the value of an entry indicates
491 physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have
492 "data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0.
493 If the hardware does not support lane reordering, monotonically
495 whether or not there is also a clock lane. This property is valid for
498 determines the logical lane number, while the value of an entry indicates
500 which places the clock lane on hardware lane 0. This property is valid for
507 lane value. An array of 64-bit unsigned integers.
509 lane and followed by the data lanes in the same order as in data-lanes.
[all …]
/f-stack/dpdk/lib/librte_eal/arm/include/
H A Drte_vect.h111 vgetq_lane_p64(poly64x2_t x, const int lane) in vgetq_lane_p64() argument
113 RTE_ASSERT(lane >= 0 && lane <= 1); in vgetq_lane_p64()
117 return p[lane]; in vgetq_lane_p64()
/f-stack/freebsd/contrib/octeon-sdk/
H A Dcvmx-qlm.h112 extern uint64_t cvmx_qlm_jtag_get(int qlm, int lane, const char *name);
122 extern void cvmx_qlm_jtag_set(int qlm, int lane, const char *name, uint64_t value);
H A Dcvmx-helper-errata.c304 int lane; in __cvmx_helper_errata_qlm_disable_2nd_order_cdr() local
313 for (lane=0; lane<4; lane++) in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
H A Dcvmx-qlm.c327 uint64_t cvmx_qlm_jtag_get(int qlm, int lane, const char *name) in cvmx_qlm_jtag_get() argument
339 …cvmx_helper_qlm_jtag_shift_zeros(qlm, qlm_jtag_length * (num_lanes-1-lane)); /* Shift to the st… in cvmx_qlm_jtag_get()
353 void cvmx_qlm_jtag_set(int qlm, int lane, const char *name, uint64_t value) in cvmx_qlm_jtag_set() argument
376 if ((l != lane) && (lane != -1)) in cvmx_qlm_jtag_set()
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Darmada-xp-mv78460.dtsi129 marvell,pcie-lane = <0>;
147 marvell,pcie-lane = <1>;
165 marvell,pcie-lane = <2>;
183 marvell,pcie-lane = <3>;
201 marvell,pcie-lane = <0>;
219 marvell,pcie-lane = <1>;
237 marvell,pcie-lane = <2>;
255 marvell,pcie-lane = <3>;
273 marvell,pcie-lane = <0>;
291 marvell,pcie-lane = <0>;
H A Darmada-xp-mv78260.dtsi108 marvell,pcie-lane = <0>;
126 marvell,pcie-lane = <1>;
144 marvell,pcie-lane = <2>;
162 marvell,pcie-lane = <3>;
180 marvell,pcie-lane = <0>;
198 marvell,pcie-lane = <1>;
216 marvell,pcie-lane = <2>;
234 marvell,pcie-lane = <3>;
252 marvell,pcie-lane = <0>;
H A Darmada-xp-mv78230.dtsi93 marvell,pcie-lane = <0>;
111 marvell,pcie-lane = <1>;
129 marvell,pcie-lane = <2>;
147 marvell,pcie-lane = <3>;
165 marvell,pcie-lane = <0>;
/f-stack/freebsd/contrib/device-tree/Bindings/display/bridge/
H A Dps8622.txt10 - lane-count: number of DP lanes to use
23 lane-count = <1>;

12345