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39
40
41 /**
42 * @file
43 *
44 * This header file defines the work queue entry (wqe) data structure.
45 * Since this is a commonly used structure that depends on structures
46 * from several hardware blocks, those definitions have been placed
47 * in this file to create a single point of definition of the wqe
48 * format.
49 * Data structures are still named according to the block that they
50 * relate to.
51 *
52 * This file must not depend on any other header files, except for cvmx.h!!!
53 *
54 *
55 * <hr>$Revision: 70030 $<hr>
56 *
57 *
58 */
59
60 #ifndef __CVMX_WQE_H__
61 #define __CVMX_WQE_H__
62
63 #ifdef __cplusplus
64 extern "C" {
65 #endif
66
67 #define OCT_TAG_TYPE_STRING(x) (((x) == CVMX_POW_TAG_TYPE_ORDERED) ? "ORDERED" : \
68 (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ? "ATOMIC" : \
69 (((x) == CVMX_POW_TAG_TYPE_NULL) ? "NULL" : \
70 "NULL_NULL")))
71
72
73 /**
74 * HW decode / err_code in work queue entry
75 */
76 typedef union
77 {
78 uint64_t u64;
79
80 /** Use this struct if the hardware determines that the packet is IP */
81 struct
82 {
83 uint64_t bufs : 8; /**< HW sets this to the number of buffers used by this packet */
84 uint64_t ip_offset : 8; /**< HW sets to the number of L2 bytes prior to the IP */
85 uint64_t vlan_valid : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
86 uint64_t vlan_stacked : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
87 uint64_t unassigned : 1;
88 uint64_t vlan_cfi : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
89 uint64_t vlan_id :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
90 uint64_t varies:12; /**< 38xx and 68xx have different definitions. */
91 uint64_t dec_ipcomp : 1; /**< the packet needs to be decompressed */
92 uint64_t tcp_or_udp : 1; /**< the packet is either TCP or UDP */
93 uint64_t dec_ipsec : 1; /**< the packet needs to be decrypted (ESP or AH) */
94 uint64_t is_v6 : 1; /**< the packet is IPv6 */
95
96 /* (rcv_error, not_IP, IP_exc, is_frag, L4_error, software, etc.) */
97
98 uint64_t software : 1; /**< reserved for software use, hardware will clear on packet creation */
99 /* exceptional conditions below */
100 uint64_t L4_error : 1; /**< the receive interface hardware detected an L4 error (only applies if !is_frag)
101 (only applies if !rcv_error && !not_IP && !IP_exc && !is_frag)
102 failure indicated in err_code below, decode:
103 - 1 = Malformed L4
104 - 2 = L4 Checksum Error: the L4 checksum value is
105 - 3 = UDP Length Error: The UDP length field would make the UDP data longer than what
106 remains in the IP packet (as defined by the IP header length field).
107 - 4 = Bad L4 Port: either the source or destination TCP/UDP port is 0.
108 - 8 = TCP FIN Only: the packet is TCP and only the FIN flag set.
109 - 9 = TCP No Flags: the packet is TCP and no flags are set.
110 - 10 = TCP FIN RST: the packet is TCP and both FIN and RST are set.
111 - 11 = TCP SYN URG: the packet is TCP and both SYN and URG are set.
112 - 12 = TCP SYN RST: the packet is TCP and both SYN and RST are set.
113 - 13 = TCP SYN FIN: the packet is TCP and both SYN and FIN are set. */
114
115
116
117 uint64_t is_frag : 1; /**< set if the packet is a fragment */
118 uint64_t IP_exc : 1; /**< the receive interface hardware detected an IP error / exception
119 (only applies if !rcv_error && !not_IP) failure indicated in err_code below, decode:
120 - 1 = Not IP: the IP version field is neither 4 nor 6.
121 - 2 = IPv4 Header Checksum Error: the IPv4 header has a checksum violation.
122 - 3 = IP Malformed Header: the packet is not long enough to contain the IP header.
123 - 4 = IP Malformed: the packet is not long enough to contain the bytes indicated by the IP
124 header. Pad is allowed.
125 - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 Hop Count field are zero.
126 - 6 = IP Options */
127
128 uint64_t is_bcast : 1; /**< set if the hardware determined that the packet is a broadcast */
129 uint64_t is_mcast : 1; /**< set if the hardware determined that the packet is a multi-cast */
130 uint64_t not_IP : 1; /**< set if the packet may not be IP (must be zero in this case) */
131 uint64_t rcv_error : 1; /**< the receive interface hardware detected a receive error (must be zero in this case) */
132 /* lower err_code = first-level descriptor of the work */
133 /* zero for packet submitted by hardware that isn't on the slow path */
134
135 uint64_t err_code : 8; /**< type is cvmx_pip_err_t */
136 } s;
137 struct
138 {
139 uint64_t bufs : 8; /**< HW sets this to the number of buffers used by this packet */
140 uint64_t ip_offset : 8; /**< HW sets to the number of L2 bytes prior to the IP */
141 uint64_t vlan_valid : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
142 uint64_t vlan_stacked : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
143 uint64_t unassigned : 1;
144 uint64_t vlan_cfi : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
145 uint64_t vlan_id :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
146
147 uint64_t port:12; /**< MAC/PIP port number. */
148
149 uint64_t dec_ipcomp : 1; /**< the packet needs to be decompressed */
150 uint64_t tcp_or_udp : 1; /**< the packet is either TCP or UDP */
151 uint64_t dec_ipsec : 1; /**< the packet needs to be decrypted (ESP or AH) */
152 uint64_t is_v6 : 1; /**< the packet is IPv6 */
153
154 /* (rcv_error, not_IP, IP_exc, is_frag, L4_error, software, etc.) */
155
156 uint64_t software : 1; /**< reserved for software use, hardware will clear on packet creation */
157 /* exceptional conditions below */
158 uint64_t L4_error : 1; /**< the receive interface hardware detected an L4 error (only applies if !is_frag)
159 (only applies if !rcv_error && !not_IP && !IP_exc && !is_frag)
160 failure indicated in err_code below, decode:
161 - 1 = Malformed L4
162 - 2 = L4 Checksum Error: the L4 checksum value is
163 - 3 = UDP Length Error: The UDP length field would make the UDP data longer than what
164 remains in the IP packet (as defined by the IP header length field).
165 - 4 = Bad L4 Port: either the source or destination TCP/UDP port is 0.
166 - 8 = TCP FIN Only: the packet is TCP and only the FIN flag set.
167 - 9 = TCP No Flags: the packet is TCP and no flags are set.
168 - 10 = TCP FIN RST: the packet is TCP and both FIN and RST are set.
169 - 11 = TCP SYN URG: the packet is TCP and both SYN and URG are set.
170 - 12 = TCP SYN RST: the packet is TCP and both SYN and RST are set.
171 - 13 = TCP SYN FIN: the packet is TCP and both SYN and FIN are set. */
172
173
174
175 uint64_t is_frag : 1; /**< set if the packet is a fragment */
176 uint64_t IP_exc : 1; /**< the receive interface hardware detected an IP error / exception
177 (only applies if !rcv_error && !not_IP) failure indicated in err_code below, decode:
178 - 1 = Not IP: the IP version field is neither 4 nor 6.
179 - 2 = IPv4 Header Checksum Error: the IPv4 header has a checksum violation.
180 - 3 = IP Malformed Header: the packet is not long enough to contain the IP header.
181 - 4 = IP Malformed: the packet is not long enough to contain the bytes indicated by the IP
182 header. Pad is allowed.
183 - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 Hop Count field are zero.
184 - 6 = IP Options */
185
186 uint64_t is_bcast : 1; /**< set if the hardware determined that the packet is a broadcast */
187 uint64_t is_mcast : 1; /**< set if the hardware determined that the packet is a multi-cast */
188 uint64_t not_IP : 1; /**< set if the packet may not be IP (must be zero in this case) */
189 uint64_t rcv_error : 1; /**< the receive interface hardware detected a receive error (must be zero in this case) */
190 /* lower err_code = first-level descriptor of the work */
191 /* zero for packet submitted by hardware that isn't on the slow path */
192
193 uint64_t err_code : 8; /**< type is cvmx_pip_err_t */
194 } s_cn68xx;
195 struct
196 {
197 uint64_t bufs : 8; /**< HW sets this to the number of buffers used by this packet */
198 uint64_t ip_offset : 8; /**< HW sets to the number of L2 bytes prior to the IP */
199 uint64_t vlan_valid : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
200 uint64_t vlan_stacked : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
201 uint64_t unassigned : 1;
202 uint64_t vlan_cfi : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
203 uint64_t vlan_id :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
204 uint64_t pr : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
205 uint64_t unassigned2a :4;
206 uint64_t unassigned2 :4;
207
208 uint64_t dec_ipcomp : 1; /**< the packet needs to be decompressed */
209 uint64_t tcp_or_udp : 1; /**< the packet is either TCP or UDP */
210 uint64_t dec_ipsec : 1; /**< the packet needs to be decrypted (ESP or AH) */
211 uint64_t is_v6 : 1; /**< the packet is IPv6 */
212
213 /* (rcv_error, not_IP, IP_exc, is_frag, L4_error, software, etc.) */
214
215 uint64_t software : 1; /**< reserved for software use, hardware will clear on packet creation */
216 /* exceptional conditions below */
217 uint64_t L4_error : 1; /**< the receive interface hardware detected an L4 error (only applies if !is_frag)
218 (only applies if !rcv_error && !not_IP && !IP_exc && !is_frag)
219 failure indicated in err_code below, decode:
220 - 1 = Malformed L4
221 - 2 = L4 Checksum Error: the L4 checksum value is
222 - 3 = UDP Length Error: The UDP length field would make the UDP data longer than what
223 remains in the IP packet (as defined by the IP header length field).
224 - 4 = Bad L4 Port: either the source or destination TCP/UDP port is 0.
225 - 8 = TCP FIN Only: the packet is TCP and only the FIN flag set.
226 - 9 = TCP No Flags: the packet is TCP and no flags are set.
227 - 10 = TCP FIN RST: the packet is TCP and both FIN and RST are set.
228 - 11 = TCP SYN URG: the packet is TCP and both SYN and URG are set.
229 - 12 = TCP SYN RST: the packet is TCP and both SYN and RST are set.
230 - 13 = TCP SYN FIN: the packet is TCP and both SYN and FIN are set. */
231
232
233
234 uint64_t is_frag : 1; /**< set if the packet is a fragment */
235 uint64_t IP_exc : 1; /**< the receive interface hardware detected an IP error / exception
236 (only applies if !rcv_error && !not_IP) failure indicated in err_code below, decode:
237 - 1 = Not IP: the IP version field is neither 4 nor 6.
238 - 2 = IPv4 Header Checksum Error: the IPv4 header has a checksum violation.
239 - 3 = IP Malformed Header: the packet is not long enough to contain the IP header.
240 - 4 = IP Malformed: the packet is not long enough to contain the bytes indicated by the IP
241 header. Pad is allowed.
242 - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 Hop Count field are zero.
243 - 6 = IP Options */
244
245 uint64_t is_bcast : 1; /**< set if the hardware determined that the packet is a broadcast */
246 uint64_t is_mcast : 1; /**< set if the hardware determined that the packet is a multi-cast */
247 uint64_t not_IP : 1; /**< set if the packet may not be IP (must be zero in this case) */
248 uint64_t rcv_error : 1; /**< the receive interface hardware detected a receive error (must be zero in this case) */
249 /* lower err_code = first-level descriptor of the work */
250 /* zero for packet submitted by hardware that isn't on the slow path */
251
252 uint64_t err_code : 8; /**< type is cvmx_pip_err_t */
253 } s_cn38xx;
254
255 /**< use this to get at the 16 vlan bits */
256 struct
257 {
258 uint64_t unused1 :16;
259 uint64_t vlan :16;
260 uint64_t unused2 :32;
261 } svlan;
262
263 /**< use this struct if the hardware could not determine that the packet is ip */
264 struct
265 {
266 uint64_t bufs : 8; /**< HW sets this to the number of buffers used by this packet */
267 uint64_t unused : 8;
268 uint64_t vlan_valid : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
269 uint64_t vlan_stacked : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
270 uint64_t unassigned : 1;
271 uint64_t vlan_cfi : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
272 uint64_t vlan_id :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
273
274 uint64_t varies:12; /**< 38xx and 68xx have different definitions. */
275 uint64_t unassigned2:4;
276
277 uint64_t software : 1; /**< reserved for software use, hardware will clear on packet creation */
278 uint64_t unassigned3 : 1;
279 uint64_t is_rarp : 1; /**< set if the hardware determined that the packet is rarp */
280 uint64_t is_arp : 1; /**< set if the hardware determined that the packet is arp */
281 uint64_t is_bcast : 1; /**< set if the hardware determined that the packet is a broadcast */
282 uint64_t is_mcast : 1; /**< set if the hardware determined that the packet is a multi-cast */
283 uint64_t not_IP : 1; /**< set if the packet may not be IP (must be one in this case) */
284 uint64_t rcv_error : 1; /**< the receive interface hardware detected a receive error.
285 Failure indicated in err_code below, decode:
286 - 1 = partial error: a packet was partially received, but internal
287 buffering / bandwidth was not adequate to receive the entire packet.
288 - 2 = jabber error: the RGMII packet was too large and is truncated.
289 - 3 = overrun error: the RGMII packet is longer than allowed and had
290 an FCS error.
291 - 4 = oversize error: the RGMII packet is longer than allowed.
292 - 5 = alignment error: the RGMII packet is not an integer number of bytes
293 and had an FCS error (100M and 10M only).
294 - 6 = fragment error: the RGMII packet is shorter than allowed and had an
295 FCS error.
296 - 7 = GMX FCS error: the RGMII packet had an FCS error.
297 - 8 = undersize error: the RGMII packet is shorter than allowed.
298 - 9 = extend error: the RGMII packet had an extend error.
299 - 10 = length mismatch error: the RGMII packet had a length that did not
300 match the length field in the L2 HDR.
301 - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII packet had one or more
302 data reception errors (RXERR) or the SPI4 packet had one or more DIP4
303 errors.
304 - 12 = RGMII skip error/SPI4 Abort Error: the RGMII packet was not large
305 enough to cover the skipped bytes or the SPI4 packet was terminated
306 with an About EOPS.
307 - 13 = RGMII nibble error/SPI4 Port NXA Error: the RGMII packet had a
308 studder error (data not repeated - 10/100M only) or the SPI4 packet
309 was sent to an NXA.
310 - 16 = FCS error: a SPI4.2 packet had an FCS error.
311 - 17 = Skip error: a packet was not large enough to cover the skipped bytes.
312 - 18 = L2 header malformed: the packet is not long enough to contain the L2 */
313
314
315 /* lower err_code = first-level descriptor of the work */
316 /* zero for packet submitted by hardware that isn't on the slow path */
317 uint64_t err_code : 8; /* type is cvmx_pip_err_t (union, so can't use directly */
318 } snoip;
319 struct
320 {
321 uint64_t bufs : 8; /**< HW sets this to the number of buffers used by this packet */
322 uint64_t unused : 8;
323 uint64_t vlan_valid : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
324 uint64_t vlan_stacked : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
325 uint64_t unassigned : 1;
326 uint64_t vlan_cfi : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
327 uint64_t vlan_id :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
328
329 uint64_t port:12; /**< MAC/PIP port number. */
330 uint64_t unassigned2:4;
331
332 uint64_t software : 1; /**< reserved for software use, hardware will clear on packet creation */
333 uint64_t unassigned3 : 1;
334 uint64_t is_rarp : 1; /**< set if the hardware determined that the packet is rarp */
335 uint64_t is_arp : 1; /**< set if the hardware determined that the packet is arp */
336 uint64_t is_bcast : 1; /**< set if the hardware determined that the packet is a broadcast */
337 uint64_t is_mcast : 1; /**< set if the hardware determined that the packet is a multi-cast */
338 uint64_t not_IP : 1; /**< set if the packet may not be IP (must be one in this case) */
339 uint64_t rcv_error : 1; /**< the receive interface hardware detected a receive error.
340 Failure indicated in err_code below, decode:
341 - 1 = partial error: a packet was partially received, but internal
342 buffering / bandwidth was not adequate to receive the entire packet.
343 - 2 = jabber error: the RGMII packet was too large and is truncated.
344 - 3 = overrun error: the RGMII packet is longer than allowed and had
345 an FCS error.
346 - 4 = oversize error: the RGMII packet is longer than allowed.
347 - 5 = alignment error: the RGMII packet is not an integer number of bytes
348 and had an FCS error (100M and 10M only).
349 - 6 = fragment error: the RGMII packet is shorter than allowed and had an
350 FCS error.
351 - 7 = GMX FCS error: the RGMII packet had an FCS error.
352 - 8 = undersize error: the RGMII packet is shorter than allowed.
353 - 9 = extend error: the RGMII packet had an extend error.
354 - 10 = length mismatch error: the RGMII packet had a length that did not
355 match the length field in the L2 HDR.
356 - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII packet had one or more
357 data reception errors (RXERR) or the SPI4 packet had one or more DIP4
358 errors.
359 - 12 = RGMII skip error/SPI4 Abort Error: the RGMII packet was not large
360 enough to cover the skipped bytes or the SPI4 packet was terminated
361 with an About EOPS.
362 - 13 = RGMII nibble error/SPI4 Port NXA Error: the RGMII packet had a
363 studder error (data not repeated - 10/100M only) or the SPI4 packet
364 was sent to an NXA.
365 - 16 = FCS error: a SPI4.2 packet had an FCS error.
366 - 17 = Skip error: a packet was not large enough to cover the skipped bytes.
367 - 18 = L2 header malformed: the packet is not long enough to contain the L2 */
368
369
370 /* lower err_code = first-level descriptor of the work */
371 /* zero for packet submitted by hardware that isn't on the slow path */
372 uint64_t err_code : 8; /* type is cvmx_pip_err_t (union, so can't use directly */
373 } snoip_cn68xx;
374 struct
375 {
376 uint64_t bufs : 8; /**< HW sets this to the number of buffers used by this packet */
377 uint64_t unused : 8;
378 uint64_t vlan_valid : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
379 uint64_t vlan_stacked : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
380 uint64_t unassigned : 1;
381 uint64_t vlan_cfi : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
382 uint64_t vlan_id :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
383 uint64_t pr : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
384 uint64_t unassigned2a :8;
385 uint64_t unassigned2 :4;
386
387 uint64_t software : 1; /**< reserved for software use, hardware will clear on packet creation */
388 uint64_t unassigned3 : 1;
389 uint64_t is_rarp : 1; /**< set if the hardware determined that the packet is rarp */
390 uint64_t is_arp : 1; /**< set if the hardware determined that the packet is arp */
391 uint64_t is_bcast : 1; /**< set if the hardware determined that the packet is a broadcast */
392 uint64_t is_mcast : 1; /**< set if the hardware determined that the packet is a multi-cast */
393 uint64_t not_IP : 1; /**< set if the packet may not be IP (must be one in this case) */
394 uint64_t rcv_error : 1; /**< the receive interface hardware detected a receive error.
395 Failure indicated in err_code below, decode:
396 - 1 = partial error: a packet was partially received, but internal
397 buffering / bandwidth was not adequate to receive the entire packet.
398 - 2 = jabber error: the RGMII packet was too large and is truncated.
399 - 3 = overrun error: the RGMII packet is longer than allowed and had
400 an FCS error.
401 - 4 = oversize error: the RGMII packet is longer than allowed.
402 - 5 = alignment error: the RGMII packet is not an integer number of bytes
403 and had an FCS error (100M and 10M only).
404 - 6 = fragment error: the RGMII packet is shorter than allowed and had an
405 FCS error.
406 - 7 = GMX FCS error: the RGMII packet had an FCS error.
407 - 8 = undersize error: the RGMII packet is shorter than allowed.
408 - 9 = extend error: the RGMII packet had an extend error.
409 - 10 = length mismatch error: the RGMII packet had a length that did not
410 match the length field in the L2 HDR.
411 - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII packet had one or more
412 data reception errors (RXERR) or the SPI4 packet had one or more DIP4
413 errors.
414 - 12 = RGMII skip error/SPI4 Abort Error: the RGMII packet was not large
415 enough to cover the skipped bytes or the SPI4 packet was terminated
416 with an About EOPS.
417 - 13 = RGMII nibble error/SPI4 Port NXA Error: the RGMII packet had a
418 studder error (data not repeated - 10/100M only) or the SPI4 packet
419 was sent to an NXA.
420 - 16 = FCS error: a SPI4.2 packet had an FCS error.
421 - 17 = Skip error: a packet was not large enough to cover the skipped bytes.
422 - 18 = L2 header malformed: the packet is not long enough to contain the L2 */
423
424
425 /* lower err_code = first-level descriptor of the work */
426 /* zero for packet submitted by hardware that isn't on the slow path */
427 uint64_t err_code : 8; /* type is cvmx_pip_err_t (union, so can't use directly */
428 } snoip_cn38xx;
429
430 } cvmx_pip_wqe_word2_t;
431
432 typedef union {
433 struct {
434 /**
435 * raw chksum result generated by the HW
436 */
437 uint16_t hw_chksum;
438 /**
439 * Field unused by hardware - available for software
440 */
441 uint8_t unused;
442 /**
443 * Next pointer used by hardware for list maintenance.
444 * May be written/read by HW before the work queue
445 * entry is scheduled to a PP (Only 36 bits used in
446 * Octeon 1)
447 */
448 uint64_t next_ptr : 40;
449
450 } cn38xx;
451 struct {
452 uint64_t l4ptr:8; /* 56..63 */
453 uint64_t unused0:8; /* 48..55 */
454 uint64_t l3ptr:8; /* 40..47 */
455 uint64_t l2ptr:8; /* 32..39 */
456 uint64_t unused1:18; /* 14..31 */
457 uint64_t bpid:6; /* 8..13 */
458 uint64_t unused2:2; /* 6..7 */
459 uint64_t pknd:6; /* 0..5 */
460 } cn68xx;
461 } cvmx_pip_wqe_word0_t;
462
463 typedef union {
464 uint64_t u64;
465 cvmx_pip_wqe_word0_t pip;
466 struct {
467 uint64_t unused:24;
468 uint64_t next_ptr:40; /* on cn68xx this is unused as well */
469
470 } raw;
471 } cvmx_wqe_word0_t;
472
473 typedef union {
474 uint64_t u64;
475 struct {
476 uint64_t len:16;
477 uint64_t varies:14;
478 /**
479 * the type of the tag (ORDERED, ATOMIC, NULL)
480 */
481 cvmx_pow_tag_type_t tag_type:2;
482 uint64_t tag:32;
483 } s;
484 struct {
485 uint64_t len:16;
486 uint64_t zero_0:1;
487 /**
488 * HW sets this to what it thought the priority of the input packet was
489 */
490 uint64_t qos:3;
491
492 uint64_t zero_1:1;
493 /**
494 * the group that the work queue entry will be scheduled to
495 */
496 uint64_t grp:6;
497 uint64_t zero_2:3;
498 cvmx_pow_tag_type_t tag_type:2;
499 uint64_t tag:32;
500 } cn68xx;
501 struct {
502 uint64_t len:16;
503 /**
504 * HW sets this to input physical port
505 */
506 uint64_t ipprt:6;
507
508 /**
509 * HW sets this to what it thought the priority of the input packet was
510 */
511 uint64_t qos:3;
512
513 /**
514 * the group that the work queue entry will be scheduled to
515 */
516 uint64_t grp:4;
517 uint64_t zero_2:1;
518 cvmx_pow_tag_type_t tag_type:2;
519 uint64_t tag:32;
520 } cn38xx;
521 } cvmx_wqe_word1_t;
522
523 /**
524 * Work queue entry format
525 *
526 * must be 8-byte aligned
527 */
528 typedef struct
529 {
530
531 /*****************************************************************
532 * WORD 0
533 * HW WRITE: the following 64 bits are filled by HW when a packet arrives
534 */
535
536 cvmx_wqe_word0_t word0;
537
538 /*****************************************************************
539 * WORD 1
540 * HW WRITE: the following 64 bits are filled by HW when a packet arrives
541 */
542
543 cvmx_wqe_word1_t word1;
544 /**
545 * WORD 2
546 * HW WRITE: the following 64-bits are filled in by hardware when a packet arrives
547 * This indicates a variety of status and error conditions.
548 */
549 cvmx_pip_wqe_word2_t word2;
550
551 /**
552 * Pointer to the first segment of the packet.
553 */
554 cvmx_buf_ptr_t packet_ptr;
555
556 /**
557 * HW WRITE: octeon will fill in a programmable amount from the
558 * packet, up to (at most, but perhaps less) the amount
559 * needed to fill the work queue entry to 128 bytes
560 * If the packet is recognized to be IP, the hardware starts (except that
561 * the IPv4 header is padded for appropriate alignment) writing here where
562 * the IP header starts.
563 * If the packet is not recognized to be IP, the hardware starts writing
564 * the beginning of the packet here.
565 */
566 uint8_t packet_data[96];
567
568
569 /**
570 * If desired, SW can make the work Q entry any length. For the
571 * purposes of discussion here, Assume 128B always, as this is all that
572 * the hardware deals with.
573 *
574 */
575
576 } CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t;
577
cvmx_wqe_get_port(cvmx_wqe_t * work)578 static inline int cvmx_wqe_get_port(cvmx_wqe_t *work)
579 {
580 int port;
581
582 if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
583 port = work->word2.s_cn68xx.port;
584 else
585 port = work->word1.cn38xx.ipprt;
586
587 return port;
588 }
589
cvmx_wqe_set_port(cvmx_wqe_t * work,int port)590 static inline void cvmx_wqe_set_port(cvmx_wqe_t *work, int port)
591 {
592 if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
593 port = work->word2.s_cn68xx.port = port;
594 else
595 port = work->word1.cn38xx.ipprt = port;
596 }
597
cvmx_wqe_get_grp(cvmx_wqe_t * work)598 static inline int cvmx_wqe_get_grp(cvmx_wqe_t *work)
599 {
600 int grp;
601
602 if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
603 grp = work->word1.cn68xx.grp;
604 else
605 grp = work->word1.cn38xx.grp;
606
607 return grp;
608 }
609
cvmx_wqe_set_grp(cvmx_wqe_t * work,int grp)610 static inline void cvmx_wqe_set_grp(cvmx_wqe_t *work, int grp)
611 {
612 if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
613 work->word1.cn68xx.grp = grp;
614 else
615 work->word1.cn38xx.grp = grp;
616 }
617
cvmx_wqe_get_qos(cvmx_wqe_t * work)618 static inline int cvmx_wqe_get_qos(cvmx_wqe_t *work)
619 {
620 int qos;
621
622 if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
623 qos = work->word1.cn68xx.qos;
624 else
625 qos = work->word1.cn38xx.qos;
626
627 return qos;
628 }
629
cvmx_wqe_set_qos(cvmx_wqe_t * work,int qos)630 static inline void cvmx_wqe_set_qos(cvmx_wqe_t *work, int qos)
631 {
632 if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
633 work->word1.cn68xx.qos = qos;
634 else
635 work->word1.cn38xx.qos = qos;
636 }
637
cvmx_wqe_get_len(cvmx_wqe_t * work)638 static inline int cvmx_wqe_get_len(cvmx_wqe_t *work)
639 {
640 int len;
641
642 if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
643 len = work->word1.cn68xx.len;
644 else
645 len = work->word1.cn38xx.len;
646
647 return len;
648 }
649
cvmx_wqe_set_len(cvmx_wqe_t * work,int len)650 static inline void cvmx_wqe_set_len(cvmx_wqe_t *work, int len)
651 {
652 if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
653 work->word1.cn68xx.len = len;
654 else
655 work->word1.cn38xx.len = len;
656 }
657
cvmx_wqe_get_tag(cvmx_wqe_t * work)658 static inline uint32_t cvmx_wqe_get_tag(cvmx_wqe_t *work)
659 {
660 return work->word1.s.tag;
661 }
662
cvmx_wqe_set_tag(cvmx_wqe_t * work,uint32_t tag)663 static inline void cvmx_wqe_set_tag(cvmx_wqe_t *work, uint32_t tag)
664 {
665 work->word1.s.tag = tag;
666 }
667
cvmx_wqe_get_tt(cvmx_wqe_t * work)668 static inline int cvmx_wqe_get_tt(cvmx_wqe_t *work)
669 {
670 return work->word1.s.tag_type;
671 }
672
cvmx_wqe_set_tt(cvmx_wqe_t * work,int tt)673 static inline void cvmx_wqe_set_tt(cvmx_wqe_t *work, int tt)
674 {
675 if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
676 {
677 work->word1.cn68xx.tag_type = (cvmx_pow_tag_type_t)tt;
678 work->word1.cn68xx.zero_2 = 0;
679 }
680 else
681 {
682 work->word1.cn38xx.tag_type = (cvmx_pow_tag_type_t)tt;
683 work->word1.cn38xx.zero_2 = 0;
684 }
685 }
686
cvmx_wqe_get_unused8(cvmx_wqe_t * work)687 static inline int cvmx_wqe_get_unused8(cvmx_wqe_t *work)
688 {
689 int len;
690
691 if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
692 len = work->word0.pip.cn68xx.unused1;
693 else
694 len = work->word0.pip.cn38xx.unused;
695
696 return len;
697 }
698
cvmx_wqe_set_unused8(cvmx_wqe_t * work,int v)699 static inline void cvmx_wqe_set_unused8(cvmx_wqe_t *work, int v)
700 {
701 if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE))
702 work->word0.pip.cn68xx.unused1 = v;
703 else
704 work->word0.pip.cn38xx.unused = v;
705 }
706
707 #ifdef __cplusplus
708 }
709 #endif
710
711 #endif /* __CVMX_WQE_H__ */
712