1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _I40E_ADMINQ_CMD_H_ 6 #define _I40E_ADMINQ_CMD_H_ 7 8 /* This header file defines the i40e Admin Queue commands and is shared between 9 * i40e Firmware and Software. 10 * 11 * This file needs to comply with the Linux Kernel coding style. 12 */ 13 14 #define I40E_FW_API_VERSION_MAJOR 0x0001 15 #define I40E_FW_API_VERSION_MINOR_X722 0x000B 16 #define I40E_FW_API_VERSION_MINOR_X710 0x000C 17 18 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 19 I40E_FW_API_VERSION_MINOR_X710 : \ 20 I40E_FW_API_VERSION_MINOR_X722) 21 22 /* API version 1.7 implements additional link and PHY-specific APIs */ 23 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 24 /* API version 1.9 for X722 implements additional link and PHY-specific APIs */ 25 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009 26 /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */ 27 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006 28 /* API version 1.10 for X722 devices adds ability to request FEC encoding */ 29 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A 30 31 struct i40e_aq_desc { 32 __le16 flags; 33 __le16 opcode; 34 __le16 datalen; 35 __le16 retval; 36 __le32 cookie_high; 37 __le32 cookie_low; 38 union { 39 struct { 40 __le32 param0; 41 __le32 param1; 42 __le32 param2; 43 __le32 param3; 44 } internal; 45 struct { 46 __le32 param0; 47 __le32 param1; 48 __le32 addr_high; 49 __le32 addr_low; 50 } external; 51 u8 raw[16]; 52 } params; 53 }; 54 55 /* Flags sub-structure 56 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 57 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 58 */ 59 60 /* command flags and offsets*/ 61 #define I40E_AQ_FLAG_DD_SHIFT 0 62 #define I40E_AQ_FLAG_CMP_SHIFT 1 63 #define I40E_AQ_FLAG_ERR_SHIFT 2 64 #define I40E_AQ_FLAG_VFE_SHIFT 3 65 #define I40E_AQ_FLAG_LB_SHIFT 9 66 #define I40E_AQ_FLAG_RD_SHIFT 10 67 #define I40E_AQ_FLAG_VFC_SHIFT 11 68 #define I40E_AQ_FLAG_BUF_SHIFT 12 69 #define I40E_AQ_FLAG_SI_SHIFT 13 70 #define I40E_AQ_FLAG_EI_SHIFT 14 71 #define I40E_AQ_FLAG_FE_SHIFT 15 72 73 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 74 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 75 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 76 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 77 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 78 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 79 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 80 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 81 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 82 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 83 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 84 85 /* error codes */ 86 enum i40e_admin_queue_err { 87 I40E_AQ_RC_OK = 0, /* success */ 88 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 89 I40E_AQ_RC_ENOENT = 2, /* No such element */ 90 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 91 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 92 I40E_AQ_RC_EIO = 5, /* I/O error */ 93 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 94 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 95 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 96 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 97 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 98 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 99 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 100 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 101 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 102 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 103 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 104 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 105 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 106 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 107 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 108 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 109 I40E_AQ_RC_EFBIG = 22, /* File too large */ 110 }; 111 112 /* Admin Queue command opcodes */ 113 enum i40e_admin_queue_opc { 114 /* aq commands */ 115 i40e_aqc_opc_get_version = 0x0001, 116 i40e_aqc_opc_driver_version = 0x0002, 117 i40e_aqc_opc_queue_shutdown = 0x0003, 118 i40e_aqc_opc_set_pf_context = 0x0004, 119 120 /* resource ownership */ 121 i40e_aqc_opc_request_resource = 0x0008, 122 i40e_aqc_opc_release_resource = 0x0009, 123 124 i40e_aqc_opc_list_func_capabilities = 0x000A, 125 i40e_aqc_opc_list_dev_capabilities = 0x000B, 126 127 /* Proxy commands */ 128 i40e_aqc_opc_set_proxy_config = 0x0104, 129 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 130 131 /* LAA */ 132 i40e_aqc_opc_mac_address_read = 0x0107, 133 i40e_aqc_opc_mac_address_write = 0x0108, 134 135 /* PXE */ 136 i40e_aqc_opc_clear_pxe_mode = 0x0110, 137 138 /* WoL commands */ 139 i40e_aqc_opc_set_wol_filter = 0x0120, 140 i40e_aqc_opc_get_wake_reason = 0x0121, 141 i40e_aqc_opc_clear_all_wol_filters = 0x025E, 142 143 /* internal switch commands */ 144 i40e_aqc_opc_get_switch_config = 0x0200, 145 i40e_aqc_opc_add_statistics = 0x0201, 146 i40e_aqc_opc_remove_statistics = 0x0202, 147 i40e_aqc_opc_set_port_parameters = 0x0203, 148 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 149 i40e_aqc_opc_set_switch_config = 0x0205, 150 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 151 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 152 153 i40e_aqc_opc_add_vsi = 0x0210, 154 i40e_aqc_opc_update_vsi_parameters = 0x0211, 155 i40e_aqc_opc_get_vsi_parameters = 0x0212, 156 157 i40e_aqc_opc_add_pv = 0x0220, 158 i40e_aqc_opc_update_pv_parameters = 0x0221, 159 i40e_aqc_opc_get_pv_parameters = 0x0222, 160 161 i40e_aqc_opc_add_veb = 0x0230, 162 i40e_aqc_opc_update_veb_parameters = 0x0231, 163 i40e_aqc_opc_get_veb_parameters = 0x0232, 164 165 i40e_aqc_opc_delete_element = 0x0243, 166 167 i40e_aqc_opc_add_macvlan = 0x0250, 168 i40e_aqc_opc_remove_macvlan = 0x0251, 169 i40e_aqc_opc_add_vlan = 0x0252, 170 i40e_aqc_opc_remove_vlan = 0x0253, 171 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 172 i40e_aqc_opc_add_tag = 0x0255, 173 i40e_aqc_opc_remove_tag = 0x0256, 174 i40e_aqc_opc_add_multicast_etag = 0x0257, 175 i40e_aqc_opc_remove_multicast_etag = 0x0258, 176 i40e_aqc_opc_update_tag = 0x0259, 177 i40e_aqc_opc_add_control_packet_filter = 0x025A, 178 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 179 i40e_aqc_opc_add_cloud_filters = 0x025C, 180 i40e_aqc_opc_remove_cloud_filters = 0x025D, 181 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 182 i40e_aqc_opc_replace_cloud_filters = 0x025F, 183 184 i40e_aqc_opc_add_mirror_rule = 0x0260, 185 i40e_aqc_opc_delete_mirror_rule = 0x0261, 186 187 /* Dynamic Device Personalization */ 188 i40e_aqc_opc_write_personalization_profile = 0x0270, 189 i40e_aqc_opc_get_personalization_profile_list = 0x0271, 190 191 /* DCB commands */ 192 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 193 i40e_aqc_opc_dcb_updated = 0x0302, 194 i40e_aqc_opc_set_dcb_parameters = 0x0303, 195 196 /* TX scheduler */ 197 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 198 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 199 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 200 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 201 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 202 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 203 204 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 205 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 206 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 207 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 208 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 209 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 210 i40e_aqc_opc_query_port_ets_config = 0x0419, 211 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 212 i40e_aqc_opc_suspend_port_tx = 0x041B, 213 i40e_aqc_opc_resume_port_tx = 0x041C, 214 i40e_aqc_opc_configure_partition_bw = 0x041D, 215 /* hmc */ 216 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 217 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 218 219 /* phy commands*/ 220 i40e_aqc_opc_get_phy_abilities = 0x0600, 221 i40e_aqc_opc_set_phy_config = 0x0601, 222 i40e_aqc_opc_set_mac_config = 0x0603, 223 i40e_aqc_opc_set_link_restart_an = 0x0605, 224 i40e_aqc_opc_get_link_status = 0x0607, 225 i40e_aqc_opc_set_phy_int_mask = 0x0613, 226 i40e_aqc_opc_get_local_advt_reg = 0x0614, 227 i40e_aqc_opc_set_local_advt_reg = 0x0615, 228 i40e_aqc_opc_get_partner_advt = 0x0616, 229 i40e_aqc_opc_set_lb_modes = 0x0618, 230 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 231 i40e_aqc_opc_set_phy_debug = 0x0622, 232 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 233 i40e_aqc_opc_run_phy_activity = 0x0626, 234 i40e_aqc_opc_set_phy_register = 0x0628, 235 i40e_aqc_opc_get_phy_register = 0x0629, 236 237 /* NVM commands */ 238 i40e_aqc_opc_nvm_read = 0x0701, 239 i40e_aqc_opc_nvm_erase = 0x0702, 240 i40e_aqc_opc_nvm_update = 0x0703, 241 i40e_aqc_opc_nvm_config_read = 0x0704, 242 i40e_aqc_opc_nvm_config_write = 0x0705, 243 i40e_aqc_opc_nvm_update_in_process = 0x0706, 244 i40e_aqc_opc_rollback_revision_update = 0x0707, 245 i40e_aqc_opc_oem_post_update = 0x0720, 246 i40e_aqc_opc_thermal_sensor = 0x0721, 247 248 /* virtualization commands */ 249 i40e_aqc_opc_send_msg_to_pf = 0x0801, 250 i40e_aqc_opc_send_msg_to_vf = 0x0802, 251 i40e_aqc_opc_send_msg_to_peer = 0x0803, 252 253 /* alternate structure */ 254 i40e_aqc_opc_alternate_write = 0x0900, 255 i40e_aqc_opc_alternate_write_indirect = 0x0901, 256 i40e_aqc_opc_alternate_read = 0x0902, 257 i40e_aqc_opc_alternate_read_indirect = 0x0903, 258 i40e_aqc_opc_alternate_write_done = 0x0904, 259 i40e_aqc_opc_alternate_set_mode = 0x0905, 260 i40e_aqc_opc_alternate_clear_port = 0x0906, 261 262 /* LLDP commands */ 263 i40e_aqc_opc_lldp_get_mib = 0x0A00, 264 i40e_aqc_opc_lldp_update_mib = 0x0A01, 265 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 266 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 267 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 268 i40e_aqc_opc_lldp_stop = 0x0A05, 269 i40e_aqc_opc_lldp_start = 0x0A06, 270 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 271 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 272 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 273 i40e_aqc_opc_lldp_restore = 0x0A0A, 274 275 /* Tunnel commands */ 276 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 277 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 278 i40e_aqc_opc_set_rss_key = 0x0B02, 279 i40e_aqc_opc_set_rss_lut = 0x0B03, 280 i40e_aqc_opc_get_rss_key = 0x0B04, 281 i40e_aqc_opc_get_rss_lut = 0x0B05, 282 283 /* Async Events */ 284 i40e_aqc_opc_event_lan_overflow = 0x1001, 285 286 /* OEM commands */ 287 i40e_aqc_opc_oem_parameter_change = 0xFE00, 288 i40e_aqc_opc_oem_device_status_change = 0xFE01, 289 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 290 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 291 292 /* debug commands */ 293 i40e_aqc_opc_debug_read_reg = 0xFF03, 294 i40e_aqc_opc_debug_write_reg = 0xFF04, 295 i40e_aqc_opc_debug_modify_reg = 0xFF07, 296 i40e_aqc_opc_debug_dump_internals = 0xFF08, 297 }; 298 299 /* command structures and indirect data structures */ 300 301 /* Structure naming conventions: 302 * - no suffix for direct command descriptor structures 303 * - _data for indirect sent data 304 * - _resp for indirect return data (data which is both will use _data) 305 * - _completion for direct return data 306 * - _element_ for repeated elements (may also be _data or _resp) 307 * 308 * Command structures are expected to overlay the params.raw member of the basic 309 * descriptor, and as such cannot exceed 16 bytes in length. 310 */ 311 312 /* This macro is used to generate a compilation error if a structure 313 * is not exactly the correct length. It gives a divide by zero error if the 314 * structure is not of the correct size, otherwise it creates an enum that is 315 * never used. 316 */ 317 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 318 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 319 320 /* This macro is used extensively to ensure that command structures are 16 321 * bytes in length as they have to map to the raw array of that size. 322 */ 323 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 324 325 /* internal (0x00XX) commands */ 326 327 /* Get version (direct 0x0001) */ 328 struct i40e_aqc_get_version { 329 __le32 rom_ver; 330 __le32 fw_build; 331 __le16 fw_major; 332 __le16 fw_minor; 333 __le16 api_major; 334 __le16 api_minor; 335 }; 336 337 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 338 339 /* Send driver version (indirect 0x0002) */ 340 struct i40e_aqc_driver_version { 341 u8 driver_major_ver; 342 u8 driver_minor_ver; 343 u8 driver_build_ver; 344 u8 driver_subbuild_ver; 345 u8 reserved[4]; 346 __le32 address_high; 347 __le32 address_low; 348 }; 349 350 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 351 352 /* Queue Shutdown (direct 0x0003) */ 353 struct i40e_aqc_queue_shutdown { 354 __le32 driver_unloading; 355 #define I40E_AQ_DRIVER_UNLOADING 0x1 356 u8 reserved[12]; 357 }; 358 359 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 360 361 /* Set PF context (0x0004, direct) */ 362 struct i40e_aqc_set_pf_context { 363 u8 pf_id; 364 u8 reserved[15]; 365 }; 366 367 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 368 369 /* Request resource ownership (direct 0x0008) 370 * Release resource ownership (direct 0x0009) 371 */ 372 #define I40E_AQ_RESOURCE_NVM 1 373 #define I40E_AQ_RESOURCE_SDP 2 374 #define I40E_AQ_RESOURCE_ACCESS_READ 1 375 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 376 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 377 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 378 379 struct i40e_aqc_request_resource { 380 __le16 resource_id; 381 __le16 access_type; 382 __le32 timeout; 383 __le32 resource_number; 384 u8 reserved[4]; 385 }; 386 387 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 388 389 /* Get function capabilities (indirect 0x000A) 390 * Get device capabilities (indirect 0x000B) 391 */ 392 struct i40e_aqc_list_capabilites { 393 u8 command_flags; 394 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 395 u8 pf_index; 396 u8 reserved[2]; 397 __le32 count; 398 __le32 addr_high; 399 __le32 addr_low; 400 }; 401 402 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 403 404 struct i40e_aqc_list_capabilities_element_resp { 405 __le16 id; 406 u8 major_rev; 407 u8 minor_rev; 408 __le32 number; 409 __le32 logical_id; 410 __le32 phys_id; 411 u8 reserved[16]; 412 }; 413 414 /* list of caps */ 415 416 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 417 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 418 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 419 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 420 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 421 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 422 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 423 #define I40E_AQ_CAP_ID_SRIOV 0x0012 424 #define I40E_AQ_CAP_ID_VF 0x0013 425 #define I40E_AQ_CAP_ID_VMDQ 0x0014 426 #define I40E_AQ_CAP_ID_8021QBG 0x0015 427 #define I40E_AQ_CAP_ID_8021QBR 0x0016 428 #define I40E_AQ_CAP_ID_VSI 0x0017 429 #define I40E_AQ_CAP_ID_DCB 0x0018 430 #define I40E_AQ_CAP_ID_FCOE 0x0021 431 #define I40E_AQ_CAP_ID_ISCSI 0x0022 432 #define I40E_AQ_CAP_ID_RSS 0x0040 433 #define I40E_AQ_CAP_ID_RXQ 0x0041 434 #define I40E_AQ_CAP_ID_TXQ 0x0042 435 #define I40E_AQ_CAP_ID_MSIX 0x0043 436 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 437 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 438 #define I40E_AQ_CAP_ID_1588 0x0046 439 #define I40E_AQ_CAP_ID_IWARP 0x0051 440 #define I40E_AQ_CAP_ID_LED 0x0061 441 #define I40E_AQ_CAP_ID_SDP 0x0062 442 #define I40E_AQ_CAP_ID_MDIO 0x0063 443 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 444 #define I40E_AQ_CAP_ID_DIS_UNUSED_PORTS 0x0067 445 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 446 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 447 #define I40E_AQ_CAP_ID_CEM 0x00F2 448 449 /* Set CPPM Configuration (direct 0x0103) */ 450 struct i40e_aqc_cppm_configuration { 451 __le16 command_flags; 452 #define I40E_AQ_CPPM_EN_LTRC 0x0800 453 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 454 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 455 #define I40E_AQ_CPPM_EN_HPTC 0x4000 456 #define I40E_AQ_CPPM_EN_DMARC 0x8000 457 __le16 ttlx; 458 __le32 dmacr; 459 __le16 dmcth; 460 u8 hptc; 461 u8 reserved; 462 __le32 pfltrc; 463 }; 464 465 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 466 467 /* Set ARP Proxy command / response (indirect 0x0104) */ 468 struct i40e_aqc_arp_proxy_data { 469 __le16 command_flags; 470 #define I40E_AQ_ARP_INIT_IPV4 0x0800 471 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 472 #define I40E_AQ_ARP_ENA 0x2000 473 #define I40E_AQ_ARP_ADD_IPV4 0x4000 474 #define I40E_AQ_ARP_DEL_IPV4 0x8000 475 __le16 table_id; 476 __le32 enabled_offloads; 477 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 478 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 479 __le32 ip_addr; 480 u8 mac_addr[6]; 481 u8 reserved[2]; 482 }; 483 484 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 485 486 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 487 struct i40e_aqc_ns_proxy_data { 488 __le16 table_idx_mac_addr_0; 489 __le16 table_idx_mac_addr_1; 490 __le16 table_idx_ipv6_0; 491 __le16 table_idx_ipv6_1; 492 __le16 control; 493 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 494 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 495 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 496 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 497 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 498 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 499 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 500 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 501 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 502 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 503 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 504 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 505 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 506 u8 mac_addr_0[6]; 507 u8 mac_addr_1[6]; 508 u8 local_mac_addr[6]; 509 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 510 u8 ipv6_addr_1[16]; 511 }; 512 513 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 514 515 /* Manage LAA Command (0x0106) - obsolete */ 516 struct i40e_aqc_mng_laa { 517 __le16 command_flags; 518 #define I40E_AQ_LAA_FLAG_WR 0x8000 519 u8 reserved[2]; 520 __le32 sal; 521 __le16 sah; 522 u8 reserved2[6]; 523 }; 524 525 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 526 527 /* Manage MAC Address Read Command (indirect 0x0107) */ 528 struct i40e_aqc_mac_address_read { 529 __le16 command_flags; 530 #define I40E_AQC_LAN_ADDR_VALID 0x10 531 #define I40E_AQC_SAN_ADDR_VALID 0x20 532 #define I40E_AQC_PORT_ADDR_VALID 0x40 533 #define I40E_AQC_WOL_ADDR_VALID 0x80 534 #define I40E_AQC_MC_MAG_EN_VALID 0x100 535 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200 536 #define I40E_AQC_ADDR_VALID_MASK 0x3F0 537 u8 reserved[6]; 538 __le32 addr_high; 539 __le32 addr_low; 540 }; 541 542 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 543 544 struct i40e_aqc_mac_address_read_data { 545 u8 pf_lan_mac[6]; 546 u8 pf_san_mac[6]; 547 u8 port_mac[6]; 548 u8 pf_wol_mac[6]; 549 }; 550 551 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 552 553 /* Manage MAC Address Write Command (0x0108) */ 554 struct i40e_aqc_mac_address_write { 555 __le16 command_flags; 556 #define I40E_AQC_MC_MAG_EN 0x0100 557 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 558 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 559 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 560 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 561 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 562 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 563 564 __le16 mac_sah; 565 __le32 mac_sal; 566 u8 reserved[8]; 567 }; 568 569 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 570 571 /* PXE commands (0x011x) */ 572 573 /* Clear PXE Command and response (direct 0x0110) */ 574 struct i40e_aqc_clear_pxe { 575 u8 rx_cnt; 576 u8 reserved[15]; 577 }; 578 579 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 580 581 /* Set WoL Filter (0x0120) */ 582 583 struct i40e_aqc_set_wol_filter { 584 __le16 filter_index; 585 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 586 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 587 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 588 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 589 590 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 591 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 592 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 593 __le16 cmd_flags; 594 #define I40E_AQC_SET_WOL_FILTER 0x8000 595 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 596 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 597 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 598 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 599 __le16 valid_flags; 600 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 601 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 602 u8 reserved[2]; 603 __le32 address_high; 604 __le32 address_low; 605 }; 606 607 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 608 609 struct i40e_aqc_set_wol_filter_data { 610 u8 filter[128]; 611 u8 mask[16]; 612 }; 613 614 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 615 616 /* Get Wake Reason (0x0121) */ 617 618 struct i40e_aqc_get_wake_reason_completion { 619 u8 reserved_1[2]; 620 __le16 wake_reason; 621 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 622 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 623 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 624 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 625 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 626 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 627 u8 reserved_2[12]; 628 }; 629 630 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 631 632 /* Switch configuration commands (0x02xx) */ 633 634 /* Used by many indirect commands that only pass an seid and a buffer in the 635 * command 636 */ 637 struct i40e_aqc_switch_seid { 638 __le16 seid; 639 u8 reserved[6]; 640 __le32 addr_high; 641 __le32 addr_low; 642 }; 643 644 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 645 646 /* Get Switch Configuration command (indirect 0x0200) 647 * uses i40e_aqc_switch_seid for the descriptor 648 */ 649 struct i40e_aqc_get_switch_config_header_resp { 650 __le16 num_reported; 651 __le16 num_total; 652 u8 reserved[12]; 653 }; 654 655 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 656 657 struct i40e_aqc_switch_config_element_resp { 658 u8 element_type; 659 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 660 #define I40E_AQ_SW_ELEM_TYPE_PF 2 661 #define I40E_AQ_SW_ELEM_TYPE_VF 3 662 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 663 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 664 #define I40E_AQ_SW_ELEM_TYPE_PV 16 665 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 666 #define I40E_AQ_SW_ELEM_TYPE_PA 18 667 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 668 u8 revision; 669 #define I40E_AQ_SW_ELEM_REV_1 1 670 __le16 seid; 671 __le16 uplink_seid; 672 __le16 downlink_seid; 673 u8 reserved[3]; 674 u8 connection_type; 675 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 676 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 677 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 678 __le16 scheduler_id; 679 __le16 element_info; 680 }; 681 682 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 683 684 /* Get Switch Configuration (indirect 0x0200) 685 * an array of elements are returned in the response buffer 686 * the first in the array is the header, remainder are elements 687 */ 688 struct i40e_aqc_get_switch_config_resp { 689 struct i40e_aqc_get_switch_config_header_resp header; 690 struct i40e_aqc_switch_config_element_resp element[1]; 691 }; 692 693 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 694 695 /* Add Statistics (direct 0x0201) 696 * Remove Statistics (direct 0x0202) 697 */ 698 struct i40e_aqc_add_remove_statistics { 699 __le16 seid; 700 __le16 vlan; 701 __le16 stat_index; 702 u8 reserved[10]; 703 }; 704 705 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 706 707 /* Set Port Parameters command (direct 0x0203) */ 708 struct i40e_aqc_set_port_parameters { 709 __le16 command_flags; 710 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 711 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 712 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 713 __le16 bad_frame_vsi; 714 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 715 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 716 __le16 default_seid; /* reserved for command */ 717 u8 reserved[10]; 718 }; 719 720 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 721 722 /* Get Switch Resource Allocation (indirect 0x0204) */ 723 struct i40e_aqc_get_switch_resource_alloc { 724 u8 num_entries; /* reserved for command */ 725 u8 reserved[7]; 726 __le32 addr_high; 727 __le32 addr_low; 728 }; 729 730 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 731 732 /* expect an array of these structs in the response buffer */ 733 struct i40e_aqc_switch_resource_alloc_element_resp { 734 u8 resource_type; 735 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 736 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 737 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 738 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 739 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 740 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 741 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 742 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 743 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 744 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 745 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 746 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 747 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 748 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 749 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 750 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 751 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 752 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 753 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 754 u8 reserved1; 755 __le16 guaranteed; 756 __le16 total; 757 __le16 used; 758 __le16 total_unalloced; 759 u8 reserved2[6]; 760 }; 761 762 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 763 764 /* Set Switch Configuration (direct 0x0205) */ 765 struct i40e_aqc_set_switch_config { 766 __le16 flags; 767 /* flags used for both fields below */ 768 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 769 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 770 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004 771 __le16 valid_flags; 772 /* The ethertype in switch_tag is dropped on ingress and used 773 * internally by the switch. Set this to zero for the default 774 * of 0x88a8 (802.1ad). Should be zero for firmware API 775 * versions lower than 1.7. 776 */ 777 __le16 switch_tag; 778 /* The ethertypes in first_tag and second_tag are used to 779 * match the outer and inner VLAN tags (respectively) when HW 780 * double VLAN tagging is enabled via the set port parameters 781 * AQ command. Otherwise these are both ignored. Set them to 782 * zero for their defaults of 0x8100 (802.1Q). Should be zero 783 * for firmware API versions lower than 1.7. 784 */ 785 __le16 first_tag; 786 __le16 second_tag; 787 /* Next byte is split into following: 788 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 789 * Bit 6 : 0 : Destination Port, 1: source port 790 * Bit 5..4 : L4 type 791 * 0: rsvd 792 * 1: TCP 793 * 2: UDP 794 * 3: Both TCP and UDP 795 * Bits 3:0 Mode 796 * 0: default mode 797 * 1: L4 port only mode 798 * 2: non-tunneled mode 799 * 3: tunneled mode 800 */ 801 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 802 803 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 804 805 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 806 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 807 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 808 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 809 810 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 811 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 812 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 813 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 814 u8 mode; 815 u8 rsvd5[5]; 816 }; 817 818 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 819 820 /* Read Receive control registers (direct 0x0206) 821 * Write Receive control registers (direct 0x0207) 822 * used for accessing Rx control registers that can be 823 * slow and need special handling when under high Rx load 824 */ 825 struct i40e_aqc_rx_ctl_reg_read_write { 826 __le32 reserved1; 827 __le32 address; 828 __le32 reserved2; 829 __le32 value; 830 }; 831 832 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 833 834 /* Add VSI (indirect 0x0210) 835 * this indirect command uses struct i40e_aqc_vsi_properties_data 836 * as the indirect buffer (128 bytes) 837 * 838 * Update VSI (indirect 0x211) 839 * uses the same data structure as Add VSI 840 * 841 * Get VSI (indirect 0x0212) 842 * uses the same completion and data structure as Add VSI 843 */ 844 struct i40e_aqc_add_get_update_vsi { 845 __le16 uplink_seid; 846 u8 connection_type; 847 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 848 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 849 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 850 u8 reserved1; 851 u8 vf_id; 852 u8 reserved2; 853 __le16 vsi_flags; 854 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 855 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 856 #define I40E_AQ_VSI_TYPE_VF 0x0 857 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 858 #define I40E_AQ_VSI_TYPE_PF 0x2 859 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 860 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 861 __le32 addr_high; 862 __le32 addr_low; 863 }; 864 865 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 866 867 struct i40e_aqc_add_get_update_vsi_completion { 868 __le16 seid; 869 __le16 vsi_number; 870 __le16 vsi_used; 871 __le16 vsi_free; 872 __le32 addr_high; 873 __le32 addr_low; 874 }; 875 876 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 877 878 struct i40e_aqc_vsi_properties_data { 879 /* first 96 byte are written by SW */ 880 __le16 valid_sections; 881 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 882 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 883 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 884 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 885 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 886 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 887 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 888 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 889 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 890 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 891 /* switch section */ 892 __le16 switch_id; /* 12bit id combined with flags below */ 893 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 894 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 895 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 896 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 897 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 898 u8 sw_reserved[2]; 899 /* security section */ 900 u8 sec_flags; 901 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 902 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 903 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 904 u8 sec_reserved; 905 /* VLAN section */ 906 __le16 pvid; /* VLANS include priority bits */ 907 __le16 fcoe_pvid; 908 u8 port_vlan_flags; 909 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 910 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 911 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 912 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 913 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 914 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 915 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 916 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 917 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 918 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 919 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 920 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 921 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 922 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 923 u8 pvlan_reserved[3]; 924 /* ingress egress up sections */ 925 __le32 ingress_table; /* bitmap, 3 bits per up */ 926 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 927 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 928 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 929 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 930 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 931 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 932 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 933 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 934 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 935 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 936 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 937 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 938 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 939 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 940 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 941 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 942 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 943 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 944 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 945 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 946 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 947 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 948 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 949 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 950 __le32 egress_table; /* same defines as for ingress table */ 951 /* cascaded PV section */ 952 __le16 cas_pv_tag; 953 u8 cas_pv_flags; 954 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 955 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 956 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 957 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 958 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 959 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 960 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 961 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 962 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 963 u8 cas_pv_reserved; 964 /* queue mapping section */ 965 __le16 mapping_flags; 966 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 967 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 968 __le16 queue_mapping[16]; 969 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 970 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 971 __le16 tc_mapping[8]; 972 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 973 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 974 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 975 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 976 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 977 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 978 /* queueing option section */ 979 u8 queueing_opt_flags; 980 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 981 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 982 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 983 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 984 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 985 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 986 u8 queueing_opt_reserved[3]; 987 /* scheduler section */ 988 u8 up_enable_bits; 989 u8 sched_reserved; 990 /* outer up section */ 991 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 992 u8 cmd_reserved[8]; 993 /* last 32 bytes are written by FW */ 994 __le16 qs_handle[8]; 995 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 996 __le16 stat_counter_idx; 997 __le16 sched_id; 998 u8 resp_reserved[12]; 999 }; 1000 1001 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 1002 1003 /* Add Port Virtualizer (direct 0x0220) 1004 * also used for update PV (direct 0x0221) but only flags are used 1005 * (IS_CTRL_PORT only works on add PV) 1006 */ 1007 struct i40e_aqc_add_update_pv { 1008 __le16 command_flags; 1009 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 1010 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 1011 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 1012 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 1013 __le16 uplink_seid; 1014 __le16 connected_seid; 1015 u8 reserved[10]; 1016 }; 1017 1018 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 1019 1020 struct i40e_aqc_add_update_pv_completion { 1021 /* reserved for update; for add also encodes error if rc == ENOSPC */ 1022 __le16 pv_seid; 1023 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1024 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1025 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1026 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1027 u8 reserved[14]; 1028 }; 1029 1030 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1031 1032 /* Get PV Params (direct 0x0222) 1033 * uses i40e_aqc_switch_seid for the descriptor 1034 */ 1035 1036 struct i40e_aqc_get_pv_params_completion { 1037 __le16 seid; 1038 __le16 default_stag; 1039 __le16 pv_flags; /* same flags as add_pv */ 1040 #define I40E_AQC_GET_PV_PV_TYPE 0x1 1041 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1042 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1043 u8 reserved[8]; 1044 __le16 default_port_seid; 1045 }; 1046 1047 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1048 1049 /* Add VEB (direct 0x0230) */ 1050 struct i40e_aqc_add_veb { 1051 __le16 uplink_seid; 1052 __le16 downlink_seid; 1053 __le16 veb_flags; 1054 #define I40E_AQC_ADD_VEB_FLOATING 0x1 1055 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1056 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1057 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1058 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1059 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1060 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1061 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1062 u8 enable_tcs; 1063 u8 reserved[9]; 1064 }; 1065 1066 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1067 1068 struct i40e_aqc_add_veb_completion { 1069 u8 reserved[6]; 1070 __le16 switch_seid; 1071 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1072 __le16 veb_seid; 1073 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1074 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1075 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1076 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1077 __le16 statistic_index; 1078 __le16 vebs_used; 1079 __le16 vebs_free; 1080 }; 1081 1082 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1083 1084 /* Get VEB Parameters (direct 0x0232) 1085 * uses i40e_aqc_switch_seid for the descriptor 1086 */ 1087 struct i40e_aqc_get_veb_parameters_completion { 1088 __le16 seid; 1089 __le16 switch_id; 1090 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1091 __le16 statistic_index; 1092 __le16 vebs_used; 1093 __le16 vebs_free; 1094 u8 reserved[4]; 1095 }; 1096 1097 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1098 1099 /* Delete Element (direct 0x0243) 1100 * uses the generic i40e_aqc_switch_seid 1101 */ 1102 1103 /* Add MAC-VLAN (indirect 0x0250) */ 1104 1105 /* used for the command for most vlan commands */ 1106 struct i40e_aqc_macvlan { 1107 __le16 num_addresses; 1108 __le16 seid[3]; 1109 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1110 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1111 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1112 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1113 __le32 addr_high; 1114 __le32 addr_low; 1115 }; 1116 1117 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1118 1119 /* indirect data for command and response */ 1120 struct i40e_aqc_add_macvlan_element_data { 1121 u8 mac_addr[6]; 1122 __le16 vlan_tag; 1123 __le16 flags; 1124 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1125 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1126 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1127 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1128 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1129 __le16 queue_number; 1130 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1131 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1132 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1133 /* response section */ 1134 u8 match_method; 1135 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1136 #define I40E_AQC_MM_HASH_MATCH 0x02 1137 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1138 u8 reserved1[3]; 1139 }; 1140 1141 struct i40e_aqc_add_remove_macvlan_completion { 1142 __le16 perfect_mac_used; 1143 __le16 perfect_mac_free; 1144 __le16 unicast_hash_free; 1145 __le16 multicast_hash_free; 1146 __le32 addr_high; 1147 __le32 addr_low; 1148 }; 1149 1150 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1151 1152 /* Remove MAC-VLAN (indirect 0x0251) 1153 * uses i40e_aqc_macvlan for the descriptor 1154 * data points to an array of num_addresses of elements 1155 */ 1156 1157 struct i40e_aqc_remove_macvlan_element_data { 1158 u8 mac_addr[6]; 1159 __le16 vlan_tag; 1160 u8 flags; 1161 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1162 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1163 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1164 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1165 u8 reserved[3]; 1166 /* reply section */ 1167 u8 error_code; 1168 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1169 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1170 u8 reply_reserved[3]; 1171 }; 1172 1173 /* Add VLAN (indirect 0x0252) 1174 * Remove VLAN (indirect 0x0253) 1175 * use the generic i40e_aqc_macvlan for the command 1176 */ 1177 struct i40e_aqc_add_remove_vlan_element_data { 1178 __le16 vlan_tag; 1179 u8 vlan_flags; 1180 /* flags for add VLAN */ 1181 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1182 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1183 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1184 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1185 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1186 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1187 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1188 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1189 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1190 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1191 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1192 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1193 /* flags for remove VLAN */ 1194 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1195 u8 reserved; 1196 u8 result; 1197 /* flags for add VLAN */ 1198 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1199 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1200 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1201 /* flags for remove VLAN */ 1202 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1203 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1204 u8 reserved1[3]; 1205 }; 1206 1207 struct i40e_aqc_add_remove_vlan_completion { 1208 u8 reserved[4]; 1209 __le16 vlans_used; 1210 __le16 vlans_free; 1211 __le32 addr_high; 1212 __le32 addr_low; 1213 }; 1214 1215 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1216 struct i40e_aqc_set_vsi_promiscuous_modes { 1217 __le16 promiscuous_flags; 1218 __le16 valid_flags; 1219 /* flags used for both fields above */ 1220 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1221 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1222 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1223 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1224 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1225 #define I40E_AQC_SET_VSI_PROMISC_RX_ONLY 0x8000 1226 __le16 seid; 1227 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1228 __le16 vlan_tag; 1229 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1230 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1231 u8 reserved[8]; 1232 }; 1233 1234 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1235 1236 /* Add S/E-tag command (direct 0x0255) 1237 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1238 */ 1239 struct i40e_aqc_add_tag { 1240 __le16 flags; 1241 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1242 __le16 seid; 1243 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1244 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1245 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1246 __le16 tag; 1247 __le16 queue_number; 1248 u8 reserved[8]; 1249 }; 1250 1251 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1252 1253 struct i40e_aqc_add_remove_tag_completion { 1254 u8 reserved[12]; 1255 __le16 tags_used; 1256 __le16 tags_free; 1257 }; 1258 1259 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1260 1261 /* Remove S/E-tag command (direct 0x0256) 1262 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1263 */ 1264 struct i40e_aqc_remove_tag { 1265 __le16 seid; 1266 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1267 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1268 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1269 __le16 tag; 1270 u8 reserved[12]; 1271 }; 1272 1273 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1274 1275 /* Add multicast E-Tag (direct 0x0257) 1276 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1277 * and no external data 1278 */ 1279 struct i40e_aqc_add_remove_mcast_etag { 1280 __le16 pv_seid; 1281 __le16 etag; 1282 u8 num_unicast_etags; 1283 u8 reserved[3]; 1284 __le32 addr_high; /* address of array of 2-byte s-tags */ 1285 __le32 addr_low; 1286 }; 1287 1288 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1289 1290 struct i40e_aqc_add_remove_mcast_etag_completion { 1291 u8 reserved[4]; 1292 __le16 mcast_etags_used; 1293 __le16 mcast_etags_free; 1294 __le32 addr_high; 1295 __le32 addr_low; 1296 1297 }; 1298 1299 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1300 1301 /* Update S/E-Tag (direct 0x0259) */ 1302 struct i40e_aqc_update_tag { 1303 __le16 seid; 1304 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1305 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1306 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1307 __le16 old_tag; 1308 __le16 new_tag; 1309 u8 reserved[10]; 1310 }; 1311 1312 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1313 1314 struct i40e_aqc_update_tag_completion { 1315 u8 reserved[12]; 1316 __le16 tags_used; 1317 __le16 tags_free; 1318 }; 1319 1320 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1321 1322 /* Add Control Packet filter (direct 0x025A) 1323 * Remove Control Packet filter (direct 0x025B) 1324 * uses the i40e_aqc_add_oveb_cloud, 1325 * and the generic direct completion structure 1326 */ 1327 struct i40e_aqc_add_remove_control_packet_filter { 1328 u8 mac[6]; 1329 __le16 etype; 1330 __le16 flags; 1331 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1332 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1333 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1334 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1335 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1336 __le16 seid; 1337 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1338 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1339 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1340 __le16 queue; 1341 u8 reserved[2]; 1342 }; 1343 1344 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1345 1346 struct i40e_aqc_add_remove_control_packet_filter_completion { 1347 __le16 mac_etype_used; 1348 __le16 etype_used; 1349 __le16 mac_etype_free; 1350 __le16 etype_free; 1351 u8 reserved[8]; 1352 }; 1353 1354 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1355 1356 /* Add Cloud filters (indirect 0x025C) 1357 * Remove Cloud filters (indirect 0x025D) 1358 * uses the i40e_aqc_add_remove_cloud_filters, 1359 * and the generic indirect completion structure 1360 */ 1361 struct i40e_aqc_add_remove_cloud_filters { 1362 u8 num_filters; 1363 u8 reserved; 1364 __le16 seid; 1365 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1366 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1367 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1368 u8 big_buffer_flag; 1369 #define I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1 1370 #define I40E_AQC_ADD_CLOUD_CMD_BB 1 1371 u8 reserved2[3]; 1372 __le32 addr_high; 1373 __le32 addr_low; 1374 }; 1375 1376 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1377 1378 struct i40e_aqc_cloud_filters_element_data { 1379 u8 outer_mac[6]; 1380 u8 inner_mac[6]; 1381 __le16 inner_vlan; 1382 union { 1383 struct { 1384 u8 reserved[12]; 1385 u8 data[4]; 1386 } v4; 1387 struct { 1388 u8 data[16]; 1389 } v6; 1390 struct { 1391 __le16 data[8]; 1392 } raw_v6; 1393 } ipaddr; 1394 __le16 flags; 1395 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1396 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1397 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1398 /* 0x0000 reserved */ 1399 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1400 /* 0x0002 reserved */ 1401 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1402 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1403 /* 0x0005 reserved */ 1404 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1405 /* 0x0007 reserved */ 1406 /* 0x0008 reserved */ 1407 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1408 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1409 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1410 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1411 #define I40E_AQC_ADD_CLOUD_FILTER_OIP1 0x0010 1412 #define I40E_AQC_ADD_CLOUD_FILTER_OIP2 0x0012 1413 /* 0x000D reserved */ 1414 /* 0x000E reserved */ 1415 /* 0x000F reserved */ 1416 /* 0x0010 to 0x0017 is for custom filters */ 1417 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */ 1418 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ 1419 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ 1420 1421 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1422 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1423 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1424 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1425 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1426 1427 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1428 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1429 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1430 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1431 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1432 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1433 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1434 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1435 1436 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1437 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1438 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1439 1440 __le32 tenant_id; 1441 u8 reserved[4]; 1442 __le16 queue_number; 1443 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1444 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1445 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1446 u8 reserved2[14]; 1447 /* response section */ 1448 u8 allocation_result; 1449 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1450 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1451 u8 response_reserved[7]; 1452 }; 1453 1454 /* i40e_aqc_add_rm_cloud_filt_elem_ext is used when 1455 * I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set. 1456 */ 1457 struct i40e_aqc_add_rm_cloud_filt_elem_ext { 1458 struct i40e_aqc_cloud_filters_element_data element; 1459 u16 general_fields[32]; 1460 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1461 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1462 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1463 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1464 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1465 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1466 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1467 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1468 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1469 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1470 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1471 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1472 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1473 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1474 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1475 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1476 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1477 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1478 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1479 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1480 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1481 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1482 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1483 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1484 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1485 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1486 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1487 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1488 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1489 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1490 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1491 }; 1492 1493 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data); 1494 1495 /* i40e_aqc_cloud_filters_element_bb is used when 1496 * I40E_AQC_CLOUD_CMD_BB flag is set. 1497 */ 1498 struct i40e_aqc_cloud_filters_element_bb { 1499 struct i40e_aqc_cloud_filters_element_data element; 1500 u16 general_fields[32]; 1501 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1502 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1503 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1504 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1505 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1506 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1507 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1508 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1509 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1510 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1511 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1512 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1513 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1514 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1515 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1516 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1517 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1518 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1519 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1520 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1521 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1522 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1523 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1524 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1525 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1526 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1527 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1528 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1529 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1530 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1531 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1532 }; 1533 1534 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); 1535 1536 struct i40e_aqc_remove_cloud_filters_completion { 1537 __le16 perfect_ovlan_used; 1538 __le16 perfect_ovlan_free; 1539 __le16 vlan_used; 1540 __le16 vlan_free; 1541 __le32 addr_high; 1542 __le32 addr_low; 1543 }; 1544 1545 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1546 1547 /* Replace filter Command 0x025F 1548 * uses the i40e_aqc_replace_cloud_filters, 1549 * and the generic indirect completion structure 1550 */ 1551 struct i40e_filter_data { 1552 u8 filter_type; 1553 u8 input[3]; 1554 }; 1555 1556 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data); 1557 1558 struct i40e_aqc_replace_cloud_filters_cmd { 1559 u8 valid_flags; 1560 #define I40E_AQC_REPLACE_L1_FILTER 0x0 1561 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 1562 #define I40E_AQC_GET_CLOUD_FILTERS 0x2 1563 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 1564 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 1565 u8 old_filter_type; 1566 u8 new_filter_type; 1567 u8 tr_bit; 1568 u8 tr_bit2; 1569 u8 reserved[3]; 1570 __le32 addr_high; 1571 __le32 addr_low; 1572 }; 1573 1574 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd); 1575 1576 struct i40e_aqc_replace_cloud_filters_cmd_buf { 1577 u8 data[32]; 1578 /* Filter type INPUT codes*/ 1579 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 1580 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL) 1581 1582 /* Field Vector offsets */ 1583 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 1584 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 1585 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 1586 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 1587 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 1588 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 1589 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 1590 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 1591 /* big FLU */ 1592 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 1593 /* big FLU */ 1594 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 1595 1596 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 1597 struct i40e_filter_data filters[8]; 1598 }; 1599 1600 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf); 1601 1602 /* Add Mirror Rule (indirect or direct 0x0260) 1603 * Delete Mirror Rule (indirect or direct 0x0261) 1604 * note: some rule types (4,5) do not use an external buffer. 1605 * take care to set the flags correctly. 1606 */ 1607 struct i40e_aqc_add_delete_mirror_rule { 1608 __le16 seid; 1609 __le16 rule_type; 1610 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1611 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1612 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1613 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1614 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1615 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1616 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1617 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1618 __le16 num_entries; 1619 __le16 destination; /* VSI for add, rule id for delete */ 1620 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1621 __le32 addr_low; 1622 }; 1623 1624 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1625 1626 struct i40e_aqc_add_delete_mirror_rule_completion { 1627 u8 reserved[2]; 1628 __le16 rule_id; /* only used on add */ 1629 __le16 mirror_rules_used; 1630 __le16 mirror_rules_free; 1631 __le32 addr_high; 1632 __le32 addr_low; 1633 }; 1634 1635 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1636 1637 /* Dynamic Device Personalization */ 1638 struct i40e_aqc_write_personalization_profile { 1639 u8 flags; 1640 u8 reserved[3]; 1641 __le32 profile_track_id; 1642 __le32 addr_high; 1643 __le32 addr_low; 1644 }; 1645 1646 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile); 1647 1648 struct i40e_aqc_write_ddp_resp { 1649 __le32 error_offset; 1650 __le32 error_info; 1651 __le32 addr_high; 1652 __le32 addr_low; 1653 }; 1654 1655 struct i40e_aqc_get_applied_profiles { 1656 u8 flags; 1657 #define I40E_AQC_GET_DDP_GET_CONF 0x1 1658 #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2 1659 u8 rsv[3]; 1660 __le32 reserved; 1661 __le32 addr_high; 1662 __le32 addr_low; 1663 }; 1664 1665 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles); 1666 1667 /* DCB 0x03xx*/ 1668 1669 /* PFC Ignore (direct 0x0301) 1670 * the command and response use the same descriptor structure 1671 */ 1672 struct i40e_aqc_pfc_ignore { 1673 u8 tc_bitmap; 1674 u8 command_flags; /* unused on response */ 1675 #define I40E_AQC_PFC_IGNORE_SET 0x80 1676 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1677 u8 reserved[14]; 1678 }; 1679 1680 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1681 1682 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1683 * with no parameters 1684 */ 1685 1686 /* TX scheduler 0x04xx */ 1687 1688 /* Almost all the indirect commands use 1689 * this generic struct to pass the SEID in param0 1690 */ 1691 struct i40e_aqc_tx_sched_ind { 1692 __le16 vsi_seid; 1693 u8 reserved[6]; 1694 __le32 addr_high; 1695 __le32 addr_low; 1696 }; 1697 1698 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1699 1700 /* Several commands respond with a set of queue set handles */ 1701 struct i40e_aqc_qs_handles_resp { 1702 __le16 qs_handles[8]; 1703 }; 1704 1705 /* Configure VSI BW limits (direct 0x0400) */ 1706 struct i40e_aqc_configure_vsi_bw_limit { 1707 __le16 vsi_seid; 1708 u8 reserved[2]; 1709 __le16 credit; 1710 u8 reserved1[2]; 1711 u8 max_credit; /* 0-3, limit = 2^max */ 1712 u8 reserved2[7]; 1713 }; 1714 1715 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1716 1717 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1718 * responds with i40e_aqc_qs_handles_resp 1719 */ 1720 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1721 u8 tc_valid_bits; 1722 u8 reserved[15]; 1723 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1724 1725 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1726 __le16 tc_bw_max[2]; 1727 u8 reserved1[28]; 1728 }; 1729 1730 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1731 1732 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1733 * responds with i40e_aqc_qs_handles_resp 1734 */ 1735 struct i40e_aqc_configure_vsi_tc_bw_data { 1736 u8 tc_valid_bits; 1737 u8 reserved[3]; 1738 u8 tc_bw_credits[8]; 1739 u8 reserved1[4]; 1740 __le16 qs_handles[8]; 1741 }; 1742 1743 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1744 1745 /* Query vsi bw configuration (indirect 0x0408) */ 1746 struct i40e_aqc_query_vsi_bw_config_resp { 1747 u8 tc_valid_bits; 1748 u8 tc_suspended_bits; 1749 u8 reserved[14]; 1750 __le16 qs_handles[8]; 1751 u8 reserved1[4]; 1752 __le16 port_bw_limit; 1753 u8 reserved2[2]; 1754 u8 max_bw; /* 0-3, limit = 2^max */ 1755 u8 reserved3[23]; 1756 }; 1757 1758 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1759 1760 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1761 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1762 u8 tc_valid_bits; 1763 u8 reserved[3]; 1764 u8 share_credits[8]; 1765 __le16 credits[8]; 1766 1767 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1768 __le16 tc_bw_max[2]; 1769 }; 1770 1771 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1772 1773 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1774 struct i40e_aqc_configure_switching_comp_bw_limit { 1775 __le16 seid; 1776 u8 reserved[2]; 1777 __le16 credit; 1778 u8 reserved1[2]; 1779 u8 max_bw; /* 0-3, limit = 2^max */ 1780 u8 reserved2[7]; 1781 }; 1782 1783 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1784 1785 /* Enable Physical Port ETS (indirect 0x0413) 1786 * Modify Physical Port ETS (indirect 0x0414) 1787 * Disable Physical Port ETS (indirect 0x0415) 1788 */ 1789 struct i40e_aqc_configure_switching_comp_ets_data { 1790 u8 reserved[4]; 1791 u8 tc_valid_bits; 1792 u8 seepage; 1793 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1794 u8 tc_strict_priority_flags; 1795 u8 reserved1[17]; 1796 u8 tc_bw_share_credits[8]; 1797 u8 reserved2[96]; 1798 }; 1799 1800 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1801 1802 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1803 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1804 u8 tc_valid_bits; 1805 u8 reserved[15]; 1806 __le16 tc_bw_credit[8]; 1807 1808 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1809 __le16 tc_bw_max[2]; 1810 u8 reserved1[28]; 1811 }; 1812 1813 I40E_CHECK_STRUCT_LEN(0x40, 1814 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1815 1816 /* Configure Switching Component Bandwidth Allocation per Tc 1817 * (indirect 0x0417) 1818 */ 1819 struct i40e_aqc_configure_switching_comp_bw_config_data { 1820 u8 tc_valid_bits; 1821 u8 reserved[2]; 1822 u8 absolute_credits; /* bool */ 1823 u8 tc_bw_share_credits[8]; 1824 u8 reserved1[20]; 1825 }; 1826 1827 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1828 1829 /* Query Switching Component Configuration (indirect 0x0418) */ 1830 struct i40e_aqc_query_switching_comp_ets_config_resp { 1831 u8 tc_valid_bits; 1832 u8 reserved[35]; 1833 __le16 port_bw_limit; 1834 u8 reserved1[2]; 1835 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1836 u8 reserved2[23]; 1837 }; 1838 1839 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1840 1841 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1842 struct i40e_aqc_query_port_ets_config_resp { 1843 u8 reserved[4]; 1844 u8 tc_valid_bits; 1845 u8 reserved1; 1846 u8 tc_strict_priority_bits; 1847 u8 reserved2; 1848 u8 tc_bw_share_credits[8]; 1849 __le16 tc_bw_limits[8]; 1850 1851 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1852 __le16 tc_bw_max[2]; 1853 u8 reserved3[32]; 1854 }; 1855 1856 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1857 1858 /* Query Switching Component Bandwidth Allocation per Traffic Type 1859 * (indirect 0x041A) 1860 */ 1861 struct i40e_aqc_query_switching_comp_bw_config_resp { 1862 u8 tc_valid_bits; 1863 u8 reserved[2]; 1864 u8 absolute_credits_enable; /* bool */ 1865 u8 tc_bw_share_credits[8]; 1866 __le16 tc_bw_limits[8]; 1867 1868 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1869 __le16 tc_bw_max[2]; 1870 }; 1871 1872 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1873 1874 /* Suspend/resume port TX traffic 1875 * (direct 0x041B and 0x041C) uses the generic SEID struct 1876 */ 1877 1878 /* Configure partition BW 1879 * (indirect 0x041D) 1880 */ 1881 struct i40e_aqc_configure_partition_bw_data { 1882 __le16 pf_valid_bits; 1883 u8 min_bw[16]; /* guaranteed bandwidth */ 1884 u8 max_bw[16]; /* bandwidth limit */ 1885 }; 1886 1887 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1888 1889 /* Get and set the active HMC resource profile and status. 1890 * (direct 0x0500) and (direct 0x0501) 1891 */ 1892 struct i40e_aq_get_set_hmc_resource_profile { 1893 u8 pm_profile; 1894 u8 pe_vf_enabled; 1895 u8 reserved[14]; 1896 }; 1897 1898 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1899 1900 enum i40e_aq_hmc_profile { 1901 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1902 I40E_HMC_PROFILE_DEFAULT = 1, 1903 I40E_HMC_PROFILE_FAVOR_VF = 2, 1904 I40E_HMC_PROFILE_EQUAL = 3, 1905 }; 1906 1907 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1908 1909 /* set in param0 for get phy abilities to report qualified modules */ 1910 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1911 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1912 1913 enum i40e_aq_phy_type { 1914 I40E_PHY_TYPE_SGMII = 0x0, 1915 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1916 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1917 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1918 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1919 I40E_PHY_TYPE_XAUI = 0x5, 1920 I40E_PHY_TYPE_XFI = 0x6, 1921 I40E_PHY_TYPE_SFI = 0x7, 1922 I40E_PHY_TYPE_XLAUI = 0x8, 1923 I40E_PHY_TYPE_XLPPI = 0x9, 1924 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1925 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1926 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1927 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1928 I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1929 I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1930 I40E_PHY_TYPE_100BASE_TX = 0x11, 1931 I40E_PHY_TYPE_1000BASE_T = 0x12, 1932 I40E_PHY_TYPE_10GBASE_T = 0x13, 1933 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1934 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1935 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1936 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1937 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1938 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1939 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1940 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1941 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1942 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1943 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1944 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1945 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1946 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1947 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1948 I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1949 I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1950 I40E_PHY_TYPE_2_5GBASE_T = 0x30, 1951 I40E_PHY_TYPE_5GBASE_T = 0x31, 1952 I40E_PHY_TYPE_MAX, 1953 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 1954 I40E_PHY_TYPE_EMPTY = 0xFE, 1955 I40E_PHY_TYPE_DEFAULT = 0xFF, 1956 }; 1957 1958 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ 1959 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ 1960 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ 1961 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \ 1962 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \ 1963 BIT_ULL(I40E_PHY_TYPE_XAUI) | \ 1964 BIT_ULL(I40E_PHY_TYPE_XFI) | \ 1965 BIT_ULL(I40E_PHY_TYPE_SFI) | \ 1966 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \ 1967 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \ 1968 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \ 1969 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \ 1970 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \ 1971 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ 1972 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ 1973 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ 1974 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ 1975 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ 1976 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ 1977 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \ 1978 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \ 1979 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \ 1980 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \ 1981 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \ 1982 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \ 1983 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \ 1984 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \ 1985 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ 1986 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ 1987 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ 1988 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ 1989 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ 1990 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ 1991 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ 1992 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ 1993 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \ 1994 BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \ 1995 BIT_ULL(I40E_PHY_TYPE_5GBASE_T)) 1996 1997 #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0 1998 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1999 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 2000 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 2001 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 2002 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 2003 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 2004 #define I40E_LINK_SPEED_5GB_SHIFT 0x7 2005 2006 enum i40e_aq_link_speed { 2007 I40E_LINK_SPEED_UNKNOWN = 0, 2008 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 2009 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 2010 I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT), 2011 I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT), 2012 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 2013 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 2014 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), 2015 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), 2016 }; 2017 2018 struct i40e_aqc_module_desc { 2019 u8 oui[3]; 2020 u8 reserved1; 2021 u8 part_number[16]; 2022 u8 revision[4]; 2023 u8 reserved2[8]; 2024 }; 2025 2026 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 2027 2028 struct i40e_aq_get_phy_abilities_resp { 2029 __le32 phy_type; /* bitmap using the above enum for offsets */ 2030 u8 link_speed; /* bitmap using the above enum bit patterns */ 2031 u8 abilities; 2032 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 2033 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 2034 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 2035 #define I40E_AQ_PHY_LINK_ENABLED 0x08 2036 #define I40E_AQ_PHY_AN_ENABLED 0x10 2037 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 2038 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 2039 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 2040 __le16 eee_capability; 2041 #define I40E_AQ_EEE_AUTO 0x0001 2042 #define I40E_AQ_EEE_100BASE_TX 0x0002 2043 #define I40E_AQ_EEE_1000BASE_T 0x0004 2044 #define I40E_AQ_EEE_10GBASE_T 0x0008 2045 #define I40E_AQ_EEE_1000BASE_KX 0x0010 2046 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 2047 #define I40E_AQ_EEE_10GBASE_KR 0x0040 2048 #define I40E_AQ_EEE_2_5GBASE_T 0x0100 2049 #define I40E_AQ_EEE_5GBASE_T 0x0200 2050 __le32 eeer_val; 2051 u8 d3_lpan; 2052 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 2053 u8 phy_type_ext; 2054 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 2055 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 2056 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 2057 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 2058 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 2059 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 2060 #define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40 2061 #define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80 2062 u8 fec_cfg_curr_mod_ext_info; 2063 #define I40E_AQ_ENABLE_FEC_KR 0x01 2064 #define I40E_AQ_ENABLE_FEC_RS 0x02 2065 #define I40E_AQ_REQUEST_FEC_KR 0x04 2066 #define I40E_AQ_REQUEST_FEC_RS 0x08 2067 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 2068 #define I40E_AQ_FEC 2069 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 2070 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 2071 2072 u8 ext_comp_code; 2073 u8 phy_id[4]; 2074 u8 module_type[3]; 2075 u8 qualified_module_count; 2076 #define I40E_AQ_PHY_MAX_QMS 16 2077 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 2078 }; 2079 2080 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 2081 2082 /* Set PHY Config (direct 0x0601) */ 2083 struct i40e_aq_set_phy_config { /* same bits as above in all */ 2084 __le32 phy_type; 2085 u8 link_speed; 2086 u8 abilities; 2087 /* bits 0-2 use the values from get_phy_abilities_resp */ 2088 #define I40E_AQ_PHY_ENABLE_LINK 0x08 2089 #define I40E_AQ_PHY_ENABLE_AN 0x10 2090 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 2091 __le16 eee_capability; 2092 __le32 eeer; 2093 u8 low_power_ctrl; 2094 u8 phy_type_ext; 2095 u8 fec_config; 2096 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 2097 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 2098 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 2099 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 2100 #define I40E_AQ_SET_FEC_AUTO BIT(4) 2101 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 2102 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 2103 u8 reserved; 2104 }; 2105 2106 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 2107 2108 /* Set MAC Config command data structure (direct 0x0603) */ 2109 struct i40e_aq_set_mac_config { 2110 __le16 max_frame_size; 2111 u8 params; 2112 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 2113 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 2114 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 2115 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 2116 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 2117 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 2118 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 2119 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 2120 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 2121 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 2122 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 2123 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 2124 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 2125 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 2126 #define I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN 0x80 2127 u8 tx_timer_priority; /* bitmap */ 2128 __le16 tx_timer_value; 2129 __le16 fc_refresh_threshold; 2130 u8 reserved[8]; 2131 }; 2132 2133 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 2134 2135 /* Restart Auto-Negotiation (direct 0x605) */ 2136 struct i40e_aqc_set_link_restart_an { 2137 u8 command; 2138 #define I40E_AQ_PHY_RESTART_AN 0x02 2139 #define I40E_AQ_PHY_LINK_ENABLE 0x04 2140 u8 reserved[15]; 2141 }; 2142 2143 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 2144 2145 /* Get Link Status cmd & response data structure (direct 0x0607) */ 2146 struct i40e_aqc_get_link_status { 2147 __le16 command_flags; /* only field set on command */ 2148 #define I40E_AQ_LSE_MASK 0x3 2149 #define I40E_AQ_LSE_NOP 0x0 2150 #define I40E_AQ_LSE_DISABLE 0x2 2151 #define I40E_AQ_LSE_ENABLE 0x3 2152 /* only response uses this flag */ 2153 #define I40E_AQ_LSE_IS_ENABLED 0x1 2154 u8 phy_type; /* i40e_aq_phy_type */ 2155 u8 link_speed; /* i40e_aq_link_speed */ 2156 u8 link_info; 2157 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 2158 #define I40E_AQ_LINK_UP_FUNCTION 0x01 2159 #define I40E_AQ_LINK_FAULT 0x02 2160 #define I40E_AQ_LINK_FAULT_TX 0x04 2161 #define I40E_AQ_LINK_FAULT_RX 0x08 2162 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 2163 #define I40E_AQ_LINK_UP_PORT 0x20 2164 #define I40E_AQ_MEDIA_AVAILABLE 0x40 2165 #define I40E_AQ_SIGNAL_DETECT 0x80 2166 u8 an_info; 2167 #define I40E_AQ_AN_COMPLETED 0x01 2168 #define I40E_AQ_LP_AN_ABILITY 0x02 2169 #define I40E_AQ_PD_FAULT 0x04 2170 #define I40E_AQ_FEC_EN 0x08 2171 #define I40E_AQ_PHY_LOW_POWER 0x10 2172 #define I40E_AQ_LINK_PAUSE_TX 0x20 2173 #define I40E_AQ_LINK_PAUSE_RX 0x40 2174 #define I40E_AQ_QUALIFIED_MODULE 0x80 2175 u8 ext_info; 2176 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 2177 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 2178 #define I40E_AQ_LINK_TX_SHIFT 0x02 2179 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 2180 #define I40E_AQ_LINK_TX_ACTIVE 0x00 2181 #define I40E_AQ_LINK_TX_DRAINED 0x01 2182 #define I40E_AQ_LINK_TX_FLUSHED 0x03 2183 #define I40E_AQ_LINK_FORCED_40G 0x10 2184 /* 25G Error Codes */ 2185 #define I40E_AQ_25G_NO_ERR 0X00 2186 #define I40E_AQ_25G_NOT_PRESENT 0X01 2187 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 2188 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 2189 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 2190 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 2191 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 2192 /* Since firmware API 1.7 loopback field keeps power class info as well */ 2193 #define I40E_AQ_LOOPBACK_MASK 0x07 2194 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6 2195 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 2196 __le16 max_frame_size; 2197 u8 config; 2198 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 2199 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 2200 #define I40E_AQ_CONFIG_CRC_ENA 0x04 2201 #define I40E_AQ_CONFIG_PACING_MASK 0x78 2202 union { 2203 struct { 2204 u8 power_desc; 2205 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 2206 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 2207 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 2208 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 2209 #define I40E_AQ_PWR_CLASS_MASK 0x03 2210 u8 reserved[4]; 2211 }; 2212 struct { 2213 u8 link_type[4]; 2214 u8 link_type_ext; 2215 }; 2216 }; 2217 }; 2218 2219 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 2220 2221 /* Set event mask command (direct 0x613) */ 2222 struct i40e_aqc_set_phy_int_mask { 2223 u8 reserved[8]; 2224 __le16 event_mask; 2225 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2226 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 2227 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 2228 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2229 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2230 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2231 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2232 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2233 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2234 u8 reserved1[6]; 2235 }; 2236 2237 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2238 2239 /* Get Local AN advt register (direct 0x0614) 2240 * Set Local AN advt register (direct 0x0615) 2241 * Get Link Partner AN advt register (direct 0x0616) 2242 */ 2243 struct i40e_aqc_an_advt_reg { 2244 __le32 local_an_reg0; 2245 __le16 local_an_reg1; 2246 u8 reserved[10]; 2247 }; 2248 2249 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2250 2251 /* Set Loopback mode (0x0618) */ 2252 struct i40e_aqc_set_lb_mode { 2253 __le16 lb_mode; 2254 #define I40E_AQ_LB_PHY_LOCAL 0x01 2255 #define I40E_AQ_LB_PHY_REMOTE 0x02 2256 #define I40E_AQ_LB_MAC_LOCAL 0x04 2257 u8 reserved[14]; 2258 }; 2259 2260 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2261 2262 /* Set PHY Debug command (0x0622) */ 2263 struct i40e_aqc_set_phy_debug { 2264 u8 command_flags; 2265 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2266 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2267 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2268 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2269 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2270 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2271 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2272 /* Disable link manageability on a single port */ 2273 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2274 /* Disable link manageability on all ports needs both bits 4 and 5 */ 2275 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2276 u8 reserved[15]; 2277 }; 2278 2279 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2280 2281 enum i40e_aq_phy_reg_type { 2282 I40E_AQC_PHY_REG_INTERNAL = 0x1, 2283 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2284 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2285 }; 2286 2287 #pragma pack(1) 2288 /* Run PHY Activity (0x0626) */ 2289 struct i40e_aqc_run_phy_activity { 2290 u8 cmd_flags; 2291 __le16 activity_id; 2292 #define I40E_AQ_RUN_PHY_ACT_ID_USR_DFND 0x10 2293 u8 reserved; 2294 union { 2295 struct { 2296 __le32 dnl_opcode; 2297 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR 0x801a 2298 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT 0x801b 2299 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR 0x1801b 2300 __le32 data; 2301 u8 reserved2[4]; 2302 } cmd; 2303 struct { 2304 __le32 cmd_status; 2305 #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC 0x4 2306 #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK 0xFFFF 2307 __le32 data0; 2308 __le32 data1; 2309 } resp; 2310 } params; 2311 }; 2312 #pragma pack() 2313 2314 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2315 2316 /* Set PHY Register command (0x0628) */ 2317 /* Get PHY Register command (0x0629) */ 2318 struct i40e_aqc_phy_register_access { 2319 u8 phy_interface; 2320 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2321 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2322 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2323 u8 dev_addres; 2324 u8 cmd_flags; 2325 #define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 0x01 2326 #define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER 0x02 2327 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT 2 2328 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK (0x3 << \ 2329 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) 2330 u8 reserved1; 2331 __le32 reg_address; 2332 __le32 reg_value; 2333 u8 reserved2[4]; 2334 }; 2335 2336 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2337 2338 /* NVM Read command (indirect 0x0701) 2339 * NVM Erase commands (direct 0x0702) 2340 * NVM Update commands (indirect 0x0703) 2341 */ 2342 struct i40e_aqc_nvm_update { 2343 u8 command_flags; 2344 #define I40E_AQ_NVM_LAST_CMD 0x01 2345 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20 2346 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40 2347 #define I40E_AQ_NVM_FLASH_ONLY 0x80 2348 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 2349 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 2350 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 2351 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 2352 u8 module_pointer; 2353 __le16 length; 2354 __le32 offset; 2355 __le32 addr_high; 2356 __le32 addr_low; 2357 }; 2358 2359 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2360 2361 /* NVM Config Read (indirect 0x0704) */ 2362 struct i40e_aqc_nvm_config_read { 2363 __le16 cmd_flags; 2364 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2365 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2366 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2367 __le16 element_count; 2368 __le16 element_id; /* Feature/field ID */ 2369 __le16 element_id_msw; /* MSWord of field ID */ 2370 __le32 address_high; 2371 __le32 address_low; 2372 }; 2373 2374 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2375 2376 /* NVM Config Write (indirect 0x0705) */ 2377 struct i40e_aqc_nvm_config_write { 2378 __le16 cmd_flags; 2379 __le16 element_count; 2380 u8 reserved[4]; 2381 __le32 address_high; 2382 __le32 address_low; 2383 }; 2384 2385 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2386 2387 /* Used for 0x0704 as well as for 0x0705 commands */ 2388 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2389 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2390 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2391 #define I40E_AQ_ANVM_FEATURE 0 2392 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 2393 struct i40e_aqc_nvm_config_data_feature { 2394 __le16 feature_id; 2395 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2396 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2397 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2398 __le16 feature_options; 2399 __le16 feature_selection; 2400 }; 2401 2402 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2403 2404 /* NVM Update in Process (direct 0x0706) */ 2405 struct i40e_aqc_nvm_update_in_process { 2406 u8 command; 2407 #define I40E_AQ_UPDATE_FLOW_END 0x0 2408 #define I40E_AQ_UPDATE_FLOW_START 0x1 2409 u8 reserved[15]; 2410 }; 2411 2412 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update_in_process); 2413 2414 struct i40e_aqc_nvm_config_data_immediate_field { 2415 __le32 field_id; 2416 __le32 field_value; 2417 __le16 field_options; 2418 __le16 reserved; 2419 }; 2420 2421 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2422 2423 /* Minimal Rollback Revision Update (direct 0x0707) */ 2424 struct i40e_aqc_rollback_revision_update { 2425 u8 optin_mode; /* bool */ 2426 #define I40E_AQ_RREV_OPTION_MODE 0x01 2427 u8 module_selected; 2428 #define I40E_AQ_RREV_MODULE_PCIE_ANALOG 0 2429 #define I40E_AQ_RREV_MODULE_PHY_ANALOG 1 2430 #define I40E_AQ_RREV_MODULE_OPTION_ROM 2 2431 #define I40E_AQ_RREV_MODULE_EMP_IMAGE 3 2432 #define I40E_AQ_RREV_MODULE_PE_IMAGE 4 2433 u8 reserved1[2]; 2434 u32 min_rrev; 2435 u8 reserved2[8]; 2436 }; 2437 2438 I40E_CHECK_CMD_LENGTH(i40e_aqc_rollback_revision_update); 2439 2440 /* OEM Post Update (indirect 0x0720) 2441 * no command data struct used 2442 */ 2443 struct i40e_aqc_nvm_oem_post_update { 2444 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2445 u8 sel_data; 2446 u8 reserved[7]; 2447 }; 2448 2449 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2450 2451 struct i40e_aqc_nvm_oem_post_update_buffer { 2452 u8 str_len; 2453 u8 dev_addr; 2454 __le16 eeprom_addr; 2455 u8 data[36]; 2456 }; 2457 2458 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2459 2460 /* Thermal Sensor (indirect 0x0721) 2461 * read or set thermal sensor configs and values 2462 * takes a sensor and command specific data buffer, not detailed here 2463 */ 2464 struct i40e_aqc_thermal_sensor { 2465 u8 sensor_action; 2466 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2467 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2468 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2469 u8 reserved[7]; 2470 __le32 addr_high; 2471 __le32 addr_low; 2472 }; 2473 2474 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2475 2476 /* Send to PF command (indirect 0x0801) id is only used by PF 2477 * Send to VF command (indirect 0x0802) id is only used by PF 2478 * Send to Peer PF command (indirect 0x0803) 2479 */ 2480 struct i40e_aqc_pf_vf_message { 2481 __le32 id; 2482 u8 reserved[4]; 2483 __le32 addr_high; 2484 __le32 addr_low; 2485 }; 2486 2487 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2488 2489 /* Alternate structure */ 2490 2491 /* Direct write (direct 0x0900) 2492 * Direct read (direct 0x0902) 2493 */ 2494 struct i40e_aqc_alternate_write { 2495 __le32 address0; 2496 __le32 data0; 2497 __le32 address1; 2498 __le32 data1; 2499 }; 2500 2501 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2502 2503 /* Indirect write (indirect 0x0901) 2504 * Indirect read (indirect 0x0903) 2505 */ 2506 2507 struct i40e_aqc_alternate_ind_write { 2508 __le32 address; 2509 __le32 length; 2510 __le32 addr_high; 2511 __le32 addr_low; 2512 }; 2513 2514 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2515 2516 /* Done alternate write (direct 0x0904) 2517 * uses i40e_aq_desc 2518 */ 2519 struct i40e_aqc_alternate_write_done { 2520 __le16 cmd_flags; 2521 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2522 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2523 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2524 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2525 u8 reserved[14]; 2526 }; 2527 2528 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2529 2530 /* Set OEM mode (direct 0x0905) */ 2531 struct i40e_aqc_alternate_set_mode { 2532 __le32 mode; 2533 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2534 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2535 u8 reserved[12]; 2536 }; 2537 2538 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2539 2540 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2541 2542 /* async events 0x10xx */ 2543 2544 /* Lan Queue Overflow Event (direct, 0x1001) */ 2545 struct i40e_aqc_lan_overflow { 2546 __le32 prtdcb_rupto; 2547 __le32 otx_ctl; 2548 u8 reserved[8]; 2549 }; 2550 2551 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2552 2553 /* Get LLDP MIB (indirect 0x0A00) */ 2554 struct i40e_aqc_lldp_get_mib { 2555 u8 type; 2556 u8 reserved1; 2557 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2558 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2559 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2560 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2561 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2562 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2563 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2564 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2565 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2566 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2567 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2568 __le16 local_len; 2569 __le16 remote_len; 2570 u8 reserved2[2]; 2571 __le32 addr_high; 2572 __le32 addr_low; 2573 }; 2574 2575 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2576 2577 /* Configure LLDP MIB Change Event (direct 0x0A01) 2578 * also used for the event (with type in the command field) 2579 */ 2580 struct i40e_aqc_lldp_update_mib { 2581 u8 command; 2582 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2583 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2584 u8 reserved[7]; 2585 __le32 addr_high; 2586 __le32 addr_low; 2587 }; 2588 2589 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2590 2591 /* Add LLDP TLV (indirect 0x0A02) 2592 * Delete LLDP TLV (indirect 0x0A04) 2593 */ 2594 struct i40e_aqc_lldp_add_tlv { 2595 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2596 u8 reserved1[1]; 2597 __le16 len; 2598 u8 reserved2[4]; 2599 __le32 addr_high; 2600 __le32 addr_low; 2601 }; 2602 2603 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2604 2605 /* Update LLDP TLV (indirect 0x0A03) */ 2606 struct i40e_aqc_lldp_update_tlv { 2607 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2608 u8 reserved; 2609 __le16 old_len; 2610 __le16 new_offset; 2611 __le16 new_len; 2612 __le32 addr_high; 2613 __le32 addr_low; 2614 }; 2615 2616 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2617 2618 /* Stop LLDP (direct 0x0A05) */ 2619 struct i40e_aqc_lldp_stop { 2620 u8 command; 2621 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2622 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2623 #define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2 2624 u8 reserved[15]; 2625 }; 2626 2627 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2628 2629 /* Start LLDP (direct 0x0A06) */ 2630 2631 struct i40e_aqc_lldp_start { 2632 u8 command; 2633 #define I40E_AQ_LLDP_AGENT_START 0x1 2634 #define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2 2635 u8 reserved[15]; 2636 }; 2637 2638 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2639 2640 /* Set DCB (direct 0x0303) */ 2641 struct i40e_aqc_set_dcb_parameters { 2642 u8 command; 2643 #define I40E_AQ_DCB_SET_AGENT 0x1 2644 #define I40E_DCB_VALID 0x1 2645 u8 valid_flags; 2646 u8 reserved[14]; 2647 }; 2648 2649 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); 2650 2651 /* Get CEE DCBX Oper Config (0x0A07) 2652 * uses the generic descriptor struct 2653 * returns below as indirect response 2654 */ 2655 2656 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2657 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2658 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2659 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2660 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2661 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2662 2663 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2664 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2665 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2666 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2667 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2668 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2669 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2670 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2671 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2672 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2673 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2674 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2675 2676 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2677 * word boundary layout issues, which the Linux compilers silently deal 2678 * with by adding padding, making the actual struct larger than designed. 2679 * However, the FW compiler for the NIC is less lenient and complains 2680 * about the struct. Hence, the struct defined here has an extra byte in 2681 * fields reserved3 and reserved4 to directly acknowledge that padding, 2682 * and the new length is used in the length check macro. 2683 */ 2684 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2685 u8 reserved1; 2686 u8 oper_num_tc; 2687 u8 oper_prio_tc[4]; 2688 u8 reserved2; 2689 u8 oper_tc_bw[8]; 2690 u8 oper_pfc_en; 2691 u8 reserved3[2]; 2692 __le16 oper_app_prio; 2693 u8 reserved4[2]; 2694 __le16 tlv_status; 2695 }; 2696 2697 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2698 2699 struct i40e_aqc_get_cee_dcb_cfg_resp { 2700 u8 oper_num_tc; 2701 u8 oper_prio_tc[4]; 2702 u8 oper_tc_bw[8]; 2703 u8 oper_pfc_en; 2704 __le16 oper_app_prio; 2705 __le32 tlv_status; 2706 u8 reserved[12]; 2707 }; 2708 2709 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2710 2711 /* Set Local LLDP MIB (indirect 0x0A08) 2712 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2713 */ 2714 struct i40e_aqc_lldp_set_local_mib { 2715 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2716 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2717 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2718 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2719 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2720 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2721 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2722 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2723 u8 type; 2724 u8 reserved0; 2725 __le16 length; 2726 u8 reserved1[4]; 2727 __le32 address_high; 2728 __le32 address_low; 2729 }; 2730 2731 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2732 2733 struct i40e_aqc_lldp_set_local_mib_resp { 2734 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2735 u8 status; 2736 u8 reserved[15]; 2737 }; 2738 2739 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2740 2741 /* Stop/Start LLDP Agent (direct 0x0A09) 2742 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2743 */ 2744 struct i40e_aqc_lldp_stop_start_specific_agent { 2745 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2746 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2747 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2748 u8 command; 2749 u8 reserved[15]; 2750 }; 2751 2752 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2753 2754 /* Restore LLDP Agent factory settings (direct 0x0A0A) */ 2755 struct i40e_aqc_lldp_restore { 2756 u8 command; 2757 #define I40E_AQ_LLDP_AGENT_RESTORE_NOT 0x0 2758 #define I40E_AQ_LLDP_AGENT_RESTORE 0x1 2759 u8 reserved[15]; 2760 }; 2761 2762 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore); 2763 2764 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2765 struct i40e_aqc_add_udp_tunnel { 2766 __le16 udp_port; 2767 u8 reserved0[3]; 2768 u8 protocol_type; 2769 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2770 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2771 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2772 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2773 u8 reserved1[10]; 2774 }; 2775 2776 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2777 2778 struct i40e_aqc_add_udp_tunnel_completion { 2779 __le16 udp_port; 2780 u8 filter_entry_index; 2781 u8 multiple_pfs; 2782 #define I40E_AQC_SINGLE_PF 0x0 2783 #define I40E_AQC_MULTIPLE_PFS 0x1 2784 u8 total_filters; 2785 u8 reserved[11]; 2786 }; 2787 2788 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2789 2790 /* remove UDP Tunnel command (0x0B01) */ 2791 struct i40e_aqc_remove_udp_tunnel { 2792 u8 reserved[2]; 2793 u8 index; /* 0 to 15 */ 2794 u8 reserved2[13]; 2795 }; 2796 2797 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2798 2799 struct i40e_aqc_del_udp_tunnel_completion { 2800 __le16 udp_port; 2801 u8 index; /* 0 to 15 */ 2802 u8 multiple_pfs; 2803 u8 total_filters_used; 2804 u8 reserved1[11]; 2805 }; 2806 2807 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2808 2809 struct i40e_aqc_get_set_rss_key { 2810 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2811 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2812 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2813 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2814 __le16 vsi_id; 2815 u8 reserved[6]; 2816 __le32 addr_high; 2817 __le32 addr_low; 2818 }; 2819 2820 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2821 2822 struct i40e_aqc_get_set_rss_key_data { 2823 u8 standard_rss_key[0x28]; 2824 u8 extended_hash_key[0xc]; 2825 }; 2826 2827 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2828 2829 struct i40e_aqc_get_set_rss_lut { 2830 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2831 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2832 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2833 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2834 __le16 vsi_id; 2835 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2836 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2837 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2838 2839 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2840 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2841 __le16 flags; 2842 u8 reserved[4]; 2843 __le32 addr_high; 2844 __le32 addr_low; 2845 }; 2846 2847 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2848 2849 /* tunnel key structure 0x0B10 */ 2850 2851 struct i40e_aqc_tunnel_key_structure { 2852 u8 key1_off; 2853 u8 key2_off; 2854 u8 key1_len; /* 0 to 15 */ 2855 u8 key2_len; /* 0 to 15 */ 2856 u8 flags; 2857 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2858 /* response flags */ 2859 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2860 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2861 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2862 u8 network_key_index; 2863 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2864 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2865 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2866 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2867 u8 reserved[10]; 2868 }; 2869 2870 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2871 2872 /* OEM mode commands (direct 0xFE0x) */ 2873 struct i40e_aqc_oem_param_change { 2874 __le32 param_type; 2875 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2876 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2877 #define I40E_AQ_OEM_PARAM_MAC 2 2878 __le32 param_value1; 2879 __le16 param_value2; 2880 u8 reserved[6]; 2881 }; 2882 2883 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2884 2885 struct i40e_aqc_oem_state_change { 2886 __le32 state; 2887 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2888 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2889 u8 reserved[12]; 2890 }; 2891 2892 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2893 2894 /* Initialize OCSD (0xFE02, direct) */ 2895 struct i40e_aqc_opc_oem_ocsd_initialize { 2896 u8 type_status; 2897 u8 reserved1[3]; 2898 __le32 ocsd_memory_block_addr_high; 2899 __le32 ocsd_memory_block_addr_low; 2900 __le32 requested_update_interval; 2901 }; 2902 2903 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2904 2905 /* Initialize OCBB (0xFE03, direct) */ 2906 struct i40e_aqc_opc_oem_ocbb_initialize { 2907 u8 type_status; 2908 u8 reserved1[3]; 2909 __le32 ocbb_memory_block_addr_high; 2910 __le32 ocbb_memory_block_addr_low; 2911 u8 reserved2[4]; 2912 }; 2913 2914 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2915 2916 /* debug commands */ 2917 2918 /* get device id (0xFF00) uses the generic structure */ 2919 2920 /* set test more (0xFF01, internal) */ 2921 2922 struct i40e_acq_set_test_mode { 2923 u8 mode; 2924 #define I40E_AQ_TEST_PARTIAL 0 2925 #define I40E_AQ_TEST_FULL 1 2926 #define I40E_AQ_TEST_NVM 2 2927 u8 reserved[3]; 2928 u8 command; 2929 #define I40E_AQ_TEST_OPEN 0 2930 #define I40E_AQ_TEST_CLOSE 1 2931 #define I40E_AQ_TEST_INC 2 2932 u8 reserved2[3]; 2933 __le32 address_high; 2934 __le32 address_low; 2935 }; 2936 2937 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2938 2939 /* Debug Read Register command (0xFF03) 2940 * Debug Write Register command (0xFF04) 2941 */ 2942 struct i40e_aqc_debug_reg_read_write { 2943 __le32 reserved; 2944 __le32 address; 2945 __le32 value_high; 2946 __le32 value_low; 2947 }; 2948 2949 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2950 2951 /* Scatter/gather Reg Read (indirect 0xFF05) 2952 * Scatter/gather Reg Write (indirect 0xFF06) 2953 */ 2954 2955 /* i40e_aq_desc is used for the command */ 2956 struct i40e_aqc_debug_reg_sg_element_data { 2957 __le32 address; 2958 __le32 value; 2959 }; 2960 2961 /* Debug Modify register (direct 0xFF07) */ 2962 struct i40e_aqc_debug_modify_reg { 2963 __le32 address; 2964 __le32 value; 2965 __le32 clear_mask; 2966 __le32 set_mask; 2967 }; 2968 2969 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2970 2971 /* dump internal data (0xFF08, indirect) */ 2972 2973 #define I40E_AQ_CLUSTER_ID_AUX 0 2974 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2975 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2976 #define I40E_AQ_CLUSTER_ID_HMC 3 2977 #define I40E_AQ_CLUSTER_ID_MAC0 4 2978 #define I40E_AQ_CLUSTER_ID_MAC1 5 2979 #define I40E_AQ_CLUSTER_ID_MAC2 6 2980 #define I40E_AQ_CLUSTER_ID_MAC3 7 2981 #define I40E_AQ_CLUSTER_ID_DCB 8 2982 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2983 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2984 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2985 2986 struct i40e_aqc_debug_dump_internals { 2987 u8 cluster_id; 2988 u8 table_id; 2989 __le16 data_size; 2990 __le32 idx; 2991 __le32 address_high; 2992 __le32 address_low; 2993 }; 2994 2995 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2996 2997 struct i40e_aqc_debug_modify_internals { 2998 u8 cluster_id; 2999 u8 cluster_specific_params[7]; 3000 __le32 address_high; 3001 __le32 address_low; 3002 }; 3003 3004 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 3005 3006 #endif /* _I40E_ADMINQ_CMD_H_ */ 3007