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Searched refs:iommu (Results 1 – 25 of 158) sorted by relevance

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/f-stack/freebsd/arm64/iommu/
H A Diommu.c85 iommu = iodom->iommu; in iommu_domain_unmap_buf()
111 iommu = iodom->iommu; in iommu_domain_map_buf()
128 iodom = IOMMU_DOMAIN_ALLOC(iommu->dev, iommu); in iommu_domain_alloc()
134 iodom->iommu = iommu; in iommu_domain_alloc()
145 iommu = iodom->iommu; in iommu_domain_free()
147 IOMMU_LOCK(iommu); in iommu_domain_free()
187 iommu = iodom->iommu; in iommu_ctx_alloc()
268 iommu = iodom->iommu; in iommu_free_ctx()
328 entry->iommu = iommu; in iommu_register()
346 if (entry->iommu == iommu) { in iommu_unregister()
[all …]
H A Diommu_if.m43 #include <dev/iommu/iommu.h>
45 INTERFACE iommu;
48 # Check if the iommu controller dev is responsible to serve traffic
83 struct iommu_unit *iommu;
110 # Allocate a new iommu context.
120 # Free the iommu context.
H A Dsmmu_acpi.c190 struct iommu_unit *iommu; in smmu_acpi_attach() local
212 iommu = &unit->iommu; in smmu_acpi_attach()
213 iommu->dev = dev; in smmu_acpi_attach()
220 err = iommu_register(iommu); in smmu_acpi_attach()
/f-stack/freebsd/contrib/device-tree/Bindings/media/
H A Dmediatek-vcodec.txt20 argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
43 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
44 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
88 iommus = <&iommu M4U_PORT_VENC_RCPU>,
89 <&iommu M4U_PORT_VENC_REC>,
90 <&iommu M4U_PORT_VENC_BSDMA>,
91 <&iommu M4U_PORT_VENC_SV_COMV>,
92 <&iommu M4U_PORT_VENC_RD_COMV>,
93 <&iommu M4U_PORT_VENC_CUR_LUMA>,
95 <&iommu M4U_PORT_VENC_REF_LUMA>,
[all …]
H A Dmediatek-mdp.txt28 argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
42 iommus = <&iommu M4U_PORT_MDP_RDMA0>;
53 iommus = <&iommu M4U_PORT_MDP_RDMA1>;
83 iommus = <&iommu M4U_PORT_MDP_WDMA>;
92 iommus = <&iommu M4U_PORT_MDP_WROT0>;
101 iommus = <&iommu M4U_PORT_MDP_WROT1>;
H A Dmediatek-jpeg-decoder.txt22 argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
36 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
37 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
/f-stack/freebsd/contrib/device-tree/Bindings/pci/
H A Dpci-iommu.txt26 Documentation/devicetree/bindings/iommu/iommu.txt.
39 (rid-base,iommu,iommu-base,length).
55 iommu: iommu@a {
70 iommu-map = <0x0 &iommu 0x0 0x10000>;
82 iommu: iommu@a {
97 iommu-map = <0x0 &iommu 0x0 0x10000>;
110 iommu: iommu@a {
125 iommu-map = <0x0000 &iommu 0x8000 0x8000>,
138 iommu_a: iommu@a {
144 iommu_b: iommu@b {
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/iommu/
H A Dqcom,iommu.txt53 apps_iommu: iommu@1e20000 {
56 #iommu-cells = <1>;
57 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
63 qcom,iommu-secure-id = <17>;
66 iommu-ctx@4000 {
73 iommu-ctx@5000 {
80 gpu_iommu: iommu@1f08000 {
83 #iommu-cells = <1>;
84 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
92 iommu-ctx@1000 {
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H A Dti,omap-iommu.txt5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
8 "ti,dra7-iommu" for DRA7xx IOMMU instances
16 Documentation/devicetree/bindings/iommu/iommu.txt
34 #iommu-cells = <0>;
35 compatible = "ti,omap2-iommu";
44 compatible = "ti,dra7-dsp-iommu";
48 #iommu-cells = <0>;
53 compatible = "ti,dra7-dsp-iommu";
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H A Dallwinner,sun50i-h6-iommu.yaml4 $id: http://devicetree.org/schemas/iommu/allwinner,sun50i-h6-iommu.yaml#
14 "#iommu-cells":
20 const: allwinner,sun50i-h6-iommu
35 - "#iommu-cells"
52 iommu: iommu@30f0000 {
53 compatible = "allwinner,sun50i-h6-iommu";
58 #iommu-cells = <1>;
H A Drockchip,iommu.txt4 A Rockchip DRM iommu translates io virtual addresses to physical addresses for
9 - compatible : Should be "rockchip,iommu"
13 - #iommu-cells : Should be <0>. This indicates the iommu is a
16 Documentation/devicetree/bindings/iommu/iommu.txt
30 vopl_mmu: iommu@ff940300 {
31 compatible = "rockchip,iommu";
37 #iommu-cells = <0>;
H A Dmsm,iommu-v0.txt9 - compatible: Must contain "qcom,apq8064-iommu".
15 - #iommu-cells: The number of cells needed to specify the stream id. This
27 required for iommu's register accesses.
29 required by iommu for bus accesses.
36 A single master device can be connected to more than one iommu
37 and multiple contexts in each of the iommu. So multiple entries
41 Example: mdp iommu and its bus master
43 mdp_port0: iommu@7500000 {
44 compatible = "qcom,apq8064-iommu";
45 #iommu-cells = <1>;
H A Darm,smmu.yaml23 pattern: "^iommu@[0-9a-f]*"
78 '#iommu-cells':
81 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
148 - '#iommu-cells'
173 smmu1: iommu@ba5e0000 {
183 #iommu-cells = <1>;
194 smmu2: iommu@ba5f0000 {
204 #iommu-cells = <2>;
220 smmu3: iommu@ba600000 {
247 smmu4: iommu@d00000 {
[all …]
H A Diommu.txt114 iommu {
115 #iommu-cells = <0>;
119 iommus = <&{/iommu}>;
126 iommu {
135 #iommu-cells = <0>;
141 iommus = <&{/iommu}>;
153 iommu {
155 #iommu-cells = <1>;
165 iommus = <&{/iommu} 23>, <&{/iommu} 24>;
172 iommu {
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H A Darm,smmu-v3.yaml4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
21 pattern: "^iommu@[0-9a-f]*"
48 '#iommu-cells':
75 - '#iommu-cells'
84 iommu@2b400000 {
93 #iommu-cells = <1>;
/f-stack/freebsd/contrib/device-tree/Bindings/virtio/
H A Dmmio.txt11 Required properties for virtio-iommu:
13 - #iommu-cells: When the node corresponds to a virtio-iommu device, it is
14 linked to DMA masters using the "iommus" or "iommu-map"
15 properties [1][2]. #iommu-cells specifies the size of the
16 "iommus" property. For virtio-iommu #iommu-cells must be
22 have an "iommus" property [1]. Since virtio-iommu itself
24 node cannot have both an "#iommu-cells" and an "iommus"
38 viommu: iommu@3100 {
43 #iommu-cells = <1>
46 [1] Documentation/devicetree/bindings/iommu/iommu.txt
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H A Diommu.txt3 When virtio-iommu uses the PCI transport, its programming interface is
6 masters. Therefore, the PCI root complex that hosts the virtio-iommu
11 - compatible: Should be "virtio,pci-iommu"
20 For virtio-iommu, #iommu-cells must be 1.
26 the iommu-map property of the root complex.
35 iommu0: iommu@0008 {
36 compatible = "virtio,pci-iommu";
38 #iommu-cells = <1>;
45 iommu-map = <0x0 &iommu0 0x0 0x8>
56 iommu-map = <0x0 &iommu0 0x10000 0x10000>;
[all …]
/f-stack/freebsd/contrib/device-tree/src/arm64/mediatek/
H A Dmt8173.dtsi519 iommu: iommu@10205000 { label
527 #iommu-cells = <1>;
1404 <&iommu M4U_PORT_VENC_REC>,
1405 <&iommu M4U_PORT_VENC_BSDMA>,
1406 <&iommu M4U_PORT_VENC_SV_COMV>,
1407 <&iommu M4U_PORT_VENC_RD_COMV>,
1408 <&iommu M4U_PORT_VENC_CUR_LUMA>,
1410 <&iommu M4U_PORT_VENC_REF_LUMA>,
1412 <&iommu M4U_PORT_VENC_NBM_RDMA>,
1413 <&iommu M4U_PORT_VENC_NBM_WDMA>,
[all …]
/f-stack/freebsd/x86/iommu/
H A Dintel_fault.c99 printf("DMAR%d: Invalidation timed out\n", unit->iommu.unit); in dmar_fault_intr_clear()
104 unit->iommu.unit); in dmar_fault_intr_clear()
109 unit->iommu.unit); in dmar_fault_intr_clear()
113 printf("DMAR%d: Advanced pending fault\n", unit->iommu.unit); in dmar_fault_intr_clear()
117 printf("DMAR%d: Advanced fault overflow\n", unit->iommu.unit); in dmar_fault_intr_clear()
179 printf("DMAR%d: Fault Overflow\n", unit->iommu.unit); in dmar_fault_intr()
211 printf("DMAR%d: ", unit->iommu.unit); in dmar_fault_task()
279 "dmar%d fault taskq", unit->iommu.unit); in dmar_init_fault_log()
H A Dintel_ctx.c275 domain->iodom.iommu->unit, start, end); in domain_init_rmrr()
295 IOMMU_LOCK(domain->iodom.iommu); in domain_init_rmrr()
298 IOMMU_UNLOCK(domain->iodom.iommu); in domain_init_rmrr()
306 domain->iodom.iommu->unit, start, end, in domain_init_rmrr()
460 IOMMU_ASSERT_LOCKED(domain->iodom.iommu); in dmar_ctx_link()
475 IOMMU_ASSERT_LOCKED(domain->iodom.iommu); in dmar_ctx_unlink()
639 dmar->iommu.unit); in dmar_get_ctx_for_dev1()
692 KASSERT(old_domain->iodom.iommu == domain->iodom.iommu, in dmar_move_ctx_to_domain()
695 domain->iodom.iommu->unit)); in dmar_move_ctx_to_domain()
947 dmar = IOMMU2DMAR(iommu); in iommu_get_ctx()
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/misc/
H A Dfsl,qoriq-mc.txt21 between ICIDs and IOMMUs, so an iommu-map property is used to define
26 Documentation/devicetree/bindings/iommu/iommu.txt.
29 Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
117 - iommu-map: Maps an ICID to an IOMMU and associated iommu-specifier
121 (icid-base,iommu,iommu-base,length).
124 associated with the listed IOMMU, with the iommu-specifier
125 (i - icid-base + iommu-base).
151 smmu: iommu@5000000 {
153 #iommu-cells = <1>;
173 iommu-map = <23 &smmu 23 41>;
/f-stack/freebsd/contrib/device-tree/src/arm64/renesas/
H A Dr8a77950.dtsi80 ipmmu_mp1: iommu@ec680000 {
85 #iommu-cells = <1>;
88 ipmmu_sy: iommu@e7730000 {
93 #iommu-cells = <1>;
96 /delete-node/ iommu@fd950000;
97 /delete-node/ iommu@fd960000;
98 /delete-node/ iommu@fd970000;
99 /delete-node/ iommu@febe0000;
100 /delete-node/ iommu@fe980000;
/f-stack/freebsd/contrib/device-tree/src/powerpc/fsl/
H A Dp5020si-post.dtsi66 fsl,iommu-parent = <&pamu0>;
95 fsl,iommu-parent = <&pamu0>;
124 fsl,iommu-parent = <&pamu0>;
153 fsl,iommu-parent = <&pamu0>;
178 fsl,iommu-parent = <&pamu0>;
307 iommu@20000 {
382 fsl,iommu-parent = <&pamu0>;
388 fsl,iommu-parent = <&pamu0>;
400 fsl,iommu-parent = <&pamu1>;
413 fsl,iommu-parent = <&pamu1>;
[all …]
H A Dp3041si-post.dtsi66 fsl,iommu-parent = <&pamu0>;
95 fsl,iommu-parent = <&pamu0>;
124 fsl,iommu-parent = <&pamu0>;
176 fsl,iommu-parent = <&pamu0>;
302 iommu@20000 {
377 fsl,iommu-parent = <&pamu0>;
383 fsl,iommu-parent = <&pamu0>;
395 fsl,iommu-parent = <&pamu1>;
409 fsl,iommu-parent = <&pamu1>;
417 fsl,iommu-parent = <&pamu1>;
[all …]
H A Dp2041si-post.dtsi66 fsl,iommu-parent = <&pamu0>;
95 fsl,iommu-parent = <&pamu0>;
124 fsl,iommu-parent = <&pamu0>;
149 fsl,iommu-parent = <&pamu0>;
275 iommu@20000 {
350 fsl,iommu-parent = <&pamu0>;
356 fsl,iommu-parent = <&pamu0>;
368 fsl,iommu-parent = <&pamu1>;
382 fsl,iommu-parent = <&pamu1>;
390 fsl,iommu-parent = <&pamu1>;
[all …]

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