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/f-stack/dpdk/lib/librte_pipeline/
H A Drte_swx_pipeline.c512 struct instruction *ip;
526 struct instruction { struct
644 struct instruction *ip;
645 struct instruction *ret;
3461 struct instruction *instr, in instr_alu_add_translate()
3514 struct instruction *instr, in instr_alu_sub_translate()
3644 struct instruction *instr, in instr_alu_shl_translate()
3697 struct instruction *instr, in instr_alu_shr_translate()
3750 struct instruction *instr, in instr_alu_and_translate()
3850 struct instruction *instr, in instr_alu_xor_translate()
[all …]
/f-stack/freebsd/contrib/openzfs/config/
H A Dhost-cpu-c-abi.m421 dnl instruction sets.
29 dnl although the instruction set of 'mips' is a large subset of the
30 dnl instruction set of 'mipsn32'.
33 dnl the instruction sets of 'mipsn32' and 'mips64' are the same.
45 dnl - Speed of execution of the common instruction set is reasonable across
66 # - 64-bit instruction set, 64-bit pointers, 64-bit 'long': x86_64.
67 # - 64-bit instruction set, 64-bit pointers, 32-bit 'long': x86_64
69 # - 64-bit instruction set, 32-bit pointers, 32-bit 'long': x86_64-x32.
70 # - 32-bit instruction set, 32-bit pointers, 32-bit 'long': i386.
103 # - aarch64 instruction set, 64-bit pointers, 64-bit 'long': arm64.
[all …]
H A Dlib-prefix.m4158 dnl 32-bit and 64-bit instruction sets or ABIs, 64-bit libraries go under
165 dnl 32-bit and 64-bit instruction sets or ABIs, 64-bit libraries go under
/f-stack/dpdk/lib/librte_acl/
H A Dmeson.build12 # a. we have AVX supported in minimum instruction set baseline
13 # b. it's not minimum instruction set, but supported by compiler
36 # a. we have AVX512 supported in minimum instruction set
38 # b. it's not minimum instruction set, but supported by
/f-stack/freebsd/contrib/device-tree/Bindings/watchdog/
H A Dmicrochip,pic32-dmt.txt4 malfunction. It is a free-running instruction fetch timer, which is clocked
5 whenever an instruction fetch occurs until a count match occurs.
/f-stack/dpdk/drivers/net/i40e/
H A Dmeson.build32 # a. we have AVX supported in minimum instruction set baseline
33 # b. it's not minimum instruction set, but supported by compiler
/f-stack/freebsd/contrib/device-tree/Bindings/nios2/
H A Dnios2.txt18 - icache-line-size: Contains instruction line size.
20 - icache-size: Contains instruction cache size.
28 - altr,has-initda: Specifies CPU support initda instruction, should be 1.
/f-stack/dpdk/drivers/net/iavf/
H A Dmeson.build22 # a. we have AVX supported in minimum instruction set baseline
23 # b. it's not minimum instruction set, but supported by compiler
/f-stack/dpdk/drivers/net/ice/
H A Dmeson.build24 # a. we have AVX supported in minimum instruction set baseline
25 # b. it's not minimum instruction set, but supported by compiler
/f-stack/freebsd/contrib/zstd/examples/
H A Dcommon.h99 static FILE* fopen_orDie(const char *filename, const char *instruction) in fopen_orDie() argument
101 FILE* const inFile = fopen(filename, instruction); in fopen_orDie()
/f-stack/dpdk/lib/librte_fib/
H A Dmeson.build13 # a. we have AVX512F supported in minimum instruction set baseline
14 # b. it's not minimum instruction set, but supported by compiler
/f-stack/freebsd/contrib/device-tree/Bindings/arm/freescale/
H A Dfsl,imx7ulp-pm.txt10 The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or
/f-stack/freebsd/contrib/device-tree/Bindings/riscv/
H A Dcpus.yaml39 Identifies that the hart uses the RISC-V instruction set
56 Identifies the specific RISC-V instruction set architecture
/f-stack/dpdk/app/
H A Dmeson.build36 # instruction-set optimized versions of code
/f-stack/freebsd/contrib/device-tree/Bindings/memory-controllers/
H A Dbrcm,dpfe-cpu.txt16 - start address and length of the DCPU instruction memory space
/f-stack/freebsd/contrib/device-tree/Bindings/media/
H A Drenesas,imr.txt5 with a simple instruction system capable of referencing video capture data or
/f-stack/freebsd/contrib/device-tree/Bindings/arm/firmware/
H A Dsdei.txt18 Note that the immediate field of the trapping instruction must be set
/f-stack/freebsd/contrib/device-tree/Bindings/eeprom/
H A Dat25.txt16 For 9 bits, the MSB of the address is sent as bit 3 of the instruction
/f-stack/dpdk/doc/guides/prog_guide/
H A Dtimer_lib.rst51 a Compare And Swap instruction should be used to guarantee that the status (state+owner) is modifie…
60 …done on 32-bit platforms without using either a compare-and-swap (CAS) instruction or using a lock,
H A Dwriting_efficient_code.rst176 On x86, atomic operations imply a lock prefix before the instruction,
177 causing the processor's LOCK# signal to be asserted during execution of the following instruction.
243 This avoids the cost of a call instruction (and the associated context saving).
265 …er version does not support the specific feature set (for example, the Intel® AVX instruction set),
274 These defines correspond to the instruction sets that the target CPU should be able to support.
H A Dstack_lib.rst74 compare-and-swap instruction to atomically update both the stack top pointer
/f-stack/freebsd/contrib/device-tree/Bindings/arm/msm/
H A Dqcom,idle-state.txt14 When the WFI instruction is executed the ARM core would gate its internal
15 clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
/f-stack/app/nginx-1.16.1/auto/cc/
H A Dgcc42 # "-mcpu=v9" enables the "casa" assembler instruction
/f-stack/dpdk/doc/guides/rawdevs/
H A Docteontx2_ep.rst17 #. Packet Input - Host to OCTEON TX2 with direct data instruction mode.
/f-stack/freebsd/contrib/zstd/lib/
H A DREADME.md139 the right instruction set (x64) and compiler (clang or gcc >= 5).
141 or when BMI2 instruction set is _required_ by the compiler command line

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