1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
3 */
4
5 #include <sys/queue.h>
6
7 #include <stdio.h>
8 #include <stdlib.h>
9 #include <string.h>
10 #include <errno.h>
11 #include <stdint.h>
12 #include <stdarg.h>
13 #include <inttypes.h>
14
15 #include <rte_interrupts.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_log.h>
19 #include <rte_debug.h>
20 #include <rte_pci.h>
21 #include <rte_bus_pci.h>
22 #include <rte_memory.h>
23 #include <rte_memcpy.h>
24 #include <rte_memzone.h>
25 #include <rte_launch.h>
26 #include <rte_eal.h>
27 #include <rte_per_lcore.h>
28 #include <rte_lcore.h>
29 #include <rte_atomic.h>
30 #include <rte_branch_prediction.h>
31 #include <rte_mempool.h>
32 #include <rte_malloc.h>
33 #include <rte_mbuf.h>
34 #include <rte_ether.h>
35 #include <rte_ethdev_driver.h>
36 #include <rte_prefetch.h>
37 #include <rte_ip.h>
38 #include <rte_udp.h>
39 #include <rte_tcp.h>
40 #include <rte_sctp.h>
41 #include <rte_net.h>
42 #include <rte_string_fns.h>
43
44 #include "e1000_logs.h"
45 #include "base/e1000_api.h"
46 #include "e1000_ethdev.h"
47 #include "base/e1000_osdep.h"
48
49 #define E1000_TXD_VLAN_SHIFT 16
50
51 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
52
53 #define E1000_TX_OFFLOAD_MASK ( \
54 PKT_TX_IPV6 | \
55 PKT_TX_IPV4 | \
56 PKT_TX_IP_CKSUM | \
57 PKT_TX_L4_MASK | \
58 PKT_TX_VLAN_PKT)
59
60 #define E1000_TX_OFFLOAD_NOTSUP_MASK \
61 (PKT_TX_OFFLOAD_MASK ^ E1000_TX_OFFLOAD_MASK)
62
63 /* PCI offset for querying configuration status register */
64 #define PCI_CFG_STATUS_REG 0x06
65 #define FLUSH_DESC_REQUIRED 0x100
66
67
68 /**
69 * Structure associated with each descriptor of the RX ring of a RX queue.
70 */
71 struct em_rx_entry {
72 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
73 };
74
75 /**
76 * Structure associated with each descriptor of the TX ring of a TX queue.
77 */
78 struct em_tx_entry {
79 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
80 uint16_t next_id; /**< Index of next descriptor in ring. */
81 uint16_t last_id; /**< Index of last scattered descriptor. */
82 };
83
84 /**
85 * Structure associated with each RX queue.
86 */
87 struct em_rx_queue {
88 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
89 volatile struct e1000_rx_desc *rx_ring; /**< RX ring virtual address. */
90 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
91 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
92 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
93 struct em_rx_entry *sw_ring; /**< address of RX software ring. */
94 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
95 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
96 uint64_t offloads; /**< Offloads of DEV_RX_OFFLOAD_* */
97 uint16_t nb_rx_desc; /**< number of RX descriptors. */
98 uint16_t rx_tail; /**< current value of RDT register. */
99 uint16_t nb_rx_hold; /**< number of held free RX desc. */
100 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
101 uint16_t queue_id; /**< RX queue index. */
102 uint16_t port_id; /**< Device port identifier. */
103 uint8_t pthresh; /**< Prefetch threshold register. */
104 uint8_t hthresh; /**< Host threshold register. */
105 uint8_t wthresh; /**< Write-back threshold register. */
106 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
107 };
108
109 /**
110 * Hardware context number
111 */
112 enum {
113 EM_CTX_0 = 0, /**< CTX0 */
114 EM_CTX_NUM = 1, /**< CTX NUM */
115 };
116
117 /** Offload features */
118 union em_vlan_macip {
119 uint32_t data;
120 struct {
121 uint16_t l3_len:9; /**< L3 (IP) Header Length. */
122 uint16_t l2_len:7; /**< L2 (MAC) Header Length. */
123 uint16_t vlan_tci;
124 /**< VLAN Tag Control Identifier (CPU order). */
125 } f;
126 };
127
128 /*
129 * Compare mask for vlan_macip_len.data,
130 * should be in sync with em_vlan_macip.f layout.
131 * */
132 #define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */
133 #define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */
134 #define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */
135 /** MAC+IP length. */
136 #define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)
137
138 /**
139 * Structure to check if new context need be built
140 */
141 struct em_ctx_info {
142 uint64_t flags; /**< ol_flags related to context build. */
143 uint32_t cmp_mask; /**< compare mask */
144 union em_vlan_macip hdrlen; /**< L2 and L3 header lenghts */
145 };
146
147 /**
148 * Structure associated with each TX queue.
149 */
150 struct em_tx_queue {
151 volatile struct e1000_data_desc *tx_ring; /**< TX ring address */
152 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
153 struct em_tx_entry *sw_ring; /**< virtual address of SW ring. */
154 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
155 uint16_t nb_tx_desc; /**< number of TX descriptors. */
156 uint16_t tx_tail; /**< Current value of TDT register. */
157 /**< Start freeing TX buffers if there are less free descriptors than
158 this value. */
159 uint16_t tx_free_thresh;
160 /**< Number of TX descriptors to use before RS bit is set. */
161 uint16_t tx_rs_thresh;
162 /** Number of TX descriptors used since RS bit was set. */
163 uint16_t nb_tx_used;
164 /** Index to last TX descriptor to have been cleaned. */
165 uint16_t last_desc_cleaned;
166 /** Total number of TX descriptors ready to be allocated. */
167 uint16_t nb_tx_free;
168 uint16_t queue_id; /**< TX queue index. */
169 uint16_t port_id; /**< Device port identifier. */
170 uint8_t pthresh; /**< Prefetch threshold register. */
171 uint8_t hthresh; /**< Host threshold register. */
172 uint8_t wthresh; /**< Write-back threshold register. */
173 struct em_ctx_info ctx_cache;
174 /**< Hardware context history.*/
175 uint64_t offloads; /**< offloads of DEV_TX_OFFLOAD_* */
176 };
177
178 #if 1
179 #define RTE_PMD_USE_PREFETCH
180 #endif
181
182 #ifdef RTE_PMD_USE_PREFETCH
183 #define rte_em_prefetch(p) rte_prefetch0(p)
184 #else
185 #define rte_em_prefetch(p) do {} while(0)
186 #endif
187
188 #ifdef RTE_PMD_PACKET_PREFETCH
189 #define rte_packet_prefetch(p) rte_prefetch1(p)
190 #else
191 #define rte_packet_prefetch(p) do {} while(0)
192 #endif
193
194 #ifndef DEFAULT_TX_FREE_THRESH
195 #define DEFAULT_TX_FREE_THRESH 32
196 #endif /* DEFAULT_TX_FREE_THRESH */
197
198 #ifndef DEFAULT_TX_RS_THRESH
199 #define DEFAULT_TX_RS_THRESH 32
200 #endif /* DEFAULT_TX_RS_THRESH */
201
202
203 /*********************************************************************
204 *
205 * TX function
206 *
207 **********************************************************************/
208
209 /*
210 * Populates TX context descriptor.
211 */
212 static inline void
em_set_xmit_ctx(struct em_tx_queue * txq,volatile struct e1000_context_desc * ctx_txd,uint64_t flags,union em_vlan_macip hdrlen)213 em_set_xmit_ctx(struct em_tx_queue* txq,
214 volatile struct e1000_context_desc *ctx_txd,
215 uint64_t flags,
216 union em_vlan_macip hdrlen)
217 {
218 uint32_t cmp_mask, cmd_len;
219 uint16_t ipcse, l2len;
220 struct e1000_context_desc ctx;
221
222 cmp_mask = 0;
223 cmd_len = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C;
224
225 l2len = hdrlen.f.l2_len;
226 ipcse = (uint16_t)(l2len + hdrlen.f.l3_len);
227
228 /* setup IPCS* fields */
229 ctx.lower_setup.ip_fields.ipcss = (uint8_t)l2len;
230 ctx.lower_setup.ip_fields.ipcso = (uint8_t)(l2len +
231 offsetof(struct rte_ipv4_hdr, hdr_checksum));
232
233 /*
234 * When doing checksum or TCP segmentation with IPv6 headers,
235 * IPCSE field should be set t0 0.
236 */
237 if (flags & PKT_TX_IP_CKSUM) {
238 ctx.lower_setup.ip_fields.ipcse =
239 (uint16_t)rte_cpu_to_le_16(ipcse - 1);
240 cmd_len |= E1000_TXD_CMD_IP;
241 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
242 } else {
243 ctx.lower_setup.ip_fields.ipcse = 0;
244 }
245
246 /* setup TUCS* fields */
247 ctx.upper_setup.tcp_fields.tucss = (uint8_t)ipcse;
248 ctx.upper_setup.tcp_fields.tucse = 0;
249
250 switch (flags & PKT_TX_L4_MASK) {
251 case PKT_TX_UDP_CKSUM:
252 ctx.upper_setup.tcp_fields.tucso = (uint8_t)(ipcse +
253 offsetof(struct rte_udp_hdr, dgram_cksum));
254 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
255 break;
256 case PKT_TX_TCP_CKSUM:
257 ctx.upper_setup.tcp_fields.tucso = (uint8_t)(ipcse +
258 offsetof(struct rte_tcp_hdr, cksum));
259 cmd_len |= E1000_TXD_CMD_TCP;
260 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
261 break;
262 default:
263 ctx.upper_setup.tcp_fields.tucso = 0;
264 }
265
266 ctx.cmd_and_length = rte_cpu_to_le_32(cmd_len);
267 ctx.tcp_seg_setup.data = 0;
268
269 *ctx_txd = ctx;
270
271 txq->ctx_cache.flags = flags;
272 txq->ctx_cache.cmp_mask = cmp_mask;
273 txq->ctx_cache.hdrlen = hdrlen;
274 }
275
276 /*
277 * Check which hardware context can be used. Use the existing match
278 * or create a new context descriptor.
279 */
280 static inline uint32_t
what_ctx_update(struct em_tx_queue * txq,uint64_t flags,union em_vlan_macip hdrlen)281 what_ctx_update(struct em_tx_queue *txq, uint64_t flags,
282 union em_vlan_macip hdrlen)
283 {
284 /* If match with the current context */
285 if (likely (txq->ctx_cache.flags == flags &&
286 ((txq->ctx_cache.hdrlen.data ^ hdrlen.data) &
287 txq->ctx_cache.cmp_mask) == 0))
288 return EM_CTX_0;
289
290 /* Mismatch */
291 return EM_CTX_NUM;
292 }
293
294 /* Reset transmit descriptors after they have been used */
295 static inline int
em_xmit_cleanup(struct em_tx_queue * txq)296 em_xmit_cleanup(struct em_tx_queue *txq)
297 {
298 struct em_tx_entry *sw_ring = txq->sw_ring;
299 volatile struct e1000_data_desc *txr = txq->tx_ring;
300 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
301 uint16_t nb_tx_desc = txq->nb_tx_desc;
302 uint16_t desc_to_clean_to;
303 uint16_t nb_tx_to_clean;
304
305 /* Determine the last descriptor needing to be cleaned */
306 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
307 if (desc_to_clean_to >= nb_tx_desc)
308 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
309
310 /* Check to make sure the last descriptor to clean is done */
311 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
312 if (! (txr[desc_to_clean_to].upper.fields.status & E1000_TXD_STAT_DD))
313 {
314 PMD_TX_FREE_LOG(DEBUG,
315 "TX descriptor %4u is not done"
316 "(port=%d queue=%d)", desc_to_clean_to,
317 txq->port_id, txq->queue_id);
318 /* Failed to clean any descriptors, better luck next time */
319 return -(1);
320 }
321
322 /* Figure out how many descriptors will be cleaned */
323 if (last_desc_cleaned > desc_to_clean_to)
324 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
325 desc_to_clean_to);
326 else
327 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
328 last_desc_cleaned);
329
330 PMD_TX_FREE_LOG(DEBUG,
331 "Cleaning %4u TX descriptors: %4u to %4u "
332 "(port=%d queue=%d)", nb_tx_to_clean,
333 last_desc_cleaned, desc_to_clean_to, txq->port_id,
334 txq->queue_id);
335
336 /*
337 * The last descriptor to clean is done, so that means all the
338 * descriptors from the last descriptor that was cleaned
339 * up to the last descriptor with the RS bit set
340 * are done. Only reset the threshold descriptor.
341 */
342 txr[desc_to_clean_to].upper.fields.status = 0;
343
344 /* Update the txq to reflect the last descriptor that was cleaned */
345 txq->last_desc_cleaned = desc_to_clean_to;
346 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
347
348 /* No Error */
349 return 0;
350 }
351
352 static inline uint32_t
tx_desc_cksum_flags_to_upper(uint64_t ol_flags)353 tx_desc_cksum_flags_to_upper(uint64_t ol_flags)
354 {
355 static const uint32_t l4_olinfo[2] = {0, E1000_TXD_POPTS_TXSM << 8};
356 static const uint32_t l3_olinfo[2] = {0, E1000_TXD_POPTS_IXSM << 8};
357 uint32_t tmp;
358
359 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
360 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
361 return tmp;
362 }
363
364 uint16_t
eth_em_xmit_pkts(void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)365 eth_em_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
366 uint16_t nb_pkts)
367 {
368 struct em_tx_queue *txq;
369 struct em_tx_entry *sw_ring;
370 struct em_tx_entry *txe, *txn;
371 volatile struct e1000_data_desc *txr;
372 volatile struct e1000_data_desc *txd;
373 struct rte_mbuf *tx_pkt;
374 struct rte_mbuf *m_seg;
375 uint64_t buf_dma_addr;
376 uint32_t popts_spec;
377 uint32_t cmd_type_len;
378 uint16_t slen;
379 uint64_t ol_flags;
380 uint16_t tx_id;
381 uint16_t tx_last;
382 uint16_t nb_tx;
383 uint16_t nb_used;
384 uint64_t tx_ol_req;
385 uint32_t ctx;
386 uint32_t new_ctx;
387 union em_vlan_macip hdrlen;
388
389 txq = tx_queue;
390 sw_ring = txq->sw_ring;
391 txr = txq->tx_ring;
392 tx_id = txq->tx_tail;
393 txe = &sw_ring[tx_id];
394
395 /* Determine if the descriptor ring needs to be cleaned. */
396 if (txq->nb_tx_free < txq->tx_free_thresh)
397 em_xmit_cleanup(txq);
398
399 /* TX loop */
400 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
401 new_ctx = 0;
402 tx_pkt = *tx_pkts++;
403
404 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
405
406 /*
407 * Determine how many (if any) context descriptors
408 * are needed for offload functionality.
409 */
410 ol_flags = tx_pkt->ol_flags;
411
412 /* If hardware offload required */
413 tx_ol_req = (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK));
414 if (tx_ol_req) {
415 hdrlen.f.vlan_tci = tx_pkt->vlan_tci;
416 hdrlen.f.l2_len = tx_pkt->l2_len;
417 hdrlen.f.l3_len = tx_pkt->l3_len;
418 /* If new context to be built or reuse the exist ctx. */
419 ctx = what_ctx_update(txq, tx_ol_req, hdrlen);
420
421 /* Only allocate context descriptor if required*/
422 new_ctx = (ctx == EM_CTX_NUM);
423 }
424
425 /*
426 * Keep track of how many descriptors are used this loop
427 * This will always be the number of segments + the number of
428 * Context descriptors required to transmit the packet
429 */
430 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
431
432 /*
433 * The number of descriptors that must be allocated for a
434 * packet is the number of segments of that packet, plus 1
435 * Context Descriptor for the hardware offload, if any.
436 * Determine the last TX descriptor to allocate in the TX ring
437 * for the packet, starting from the current position (tx_id)
438 * in the ring.
439 */
440 tx_last = (uint16_t) (tx_id + nb_used - 1);
441
442 /* Circular ring */
443 if (tx_last >= txq->nb_tx_desc)
444 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
445
446 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
447 " tx_first=%u tx_last=%u",
448 (unsigned) txq->port_id,
449 (unsigned) txq->queue_id,
450 (unsigned) tx_pkt->pkt_len,
451 (unsigned) tx_id,
452 (unsigned) tx_last);
453
454 /*
455 * Make sure there are enough TX descriptors available to
456 * transmit the entire packet.
457 * nb_used better be less than or equal to txq->tx_rs_thresh
458 */
459 while (unlikely (nb_used > txq->nb_tx_free)) {
460 PMD_TX_FREE_LOG(DEBUG, "Not enough free TX descriptors "
461 "nb_used=%4u nb_free=%4u "
462 "(port=%d queue=%d)",
463 nb_used, txq->nb_tx_free,
464 txq->port_id, txq->queue_id);
465
466 if (em_xmit_cleanup(txq) != 0) {
467 /* Could not clean any descriptors */
468 if (nb_tx == 0)
469 return 0;
470 goto end_of_tx;
471 }
472 }
473
474 /*
475 * By now there are enough free TX descriptors to transmit
476 * the packet.
477 */
478
479 /*
480 * Set common flags of all TX Data Descriptors.
481 *
482 * The following bits must be set in all Data Descriptors:
483 * - E1000_TXD_DTYP_DATA
484 * - E1000_TXD_DTYP_DEXT
485 *
486 * The following bits must be set in the first Data Descriptor
487 * and are ignored in the other ones:
488 * - E1000_TXD_POPTS_IXSM
489 * - E1000_TXD_POPTS_TXSM
490 *
491 * The following bits must be set in the last Data Descriptor
492 * and are ignored in the other ones:
493 * - E1000_TXD_CMD_VLE
494 * - E1000_TXD_CMD_IFCS
495 *
496 * The following bits must only be set in the last Data
497 * Descriptor:
498 * - E1000_TXD_CMD_EOP
499 *
500 * The following bits can be set in any Data Descriptor, but
501 * are only set in the last Data Descriptor:
502 * - E1000_TXD_CMD_RS
503 */
504 cmd_type_len = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
505 E1000_TXD_CMD_IFCS;
506 popts_spec = 0;
507
508 /* Set VLAN Tag offload fields. */
509 if (ol_flags & PKT_TX_VLAN_PKT) {
510 cmd_type_len |= E1000_TXD_CMD_VLE;
511 popts_spec = tx_pkt->vlan_tci << E1000_TXD_VLAN_SHIFT;
512 }
513
514 if (tx_ol_req) {
515 /*
516 * Setup the TX Context Descriptor if required
517 */
518 if (new_ctx) {
519 volatile struct e1000_context_desc *ctx_txd;
520
521 ctx_txd = (volatile struct e1000_context_desc *)
522 &txr[tx_id];
523
524 txn = &sw_ring[txe->next_id];
525 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
526
527 if (txe->mbuf != NULL) {
528 rte_pktmbuf_free_seg(txe->mbuf);
529 txe->mbuf = NULL;
530 }
531
532 em_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
533 hdrlen);
534
535 txe->last_id = tx_last;
536 tx_id = txe->next_id;
537 txe = txn;
538 }
539
540 /*
541 * Setup the TX Data Descriptor,
542 * This path will go through
543 * whatever new/reuse the context descriptor
544 */
545 popts_spec |= tx_desc_cksum_flags_to_upper(ol_flags);
546 }
547
548 m_seg = tx_pkt;
549 do {
550 txd = &txr[tx_id];
551 txn = &sw_ring[txe->next_id];
552
553 if (txe->mbuf != NULL)
554 rte_pktmbuf_free_seg(txe->mbuf);
555 txe->mbuf = m_seg;
556
557 /*
558 * Set up Transmit Data Descriptor.
559 */
560 slen = m_seg->data_len;
561 buf_dma_addr = rte_mbuf_data_iova(m_seg);
562
563 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
564 txd->lower.data = rte_cpu_to_le_32(cmd_type_len | slen);
565 txd->upper.data = rte_cpu_to_le_32(popts_spec);
566
567 txe->last_id = tx_last;
568 tx_id = txe->next_id;
569 txe = txn;
570 m_seg = m_seg->next;
571 } while (m_seg != NULL);
572
573 /*
574 * The last packet data descriptor needs End Of Packet (EOP)
575 */
576 cmd_type_len |= E1000_TXD_CMD_EOP;
577 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
578 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
579
580 /* Set RS bit only on threshold packets' last descriptor */
581 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
582 PMD_TX_FREE_LOG(DEBUG,
583 "Setting RS bit on TXD id=%4u "
584 "(port=%d queue=%d)",
585 tx_last, txq->port_id, txq->queue_id);
586
587 cmd_type_len |= E1000_TXD_CMD_RS;
588
589 /* Update txq RS bit counters */
590 txq->nb_tx_used = 0;
591 }
592 txd->lower.data |= rte_cpu_to_le_32(cmd_type_len);
593 }
594 end_of_tx:
595 rte_wmb();
596
597 /*
598 * Set the Transmit Descriptor Tail (TDT)
599 */
600 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
601 (unsigned) txq->port_id, (unsigned) txq->queue_id,
602 (unsigned) tx_id, (unsigned) nb_tx);
603 E1000_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
604 txq->tx_tail = tx_id;
605
606 return nb_tx;
607 }
608
609 /*********************************************************************
610 *
611 * TX prep functions
612 *
613 **********************************************************************/
614 uint16_t
eth_em_prep_pkts(__rte_unused void * tx_queue,struct rte_mbuf ** tx_pkts,uint16_t nb_pkts)615 eth_em_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
616 uint16_t nb_pkts)
617 {
618 int i, ret;
619 struct rte_mbuf *m;
620
621 for (i = 0; i < nb_pkts; i++) {
622 m = tx_pkts[i];
623
624 if (m->ol_flags & E1000_TX_OFFLOAD_NOTSUP_MASK) {
625 rte_errno = ENOTSUP;
626 return i;
627 }
628
629 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
630 ret = rte_validate_tx_offload(m);
631 if (ret != 0) {
632 rte_errno = -ret;
633 return i;
634 }
635 #endif
636 ret = rte_net_intel_cksum_prepare(m);
637 if (ret != 0) {
638 rte_errno = -ret;
639 return i;
640 }
641 }
642
643 return i;
644 }
645
646 /*********************************************************************
647 *
648 * RX functions
649 *
650 **********************************************************************/
651
652 static inline uint64_t
rx_desc_status_to_pkt_flags(uint32_t rx_status)653 rx_desc_status_to_pkt_flags(uint32_t rx_status)
654 {
655 uint64_t pkt_flags;
656
657 /* Check if VLAN present */
658 pkt_flags = ((rx_status & E1000_RXD_STAT_VP) ?
659 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED : 0);
660
661 return pkt_flags;
662 }
663
664 static inline uint64_t
rx_desc_error_to_pkt_flags(uint32_t rx_error)665 rx_desc_error_to_pkt_flags(uint32_t rx_error)
666 {
667 uint64_t pkt_flags = 0;
668
669 if (rx_error & E1000_RXD_ERR_IPE)
670 pkt_flags |= PKT_RX_IP_CKSUM_BAD;
671 if (rx_error & E1000_RXD_ERR_TCPE)
672 pkt_flags |= PKT_RX_L4_CKSUM_BAD;
673 return pkt_flags;
674 }
675
676 uint16_t
eth_em_recv_pkts(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)677 eth_em_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
678 uint16_t nb_pkts)
679 {
680 volatile struct e1000_rx_desc *rx_ring;
681 volatile struct e1000_rx_desc *rxdp;
682 struct em_rx_queue *rxq;
683 struct em_rx_entry *sw_ring;
684 struct em_rx_entry *rxe;
685 struct rte_mbuf *rxm;
686 struct rte_mbuf *nmb;
687 struct e1000_rx_desc rxd;
688 uint64_t dma_addr;
689 uint16_t pkt_len;
690 uint16_t rx_id;
691 uint16_t nb_rx;
692 uint16_t nb_hold;
693 uint8_t status;
694
695 rxq = rx_queue;
696
697 nb_rx = 0;
698 nb_hold = 0;
699 rx_id = rxq->rx_tail;
700 rx_ring = rxq->rx_ring;
701 sw_ring = rxq->sw_ring;
702 while (nb_rx < nb_pkts) {
703 /*
704 * The order of operations here is important as the DD status
705 * bit must not be read after any other descriptor fields.
706 * rx_ring and rxdp are pointing to volatile data so the order
707 * of accesses cannot be reordered by the compiler. If they were
708 * not volatile, they could be reordered which could lead to
709 * using invalid descriptor fields when read from rxd.
710 */
711 rxdp = &rx_ring[rx_id];
712 status = rxdp->status;
713 if (! (status & E1000_RXD_STAT_DD))
714 break;
715 rxd = *rxdp;
716
717 /*
718 * End of packet.
719 *
720 * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is
721 * likely to be invalid and to be dropped by the various
722 * validation checks performed by the network stack.
723 *
724 * Allocate a new mbuf to replenish the RX ring descriptor.
725 * If the allocation fails:
726 * - arrange for that RX descriptor to be the first one
727 * being parsed the next time the receive function is
728 * invoked [on the same queue].
729 *
730 * - Stop parsing the RX ring and return immediately.
731 *
732 * This policy do not drop the packet received in the RX
733 * descriptor for which the allocation of a new mbuf failed.
734 * Thus, it allows that packet to be later retrieved if
735 * mbuf have been freed in the mean time.
736 * As a side effect, holding RX descriptors instead of
737 * systematically giving them back to the NIC may lead to
738 * RX ring exhaustion situations.
739 * However, the NIC can gracefully prevent such situations
740 * to happen by sending specific "back-pressure" flow control
741 * frames to its peer(s).
742 */
743 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
744 "status=0x%x pkt_len=%u",
745 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
746 (unsigned) rx_id, (unsigned) status,
747 (unsigned) rte_le_to_cpu_16(rxd.length));
748
749 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
750 if (nmb == NULL) {
751 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
752 "queue_id=%u",
753 (unsigned) rxq->port_id,
754 (unsigned) rxq->queue_id);
755 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
756 break;
757 }
758
759 nb_hold++;
760 rxe = &sw_ring[rx_id];
761 rx_id++;
762 if (rx_id == rxq->nb_rx_desc)
763 rx_id = 0;
764
765 /* Prefetch next mbuf while processing current one. */
766 rte_em_prefetch(sw_ring[rx_id].mbuf);
767
768 /*
769 * When next RX descriptor is on a cache-line boundary,
770 * prefetch the next 4 RX descriptors and the next 8 pointers
771 * to mbufs.
772 */
773 if ((rx_id & 0x3) == 0) {
774 rte_em_prefetch(&rx_ring[rx_id]);
775 rte_em_prefetch(&sw_ring[rx_id]);
776 }
777
778 /* Rearm RXD: attach new mbuf and reset status to zero. */
779
780 rxm = rxe->mbuf;
781 rxe->mbuf = nmb;
782 dma_addr =
783 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
784 rxdp->buffer_addr = dma_addr;
785 rxdp->status = 0;
786
787 /*
788 * Initialize the returned mbuf.
789 * 1) setup generic mbuf fields:
790 * - number of segments,
791 * - next segment,
792 * - packet length,
793 * - RX port identifier.
794 * 2) integrate hardware offload data, if any:
795 * - RSS flag & hash,
796 * - IP checksum flag,
797 * - VLAN TCI, if any,
798 * - error flags.
799 */
800 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.length) -
801 rxq->crc_len);
802 rxm->data_off = RTE_PKTMBUF_HEADROOM;
803 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
804 rxm->nb_segs = 1;
805 rxm->next = NULL;
806 rxm->pkt_len = pkt_len;
807 rxm->data_len = pkt_len;
808 rxm->port = rxq->port_id;
809
810 rxm->ol_flags = rx_desc_status_to_pkt_flags(status);
811 rxm->ol_flags = rxm->ol_flags |
812 rx_desc_error_to_pkt_flags(rxd.errors);
813
814 /* Only valid if PKT_RX_VLAN set in pkt_flags */
815 rxm->vlan_tci = rte_le_to_cpu_16(rxd.special);
816
817 /*
818 * Store the mbuf address into the next entry of the array
819 * of returned packets.
820 */
821 rx_pkts[nb_rx++] = rxm;
822 }
823 rxq->rx_tail = rx_id;
824
825 /*
826 * If the number of free RX descriptors is greater than the RX free
827 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
828 * register.
829 * Update the RDT with the value of the last processed RX descriptor
830 * minus 1, to guarantee that the RDT register is never equal to the
831 * RDH register, which creates a "full" ring situtation from the
832 * hardware point of view...
833 */
834 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
835 if (nb_hold > rxq->rx_free_thresh) {
836 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
837 "nb_hold=%u nb_rx=%u",
838 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
839 (unsigned) rx_id, (unsigned) nb_hold,
840 (unsigned) nb_rx);
841 rx_id = (uint16_t) ((rx_id == 0) ?
842 (rxq->nb_rx_desc - 1) : (rx_id - 1));
843 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
844 nb_hold = 0;
845 }
846 rxq->nb_rx_hold = nb_hold;
847 return nb_rx;
848 }
849
850 uint16_t
eth_em_recv_scattered_pkts(void * rx_queue,struct rte_mbuf ** rx_pkts,uint16_t nb_pkts)851 eth_em_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
852 uint16_t nb_pkts)
853 {
854 struct em_rx_queue *rxq;
855 volatile struct e1000_rx_desc *rx_ring;
856 volatile struct e1000_rx_desc *rxdp;
857 struct em_rx_entry *sw_ring;
858 struct em_rx_entry *rxe;
859 struct rte_mbuf *first_seg;
860 struct rte_mbuf *last_seg;
861 struct rte_mbuf *rxm;
862 struct rte_mbuf *nmb;
863 struct e1000_rx_desc rxd;
864 uint64_t dma; /* Physical address of mbuf data buffer */
865 uint16_t rx_id;
866 uint16_t nb_rx;
867 uint16_t nb_hold;
868 uint16_t data_len;
869 uint8_t status;
870
871 rxq = rx_queue;
872
873 nb_rx = 0;
874 nb_hold = 0;
875 rx_id = rxq->rx_tail;
876 rx_ring = rxq->rx_ring;
877 sw_ring = rxq->sw_ring;
878
879 /*
880 * Retrieve RX context of current packet, if any.
881 */
882 first_seg = rxq->pkt_first_seg;
883 last_seg = rxq->pkt_last_seg;
884
885 while (nb_rx < nb_pkts) {
886 next_desc:
887 /*
888 * The order of operations here is important as the DD status
889 * bit must not be read after any other descriptor fields.
890 * rx_ring and rxdp are pointing to volatile data so the order
891 * of accesses cannot be reordered by the compiler. If they were
892 * not volatile, they could be reordered which could lead to
893 * using invalid descriptor fields when read from rxd.
894 */
895 rxdp = &rx_ring[rx_id];
896 status = rxdp->status;
897 if (! (status & E1000_RXD_STAT_DD))
898 break;
899 rxd = *rxdp;
900
901 /*
902 * Descriptor done.
903 *
904 * Allocate a new mbuf to replenish the RX ring descriptor.
905 * If the allocation fails:
906 * - arrange for that RX descriptor to be the first one
907 * being parsed the next time the receive function is
908 * invoked [on the same queue].
909 *
910 * - Stop parsing the RX ring and return immediately.
911 *
912 * This policy does not drop the packet received in the RX
913 * descriptor for which the allocation of a new mbuf failed.
914 * Thus, it allows that packet to be later retrieved if
915 * mbuf have been freed in the mean time.
916 * As a side effect, holding RX descriptors instead of
917 * systematically giving them back to the NIC may lead to
918 * RX ring exhaustion situations.
919 * However, the NIC can gracefully prevent such situations
920 * to happen by sending specific "back-pressure" flow control
921 * frames to its peer(s).
922 */
923 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
924 "status=0x%x data_len=%u",
925 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
926 (unsigned) rx_id, (unsigned) status,
927 (unsigned) rte_le_to_cpu_16(rxd.length));
928
929 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
930 if (nmb == NULL) {
931 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
932 "queue_id=%u", (unsigned) rxq->port_id,
933 (unsigned) rxq->queue_id);
934 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
935 break;
936 }
937
938 nb_hold++;
939 rxe = &sw_ring[rx_id];
940 rx_id++;
941 if (rx_id == rxq->nb_rx_desc)
942 rx_id = 0;
943
944 /* Prefetch next mbuf while processing current one. */
945 rte_em_prefetch(sw_ring[rx_id].mbuf);
946
947 /*
948 * When next RX descriptor is on a cache-line boundary,
949 * prefetch the next 4 RX descriptors and the next 8 pointers
950 * to mbufs.
951 */
952 if ((rx_id & 0x3) == 0) {
953 rte_em_prefetch(&rx_ring[rx_id]);
954 rte_em_prefetch(&sw_ring[rx_id]);
955 }
956
957 /*
958 * Update RX descriptor with the physical address of the new
959 * data buffer of the new allocated mbuf.
960 */
961 rxm = rxe->mbuf;
962 rxe->mbuf = nmb;
963 dma = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
964 rxdp->buffer_addr = dma;
965 rxdp->status = 0;
966
967 /*
968 * Set data length & data buffer address of mbuf.
969 */
970 data_len = rte_le_to_cpu_16(rxd.length);
971 rxm->data_len = data_len;
972 rxm->data_off = RTE_PKTMBUF_HEADROOM;
973
974 /*
975 * If this is the first buffer of the received packet,
976 * set the pointer to the first mbuf of the packet and
977 * initialize its context.
978 * Otherwise, update the total length and the number of segments
979 * of the current scattered packet, and update the pointer to
980 * the last mbuf of the current packet.
981 */
982 if (first_seg == NULL) {
983 first_seg = rxm;
984 first_seg->pkt_len = data_len;
985 first_seg->nb_segs = 1;
986 } else {
987 first_seg->pkt_len += data_len;
988 first_seg->nb_segs++;
989 last_seg->next = rxm;
990 }
991
992 /*
993 * If this is not the last buffer of the received packet,
994 * update the pointer to the last mbuf of the current scattered
995 * packet and continue to parse the RX ring.
996 */
997 if (! (status & E1000_RXD_STAT_EOP)) {
998 last_seg = rxm;
999 goto next_desc;
1000 }
1001
1002 /*
1003 * This is the last buffer of the received packet.
1004 * If the CRC is not stripped by the hardware:
1005 * - Subtract the CRC length from the total packet length.
1006 * - If the last buffer only contains the whole CRC or a part
1007 * of it, free the mbuf associated to the last buffer.
1008 * If part of the CRC is also contained in the previous
1009 * mbuf, subtract the length of that CRC part from the
1010 * data length of the previous mbuf.
1011 */
1012 rxm->next = NULL;
1013 if (unlikely(rxq->crc_len > 0)) {
1014 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1015 if (data_len <= RTE_ETHER_CRC_LEN) {
1016 rte_pktmbuf_free_seg(rxm);
1017 first_seg->nb_segs--;
1018 last_seg->data_len = (uint16_t)
1019 (last_seg->data_len -
1020 (RTE_ETHER_CRC_LEN - data_len));
1021 last_seg->next = NULL;
1022 } else
1023 rxm->data_len = (uint16_t)
1024 (data_len - RTE_ETHER_CRC_LEN);
1025 }
1026
1027 /*
1028 * Initialize the first mbuf of the returned packet:
1029 * - RX port identifier,
1030 * - hardware offload data, if any:
1031 * - IP checksum flag,
1032 * - error flags.
1033 */
1034 first_seg->port = rxq->port_id;
1035
1036 first_seg->ol_flags = rx_desc_status_to_pkt_flags(status);
1037 first_seg->ol_flags = first_seg->ol_flags |
1038 rx_desc_error_to_pkt_flags(rxd.errors);
1039
1040 /* Only valid if PKT_RX_VLAN set in pkt_flags */
1041 rxm->vlan_tci = rte_le_to_cpu_16(rxd.special);
1042
1043 /* Prefetch data of first segment, if configured to do so. */
1044 rte_packet_prefetch((char *)first_seg->buf_addr +
1045 first_seg->data_off);
1046
1047 /*
1048 * Store the mbuf address into the next entry of the array
1049 * of returned packets.
1050 */
1051 rx_pkts[nb_rx++] = first_seg;
1052
1053 /*
1054 * Setup receipt context for a new packet.
1055 */
1056 first_seg = NULL;
1057 }
1058
1059 /*
1060 * Record index of the next RX descriptor to probe.
1061 */
1062 rxq->rx_tail = rx_id;
1063
1064 /*
1065 * Save receive context.
1066 */
1067 rxq->pkt_first_seg = first_seg;
1068 rxq->pkt_last_seg = last_seg;
1069
1070 /*
1071 * If the number of free RX descriptors is greater than the RX free
1072 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1073 * register.
1074 * Update the RDT with the value of the last processed RX descriptor
1075 * minus 1, to guarantee that the RDT register is never equal to the
1076 * RDH register, which creates a "full" ring situtation from the
1077 * hardware point of view...
1078 */
1079 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1080 if (nb_hold > rxq->rx_free_thresh) {
1081 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1082 "nb_hold=%u nb_rx=%u",
1083 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1084 (unsigned) rx_id, (unsigned) nb_hold,
1085 (unsigned) nb_rx);
1086 rx_id = (uint16_t) ((rx_id == 0) ?
1087 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1088 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1089 nb_hold = 0;
1090 }
1091 rxq->nb_rx_hold = nb_hold;
1092 return nb_rx;
1093 }
1094
1095 #define EM_MAX_BUF_SIZE 16384
1096 #define EM_RCTL_FLXBUF_STEP 1024
1097
1098 static void
em_tx_queue_release_mbufs(struct em_tx_queue * txq)1099 em_tx_queue_release_mbufs(struct em_tx_queue *txq)
1100 {
1101 unsigned i;
1102
1103 if (txq->sw_ring != NULL) {
1104 for (i = 0; i != txq->nb_tx_desc; i++) {
1105 if (txq->sw_ring[i].mbuf != NULL) {
1106 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1107 txq->sw_ring[i].mbuf = NULL;
1108 }
1109 }
1110 }
1111 }
1112
1113 static void
em_tx_queue_release(struct em_tx_queue * txq)1114 em_tx_queue_release(struct em_tx_queue *txq)
1115 {
1116 if (txq != NULL) {
1117 em_tx_queue_release_mbufs(txq);
1118 rte_free(txq->sw_ring);
1119 rte_free(txq);
1120 }
1121 }
1122
1123 void
eth_em_tx_queue_release(void * txq)1124 eth_em_tx_queue_release(void *txq)
1125 {
1126 em_tx_queue_release(txq);
1127 }
1128
1129 /* (Re)set dynamic em_tx_queue fields to defaults */
1130 static void
em_reset_tx_queue(struct em_tx_queue * txq)1131 em_reset_tx_queue(struct em_tx_queue *txq)
1132 {
1133 uint16_t i, nb_desc, prev;
1134 static const struct e1000_data_desc txd_init = {
1135 .upper.fields = {.status = E1000_TXD_STAT_DD},
1136 };
1137
1138 nb_desc = txq->nb_tx_desc;
1139
1140 /* Initialize ring entries */
1141
1142 prev = (uint16_t) (nb_desc - 1);
1143
1144 for (i = 0; i < nb_desc; i++) {
1145 txq->tx_ring[i] = txd_init;
1146 txq->sw_ring[i].mbuf = NULL;
1147 txq->sw_ring[i].last_id = i;
1148 txq->sw_ring[prev].next_id = i;
1149 prev = i;
1150 }
1151
1152 /*
1153 * Always allow 1 descriptor to be un-allocated to avoid
1154 * a H/W race condition
1155 */
1156 txq->nb_tx_free = (uint16_t)(nb_desc - 1);
1157 txq->last_desc_cleaned = (uint16_t)(nb_desc - 1);
1158 txq->nb_tx_used = 0;
1159 txq->tx_tail = 0;
1160
1161 memset((void*)&txq->ctx_cache, 0, sizeof (txq->ctx_cache));
1162 }
1163
1164 uint64_t
em_get_tx_port_offloads_capa(struct rte_eth_dev * dev)1165 em_get_tx_port_offloads_capa(struct rte_eth_dev *dev)
1166 {
1167 uint64_t tx_offload_capa;
1168
1169 RTE_SET_USED(dev);
1170 tx_offload_capa =
1171 DEV_TX_OFFLOAD_MULTI_SEGS |
1172 DEV_TX_OFFLOAD_VLAN_INSERT |
1173 DEV_TX_OFFLOAD_IPV4_CKSUM |
1174 DEV_TX_OFFLOAD_UDP_CKSUM |
1175 DEV_TX_OFFLOAD_TCP_CKSUM;
1176
1177 return tx_offload_capa;
1178 }
1179
1180 uint64_t
em_get_tx_queue_offloads_capa(struct rte_eth_dev * dev)1181 em_get_tx_queue_offloads_capa(struct rte_eth_dev *dev)
1182 {
1183 uint64_t tx_queue_offload_capa;
1184
1185 /*
1186 * As only one Tx queue can be used, let per queue offloading
1187 * capability be same to per port queue offloading capability
1188 * for better convenience.
1189 */
1190 tx_queue_offload_capa = em_get_tx_port_offloads_capa(dev);
1191
1192 return tx_queue_offload_capa;
1193 }
1194
1195 int
eth_em_tx_queue_setup(struct rte_eth_dev * dev,uint16_t queue_idx,uint16_t nb_desc,unsigned int socket_id,const struct rte_eth_txconf * tx_conf)1196 eth_em_tx_queue_setup(struct rte_eth_dev *dev,
1197 uint16_t queue_idx,
1198 uint16_t nb_desc,
1199 unsigned int socket_id,
1200 const struct rte_eth_txconf *tx_conf)
1201 {
1202 const struct rte_memzone *tz;
1203 struct em_tx_queue *txq;
1204 struct e1000_hw *hw;
1205 uint32_t tsize;
1206 uint16_t tx_rs_thresh, tx_free_thresh;
1207 uint64_t offloads;
1208
1209 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1210
1211 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1212
1213 /*
1214 * Validate number of transmit descriptors.
1215 * It must not exceed hardware maximum, and must be multiple
1216 * of E1000_ALIGN.
1217 */
1218 if (nb_desc % EM_TXD_ALIGN != 0 ||
1219 (nb_desc > E1000_MAX_RING_DESC) ||
1220 (nb_desc < E1000_MIN_RING_DESC)) {
1221 return -(EINVAL);
1222 }
1223
1224 tx_free_thresh = tx_conf->tx_free_thresh;
1225 if (tx_free_thresh == 0)
1226 tx_free_thresh = (uint16_t)RTE_MIN(nb_desc / 4,
1227 DEFAULT_TX_FREE_THRESH);
1228
1229 tx_rs_thresh = tx_conf->tx_rs_thresh;
1230 if (tx_rs_thresh == 0)
1231 tx_rs_thresh = (uint16_t)RTE_MIN(tx_free_thresh,
1232 DEFAULT_TX_RS_THRESH);
1233
1234 if (tx_free_thresh >= (nb_desc - 3)) {
1235 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
1236 "number of TX descriptors minus 3. "
1237 "(tx_free_thresh=%u port=%d queue=%d)",
1238 (unsigned int)tx_free_thresh,
1239 (int)dev->data->port_id, (int)queue_idx);
1240 return -(EINVAL);
1241 }
1242 if (tx_rs_thresh > tx_free_thresh) {
1243 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1244 "tx_free_thresh. (tx_free_thresh=%u "
1245 "tx_rs_thresh=%u port=%d queue=%d)",
1246 (unsigned int)tx_free_thresh,
1247 (unsigned int)tx_rs_thresh,
1248 (int)dev->data->port_id,
1249 (int)queue_idx);
1250 return -(EINVAL);
1251 }
1252
1253 /*
1254 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1255 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1256 * by the NIC and all descriptors are written back after the NIC
1257 * accumulates WTHRESH descriptors.
1258 */
1259 if (tx_conf->tx_thresh.wthresh != 0 && tx_rs_thresh != 1) {
1260 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1261 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1262 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1263 (int)dev->data->port_id, (int)queue_idx);
1264 return -(EINVAL);
1265 }
1266
1267 /* Free memory prior to re-allocation if needed... */
1268 if (dev->data->tx_queues[queue_idx] != NULL) {
1269 em_tx_queue_release(dev->data->tx_queues[queue_idx]);
1270 dev->data->tx_queues[queue_idx] = NULL;
1271 }
1272
1273 /*
1274 * Allocate TX ring hardware descriptors. A memzone large enough to
1275 * handle the maximum ring size is allocated in order to allow for
1276 * resizing in later calls to the queue setup function.
1277 */
1278 tsize = sizeof(txq->tx_ring[0]) * E1000_MAX_RING_DESC;
1279 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx, tsize,
1280 RTE_CACHE_LINE_SIZE, socket_id);
1281 if (tz == NULL)
1282 return -ENOMEM;
1283
1284 /* Allocate the tx queue data structure. */
1285 if ((txq = rte_zmalloc("ethdev TX queue", sizeof(*txq),
1286 RTE_CACHE_LINE_SIZE)) == NULL)
1287 return -ENOMEM;
1288
1289 /* Allocate software ring */
1290 if ((txq->sw_ring = rte_zmalloc("txq->sw_ring",
1291 sizeof(txq->sw_ring[0]) * nb_desc,
1292 RTE_CACHE_LINE_SIZE)) == NULL) {
1293 em_tx_queue_release(txq);
1294 return -ENOMEM;
1295 }
1296
1297 txq->nb_tx_desc = nb_desc;
1298 txq->tx_free_thresh = tx_free_thresh;
1299 txq->tx_rs_thresh = tx_rs_thresh;
1300 txq->pthresh = tx_conf->tx_thresh.pthresh;
1301 txq->hthresh = tx_conf->tx_thresh.hthresh;
1302 txq->wthresh = tx_conf->tx_thresh.wthresh;
1303 txq->queue_id = queue_idx;
1304 txq->port_id = dev->data->port_id;
1305
1306 txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(queue_idx));
1307 txq->tx_ring_phys_addr = tz->iova;
1308 txq->tx_ring = (struct e1000_data_desc *) tz->addr;
1309
1310 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1311 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1312
1313 em_reset_tx_queue(txq);
1314
1315 dev->data->tx_queues[queue_idx] = txq;
1316 txq->offloads = offloads;
1317 return 0;
1318 }
1319
1320 static void
em_rx_queue_release_mbufs(struct em_rx_queue * rxq)1321 em_rx_queue_release_mbufs(struct em_rx_queue *rxq)
1322 {
1323 unsigned i;
1324
1325 if (rxq->sw_ring != NULL) {
1326 for (i = 0; i != rxq->nb_rx_desc; i++) {
1327 if (rxq->sw_ring[i].mbuf != NULL) {
1328 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1329 rxq->sw_ring[i].mbuf = NULL;
1330 }
1331 }
1332 }
1333 }
1334
1335 static void
em_rx_queue_release(struct em_rx_queue * rxq)1336 em_rx_queue_release(struct em_rx_queue *rxq)
1337 {
1338 if (rxq != NULL) {
1339 em_rx_queue_release_mbufs(rxq);
1340 rte_free(rxq->sw_ring);
1341 rte_free(rxq);
1342 }
1343 }
1344
1345 void
eth_em_rx_queue_release(void * rxq)1346 eth_em_rx_queue_release(void *rxq)
1347 {
1348 em_rx_queue_release(rxq);
1349 }
1350
1351 /* Reset dynamic em_rx_queue fields back to defaults */
1352 static void
em_reset_rx_queue(struct em_rx_queue * rxq)1353 em_reset_rx_queue(struct em_rx_queue *rxq)
1354 {
1355 rxq->rx_tail = 0;
1356 rxq->nb_rx_hold = 0;
1357 rxq->pkt_first_seg = NULL;
1358 rxq->pkt_last_seg = NULL;
1359 }
1360
1361 uint64_t
em_get_rx_port_offloads_capa(struct rte_eth_dev * dev)1362 em_get_rx_port_offloads_capa(struct rte_eth_dev *dev)
1363 {
1364 uint64_t rx_offload_capa;
1365 uint32_t max_rx_pktlen;
1366
1367 max_rx_pktlen = em_get_max_pktlen(dev);
1368
1369 rx_offload_capa =
1370 DEV_RX_OFFLOAD_VLAN_STRIP |
1371 DEV_RX_OFFLOAD_VLAN_FILTER |
1372 DEV_RX_OFFLOAD_IPV4_CKSUM |
1373 DEV_RX_OFFLOAD_UDP_CKSUM |
1374 DEV_RX_OFFLOAD_TCP_CKSUM |
1375 DEV_RX_OFFLOAD_KEEP_CRC |
1376 DEV_RX_OFFLOAD_SCATTER;
1377 if (max_rx_pktlen > RTE_ETHER_MAX_LEN)
1378 rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1379
1380 return rx_offload_capa;
1381 }
1382
1383 uint64_t
em_get_rx_queue_offloads_capa(struct rte_eth_dev * dev)1384 em_get_rx_queue_offloads_capa(struct rte_eth_dev *dev)
1385 {
1386 uint64_t rx_queue_offload_capa;
1387
1388 /*
1389 * As only one Rx queue can be used, let per queue offloading
1390 * capability be same to per port queue offloading capability
1391 * for better convenience.
1392 */
1393 rx_queue_offload_capa = em_get_rx_port_offloads_capa(dev);
1394
1395 return rx_queue_offload_capa;
1396 }
1397
1398 int
eth_em_rx_queue_setup(struct rte_eth_dev * dev,uint16_t queue_idx,uint16_t nb_desc,unsigned int socket_id,const struct rte_eth_rxconf * rx_conf,struct rte_mempool * mp)1399 eth_em_rx_queue_setup(struct rte_eth_dev *dev,
1400 uint16_t queue_idx,
1401 uint16_t nb_desc,
1402 unsigned int socket_id,
1403 const struct rte_eth_rxconf *rx_conf,
1404 struct rte_mempool *mp)
1405 {
1406 const struct rte_memzone *rz;
1407 struct em_rx_queue *rxq;
1408 struct e1000_hw *hw;
1409 uint32_t rsize;
1410 uint64_t offloads;
1411
1412 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1413
1414 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1415
1416 /*
1417 * Validate number of receive descriptors.
1418 * It must not exceed hardware maximum, and must be multiple
1419 * of E1000_ALIGN.
1420 */
1421 if (nb_desc % EM_RXD_ALIGN != 0 ||
1422 (nb_desc > E1000_MAX_RING_DESC) ||
1423 (nb_desc < E1000_MIN_RING_DESC)) {
1424 return -EINVAL;
1425 }
1426
1427 /*
1428 * EM devices don't support drop_en functionality.
1429 * It's an optimization that does nothing on single-queue devices,
1430 * so just log the issue and carry on.
1431 */
1432 if (rx_conf->rx_drop_en) {
1433 PMD_INIT_LOG(NOTICE, "drop_en functionality not supported by "
1434 "device");
1435 }
1436
1437 /* Free memory prior to re-allocation if needed. */
1438 if (dev->data->rx_queues[queue_idx] != NULL) {
1439 em_rx_queue_release(dev->data->rx_queues[queue_idx]);
1440 dev->data->rx_queues[queue_idx] = NULL;
1441 }
1442
1443 /* Allocate RX ring for max possible mumber of hardware descriptors. */
1444 rsize = sizeof(rxq->rx_ring[0]) * E1000_MAX_RING_DESC;
1445 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, rsize,
1446 RTE_CACHE_LINE_SIZE, socket_id);
1447 if (rz == NULL)
1448 return -ENOMEM;
1449
1450 /* Allocate the RX queue data structure. */
1451 if ((rxq = rte_zmalloc("ethdev RX queue", sizeof(*rxq),
1452 RTE_CACHE_LINE_SIZE)) == NULL)
1453 return -ENOMEM;
1454
1455 /* Allocate software ring. */
1456 if ((rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1457 sizeof (rxq->sw_ring[0]) * nb_desc,
1458 RTE_CACHE_LINE_SIZE)) == NULL) {
1459 em_rx_queue_release(rxq);
1460 return -ENOMEM;
1461 }
1462
1463 rxq->mb_pool = mp;
1464 rxq->nb_rx_desc = nb_desc;
1465 rxq->pthresh = rx_conf->rx_thresh.pthresh;
1466 rxq->hthresh = rx_conf->rx_thresh.hthresh;
1467 rxq->wthresh = rx_conf->rx_thresh.wthresh;
1468 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1469 rxq->queue_id = queue_idx;
1470 rxq->port_id = dev->data->port_id;
1471 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1472 rxq->crc_len = RTE_ETHER_CRC_LEN;
1473 else
1474 rxq->crc_len = 0;
1475
1476 rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(queue_idx));
1477 rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(queue_idx));
1478 rxq->rx_ring_phys_addr = rz->iova;
1479 rxq->rx_ring = (struct e1000_rx_desc *) rz->addr;
1480
1481 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1482 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1483
1484 dev->data->rx_queues[queue_idx] = rxq;
1485 em_reset_rx_queue(rxq);
1486 rxq->offloads = offloads;
1487
1488 return 0;
1489 }
1490
1491 uint32_t
eth_em_rx_queue_count(struct rte_eth_dev * dev,uint16_t rx_queue_id)1492 eth_em_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1493 {
1494 #define EM_RXQ_SCAN_INTERVAL 4
1495 volatile struct e1000_rx_desc *rxdp;
1496 struct em_rx_queue *rxq;
1497 uint32_t desc = 0;
1498
1499 rxq = dev->data->rx_queues[rx_queue_id];
1500 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1501
1502 while ((desc < rxq->nb_rx_desc) &&
1503 (rxdp->status & E1000_RXD_STAT_DD)) {
1504 desc += EM_RXQ_SCAN_INTERVAL;
1505 rxdp += EM_RXQ_SCAN_INTERVAL;
1506 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1507 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1508 desc - rxq->nb_rx_desc]);
1509 }
1510
1511 return desc;
1512 }
1513
1514 int
eth_em_rx_descriptor_done(void * rx_queue,uint16_t offset)1515 eth_em_rx_descriptor_done(void *rx_queue, uint16_t offset)
1516 {
1517 volatile struct e1000_rx_desc *rxdp;
1518 struct em_rx_queue *rxq = rx_queue;
1519 uint32_t desc;
1520
1521 if (unlikely(offset >= rxq->nb_rx_desc))
1522 return 0;
1523 desc = rxq->rx_tail + offset;
1524 if (desc >= rxq->nb_rx_desc)
1525 desc -= rxq->nb_rx_desc;
1526
1527 rxdp = &rxq->rx_ring[desc];
1528 return !!(rxdp->status & E1000_RXD_STAT_DD);
1529 }
1530
1531 int
eth_em_rx_descriptor_status(void * rx_queue,uint16_t offset)1532 eth_em_rx_descriptor_status(void *rx_queue, uint16_t offset)
1533 {
1534 struct em_rx_queue *rxq = rx_queue;
1535 volatile uint8_t *status;
1536 uint32_t desc;
1537
1538 if (unlikely(offset >= rxq->nb_rx_desc))
1539 return -EINVAL;
1540
1541 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1542 return RTE_ETH_RX_DESC_UNAVAIL;
1543
1544 desc = rxq->rx_tail + offset;
1545 if (desc >= rxq->nb_rx_desc)
1546 desc -= rxq->nb_rx_desc;
1547
1548 status = &rxq->rx_ring[desc].status;
1549 if (*status & E1000_RXD_STAT_DD)
1550 return RTE_ETH_RX_DESC_DONE;
1551
1552 return RTE_ETH_RX_DESC_AVAIL;
1553 }
1554
1555 int
eth_em_tx_descriptor_status(void * tx_queue,uint16_t offset)1556 eth_em_tx_descriptor_status(void *tx_queue, uint16_t offset)
1557 {
1558 struct em_tx_queue *txq = tx_queue;
1559 volatile uint8_t *status;
1560 uint32_t desc;
1561
1562 if (unlikely(offset >= txq->nb_tx_desc))
1563 return -EINVAL;
1564
1565 desc = txq->tx_tail + offset;
1566 /* go to next desc that has the RS bit */
1567 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1568 txq->tx_rs_thresh;
1569 if (desc >= txq->nb_tx_desc) {
1570 desc -= txq->nb_tx_desc;
1571 if (desc >= txq->nb_tx_desc)
1572 desc -= txq->nb_tx_desc;
1573 }
1574
1575 status = &txq->tx_ring[desc].upper.fields.status;
1576 if (*status & E1000_TXD_STAT_DD)
1577 return RTE_ETH_TX_DESC_DONE;
1578
1579 return RTE_ETH_TX_DESC_FULL;
1580 }
1581
1582 void
em_dev_clear_queues(struct rte_eth_dev * dev)1583 em_dev_clear_queues(struct rte_eth_dev *dev)
1584 {
1585 uint16_t i;
1586 struct em_tx_queue *txq;
1587 struct em_rx_queue *rxq;
1588
1589 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1590 txq = dev->data->tx_queues[i];
1591 if (txq != NULL) {
1592 em_tx_queue_release_mbufs(txq);
1593 em_reset_tx_queue(txq);
1594 }
1595 }
1596
1597 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1598 rxq = dev->data->rx_queues[i];
1599 if (rxq != NULL) {
1600 em_rx_queue_release_mbufs(rxq);
1601 em_reset_rx_queue(rxq);
1602 }
1603 }
1604 }
1605
1606 void
em_dev_free_queues(struct rte_eth_dev * dev)1607 em_dev_free_queues(struct rte_eth_dev *dev)
1608 {
1609 uint16_t i;
1610
1611 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1612 eth_em_rx_queue_release(dev->data->rx_queues[i]);
1613 dev->data->rx_queues[i] = NULL;
1614 rte_eth_dma_zone_free(dev, "rx_ring", i);
1615 }
1616 dev->data->nb_rx_queues = 0;
1617
1618 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1619 eth_em_tx_queue_release(dev->data->tx_queues[i]);
1620 dev->data->tx_queues[i] = NULL;
1621 rte_eth_dma_zone_free(dev, "tx_ring", i);
1622 }
1623 dev->data->nb_tx_queues = 0;
1624 }
1625
1626 /*
1627 * Takes as input/output parameter RX buffer size.
1628 * Returns (BSIZE | BSEX | FLXBUF) fields of RCTL register.
1629 */
1630 static uint32_t
em_rctl_bsize(__rte_unused enum e1000_mac_type hwtyp,uint32_t * bufsz)1631 em_rctl_bsize(__rte_unused enum e1000_mac_type hwtyp, uint32_t *bufsz)
1632 {
1633 /*
1634 * For BSIZE & BSEX all configurable sizes are:
1635 * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);
1636 * 8192: rctl |= (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX);
1637 * 4096: rctl |= (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX);
1638 * 2048: rctl |= E1000_RCTL_SZ_2048;
1639 * 1024: rctl |= E1000_RCTL_SZ_1024;
1640 * 512: rctl |= E1000_RCTL_SZ_512;
1641 * 256: rctl |= E1000_RCTL_SZ_256;
1642 */
1643 static const struct {
1644 uint32_t bufsz;
1645 uint32_t rctl;
1646 } bufsz_to_rctl[] = {
1647 {16384, (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX)},
1648 {8192, (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX)},
1649 {4096, (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX)},
1650 {2048, E1000_RCTL_SZ_2048},
1651 {1024, E1000_RCTL_SZ_1024},
1652 {512, E1000_RCTL_SZ_512},
1653 {256, E1000_RCTL_SZ_256},
1654 };
1655
1656 int i;
1657 uint32_t rctl_bsize;
1658
1659 rctl_bsize = *bufsz;
1660
1661 /*
1662 * Starting from 82571 it is possible to specify RX buffer size
1663 * by RCTL.FLXBUF. When this field is different from zero, the
1664 * RX buffer size = RCTL.FLXBUF * 1K
1665 * (e.g. t is possible to specify RX buffer size 1,2,...,15KB).
1666 * It is working ok on real HW, but by some reason doesn't work
1667 * on VMware emulated 82574L.
1668 * So for now, always use BSIZE/BSEX to setup RX buffer size.
1669 * If you don't plan to use it on VMware emulated 82574L and
1670 * would like to specify RX buffer size in 1K granularity,
1671 * uncomment the following lines:
1672 * ***************************************************************
1673 * if (hwtyp >= e1000_82571 && hwtyp <= e1000_82574 &&
1674 * rctl_bsize >= EM_RCTL_FLXBUF_STEP) {
1675 * rctl_bsize /= EM_RCTL_FLXBUF_STEP;
1676 * *bufsz = rctl_bsize;
1677 * return (rctl_bsize << E1000_RCTL_FLXBUF_SHIFT &
1678 * E1000_RCTL_FLXBUF_MASK);
1679 * }
1680 * ***************************************************************
1681 */
1682
1683 for (i = 0; i != sizeof(bufsz_to_rctl) / sizeof(bufsz_to_rctl[0]);
1684 i++) {
1685 if (rctl_bsize >= bufsz_to_rctl[i].bufsz) {
1686 *bufsz = bufsz_to_rctl[i].bufsz;
1687 return bufsz_to_rctl[i].rctl;
1688 }
1689 }
1690
1691 /* Should never happen. */
1692 return -EINVAL;
1693 }
1694
1695 static int
em_alloc_rx_queue_mbufs(struct em_rx_queue * rxq)1696 em_alloc_rx_queue_mbufs(struct em_rx_queue *rxq)
1697 {
1698 struct em_rx_entry *rxe = rxq->sw_ring;
1699 uint64_t dma_addr;
1700 unsigned i;
1701 static const struct e1000_rx_desc rxd_init = {
1702 .buffer_addr = 0,
1703 };
1704
1705 /* Initialize software ring entries */
1706 for (i = 0; i < rxq->nb_rx_desc; i++) {
1707 volatile struct e1000_rx_desc *rxd;
1708 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
1709
1710 if (mbuf == NULL) {
1711 PMD_INIT_LOG(ERR, "RX mbuf alloc failed "
1712 "queue_id=%hu", rxq->queue_id);
1713 return -ENOMEM;
1714 }
1715
1716 dma_addr =
1717 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
1718
1719 /* Clear HW ring memory */
1720 rxq->rx_ring[i] = rxd_init;
1721
1722 rxd = &rxq->rx_ring[i];
1723 rxd->buffer_addr = dma_addr;
1724 rxe[i].mbuf = mbuf;
1725 }
1726
1727 return 0;
1728 }
1729
1730 /*********************************************************************
1731 *
1732 * Enable receive unit.
1733 *
1734 **********************************************************************/
1735 int
eth_em_rx_init(struct rte_eth_dev * dev)1736 eth_em_rx_init(struct rte_eth_dev *dev)
1737 {
1738 struct e1000_hw *hw;
1739 struct em_rx_queue *rxq;
1740 struct rte_eth_rxmode *rxmode;
1741 uint32_t rctl;
1742 uint32_t rfctl;
1743 uint32_t rxcsum;
1744 uint32_t rctl_bsize;
1745 uint16_t i;
1746 int ret;
1747
1748 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1749 rxmode = &dev->data->dev_conf.rxmode;
1750
1751 /*
1752 * Make sure receives are disabled while setting
1753 * up the descriptor ring.
1754 */
1755 rctl = E1000_READ_REG(hw, E1000_RCTL);
1756 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
1757
1758 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
1759
1760 /* Disable extended descriptor type. */
1761 rfctl &= ~E1000_RFCTL_EXTEN;
1762 /* Disable accelerated acknowledge */
1763 if (hw->mac.type == e1000_82574)
1764 rfctl |= E1000_RFCTL_ACK_DIS;
1765
1766 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
1767
1768 /*
1769 * XXX TEMPORARY WORKAROUND: on some systems with 82573
1770 * long latencies are observed, like Lenovo X60. This
1771 * change eliminates the problem, but since having positive
1772 * values in RDTR is a known source of problems on other
1773 * platforms another solution is being sought.
1774 */
1775 if (hw->mac.type == e1000_82573)
1776 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
1777
1778 dev->rx_pkt_burst = (eth_rx_burst_t)eth_em_recv_pkts;
1779
1780 /* Determine RX bufsize. */
1781 rctl_bsize = EM_MAX_BUF_SIZE;
1782 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1783 uint32_t buf_size;
1784
1785 rxq = dev->data->rx_queues[i];
1786 buf_size = rte_pktmbuf_data_room_size(rxq->mb_pool) -
1787 RTE_PKTMBUF_HEADROOM;
1788 rctl_bsize = RTE_MIN(rctl_bsize, buf_size);
1789 }
1790
1791 rctl |= em_rctl_bsize(hw->mac.type, &rctl_bsize);
1792
1793 /* Configure and enable each RX queue. */
1794 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1795 uint64_t bus_addr;
1796 uint32_t rxdctl;
1797
1798 rxq = dev->data->rx_queues[i];
1799
1800 /* Allocate buffers for descriptor rings and setup queue */
1801 ret = em_alloc_rx_queue_mbufs(rxq);
1802 if (ret)
1803 return ret;
1804
1805 /*
1806 * Reset crc_len in case it was changed after queue setup by a
1807 * call to configure
1808 */
1809 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1810 rxq->crc_len = RTE_ETHER_CRC_LEN;
1811 else
1812 rxq->crc_len = 0;
1813
1814 bus_addr = rxq->rx_ring_phys_addr;
1815 E1000_WRITE_REG(hw, E1000_RDLEN(i),
1816 rxq->nb_rx_desc *
1817 sizeof(*rxq->rx_ring));
1818 E1000_WRITE_REG(hw, E1000_RDBAH(i),
1819 (uint32_t)(bus_addr >> 32));
1820 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
1821
1822 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
1823 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
1824
1825 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
1826 rxdctl &= 0xFE000000;
1827 rxdctl |= rxq->pthresh & 0x3F;
1828 rxdctl |= (rxq->hthresh & 0x3F) << 8;
1829 rxdctl |= (rxq->wthresh & 0x3F) << 16;
1830 rxdctl |= E1000_RXDCTL_GRAN;
1831 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
1832
1833 /*
1834 * Due to EM devices not having any sort of hardware
1835 * limit for packet length, jumbo frame of any size
1836 * can be accepted, thus we have to enable scattered
1837 * rx if jumbo frames are enabled (or if buffer size
1838 * is too small to accommodate non-jumbo packets)
1839 * to avoid splitting packets that don't fit into
1840 * one buffer.
1841 */
1842 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME ||
1843 rctl_bsize < RTE_ETHER_MAX_LEN) {
1844 if (!dev->data->scattered_rx)
1845 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
1846 dev->rx_pkt_burst =
1847 (eth_rx_burst_t)eth_em_recv_scattered_pkts;
1848 dev->data->scattered_rx = 1;
1849 }
1850 }
1851
1852 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) {
1853 if (!dev->data->scattered_rx)
1854 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
1855 dev->rx_pkt_burst = eth_em_recv_scattered_pkts;
1856 dev->data->scattered_rx = 1;
1857 }
1858
1859 /*
1860 * Setup the Checksum Register.
1861 * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
1862 */
1863 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
1864
1865 if (rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM)
1866 rxcsum |= E1000_RXCSUM_IPOFL;
1867 else
1868 rxcsum &= ~E1000_RXCSUM_IPOFL;
1869 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
1870
1871 /* No MRQ or RSS support for now */
1872
1873 /* Set early receive threshold on appropriate hw */
1874 if ((hw->mac.type == e1000_ich9lan ||
1875 hw->mac.type == e1000_pch2lan ||
1876 hw->mac.type == e1000_ich10lan) &&
1877 rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1878 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
1879 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
1880 E1000_WRITE_REG(hw, E1000_ERT, 0x100 | (1 << 13));
1881 }
1882
1883 if (hw->mac.type == e1000_pch2lan) {
1884 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1885 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
1886 else
1887 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
1888 }
1889
1890 /* Setup the Receive Control Register. */
1891 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1892 rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
1893 else
1894 rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */
1895
1896 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1897 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
1898 E1000_RCTL_RDMTS_HALF |
1899 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1900
1901 /* Make sure VLAN Filters are off. */
1902 rctl &= ~E1000_RCTL_VFE;
1903 /* Don't store bad packets. */
1904 rctl &= ~E1000_RCTL_SBP;
1905 /* Legacy descriptor type. */
1906 rctl &= ~E1000_RCTL_DTYP_MASK;
1907
1908 /*
1909 * Configure support of jumbo frames, if any.
1910 */
1911 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1912 rctl |= E1000_RCTL_LPE;
1913 else
1914 rctl &= ~E1000_RCTL_LPE;
1915
1916 /* Enable Receives. */
1917 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1918
1919 return 0;
1920 }
1921
1922 /*********************************************************************
1923 *
1924 * Enable transmit unit.
1925 *
1926 **********************************************************************/
1927 void
eth_em_tx_init(struct rte_eth_dev * dev)1928 eth_em_tx_init(struct rte_eth_dev *dev)
1929 {
1930 struct e1000_hw *hw;
1931 struct em_tx_queue *txq;
1932 uint32_t tctl;
1933 uint32_t txdctl;
1934 uint16_t i;
1935
1936 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1937
1938 /* Setup the Base and Length of the Tx Descriptor Rings. */
1939 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1940 uint64_t bus_addr;
1941
1942 txq = dev->data->tx_queues[i];
1943 bus_addr = txq->tx_ring_phys_addr;
1944 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1945 txq->nb_tx_desc *
1946 sizeof(*txq->tx_ring));
1947 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1948 (uint32_t)(bus_addr >> 32));
1949 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
1950
1951 /* Setup the HW Tx Head and Tail descriptor pointers. */
1952 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1953 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1954
1955 /* Setup Transmit threshold registers. */
1956 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
1957 /*
1958 * bit 22 is reserved, on some models should always be 0,
1959 * on others - always 1.
1960 */
1961 txdctl &= E1000_TXDCTL_COUNT_DESC;
1962 txdctl |= txq->pthresh & 0x3F;
1963 txdctl |= (txq->hthresh & 0x3F) << 8;
1964 txdctl |= (txq->wthresh & 0x3F) << 16;
1965 txdctl |= E1000_TXDCTL_GRAN;
1966 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1967 }
1968
1969 /* Program the Transmit Control Register. */
1970 tctl = E1000_READ_REG(hw, E1000_TCTL);
1971 tctl &= ~E1000_TCTL_CT;
1972 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1973 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1974
1975 /* SPT and CNP Si errata workaround to avoid data corruption */
1976 if (hw->mac.type == e1000_pch_spt) {
1977 uint32_t reg_val;
1978 reg_val = E1000_READ_REG(hw, E1000_IOSFPC);
1979 reg_val |= E1000_RCTL_RDMTS_HEX;
1980 E1000_WRITE_REG(hw, E1000_IOSFPC, reg_val);
1981
1982 /* Dropping the number of outstanding requests from
1983 * 3 to 2 in order to avoid a buffer overrun.
1984 */
1985 reg_val = E1000_READ_REG(hw, E1000_TARC(0));
1986 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
1987 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
1988 E1000_WRITE_REG(hw, E1000_TARC(0), reg_val);
1989 }
1990
1991 /* This write will effectively turn on the transmit unit. */
1992 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1993 }
1994
1995 void
em_rxq_info_get(struct rte_eth_dev * dev,uint16_t queue_id,struct rte_eth_rxq_info * qinfo)1996 em_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1997 struct rte_eth_rxq_info *qinfo)
1998 {
1999 struct em_rx_queue *rxq;
2000
2001 rxq = dev->data->rx_queues[queue_id];
2002
2003 qinfo->mp = rxq->mb_pool;
2004 qinfo->scattered_rx = dev->data->scattered_rx;
2005 qinfo->nb_desc = rxq->nb_rx_desc;
2006 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2007 qinfo->conf.offloads = rxq->offloads;
2008 }
2009
2010 void
em_txq_info_get(struct rte_eth_dev * dev,uint16_t queue_id,struct rte_eth_txq_info * qinfo)2011 em_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2012 struct rte_eth_txq_info *qinfo)
2013 {
2014 struct em_tx_queue *txq;
2015
2016 txq = dev->data->tx_queues[queue_id];
2017
2018 qinfo->nb_desc = txq->nb_tx_desc;
2019
2020 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2021 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2022 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2023 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2024 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2025 qinfo->conf.offloads = txq->offloads;
2026 }
2027
2028 static void
e1000_flush_tx_ring(struct rte_eth_dev * dev)2029 e1000_flush_tx_ring(struct rte_eth_dev *dev)
2030 {
2031 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2032 volatile struct e1000_data_desc *tx_desc;
2033 volatile uint32_t *tdt_reg_addr;
2034 uint32_t tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
2035 uint16_t size = 512;
2036 struct em_tx_queue *txq;
2037 int i;
2038
2039 if (dev->data->tx_queues == NULL)
2040 return;
2041 tctl = E1000_READ_REG(hw, E1000_TCTL);
2042 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN);
2043 for (i = 0; i < dev->data->nb_tx_queues &&
2044 i < E1000_I219_MAX_TX_QUEUE_NUM; i++) {
2045 txq = dev->data->tx_queues[i];
2046 tdt = E1000_READ_REG(hw, E1000_TDT(i));
2047 if (tdt != txq->tx_tail)
2048 return;
2049 tx_desc = &txq->tx_ring[txq->tx_tail];
2050 tx_desc->buffer_addr = rte_cpu_to_le_64(txq->tx_ring_phys_addr);
2051 tx_desc->lower.data = rte_cpu_to_le_32(txd_lower | size);
2052 tx_desc->upper.data = 0;
2053
2054 rte_io_wmb();
2055 txq->tx_tail++;
2056 if (txq->tx_tail == txq->nb_tx_desc)
2057 txq->tx_tail = 0;
2058 tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(i));
2059 E1000_PCI_REG_WRITE(tdt_reg_addr, txq->tx_tail);
2060 usec_delay(250);
2061 }
2062 }
2063
2064 static void
e1000_flush_rx_ring(struct rte_eth_dev * dev)2065 e1000_flush_rx_ring(struct rte_eth_dev *dev)
2066 {
2067 uint32_t rctl, rxdctl;
2068 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2069 int i;
2070
2071 rctl = E1000_READ_REG(hw, E1000_RCTL);
2072 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2073 E1000_WRITE_FLUSH(hw);
2074 usec_delay(150);
2075
2076 for (i = 0; i < dev->data->nb_rx_queues &&
2077 i < E1000_I219_MAX_RX_QUEUE_NUM; i++) {
2078 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2079 /* zero the lower 14 bits (prefetch and host thresholds) */
2080 rxdctl &= 0xffffc000;
2081
2082 /* update thresholds: prefetch threshold to 31,
2083 * host threshold to 1 and make sure the granularity
2084 * is "descriptors" and not "cache lines"
2085 */
2086 rxdctl |= (0x1F | (1UL << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);
2087
2088 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2089 }
2090 /* momentarily enable the RX ring for the changes to take effect */
2091 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN);
2092 E1000_WRITE_FLUSH(hw);
2093 usec_delay(150);
2094 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2095 }
2096
2097 /**
2098 * em_flush_desc_rings - remove all descriptors from the descriptor rings
2099 *
2100 * In i219, the descriptor rings must be emptied before resetting/closing the
2101 * HW. Failure to do this will cause the HW to enter a unit hang state which
2102 * can only be released by PCI reset on the device
2103 *
2104 */
2105
2106 void
em_flush_desc_rings(struct rte_eth_dev * dev)2107 em_flush_desc_rings(struct rte_eth_dev *dev)
2108 {
2109 uint32_t fextnvm11, tdlen;
2110 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2111 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2112 uint16_t pci_cfg_status = 0;
2113 int ret;
2114
2115 fextnvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);
2116 E1000_WRITE_REG(hw, E1000_FEXTNVM11,
2117 fextnvm11 | E1000_FEXTNVM11_DISABLE_MULR_FIX);
2118 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0));
2119 ret = rte_pci_read_config(pci_dev, &pci_cfg_status,
2120 sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
2121 if (ret < 0) {
2122 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
2123 PCI_CFG_STATUS_REG);
2124 return;
2125 }
2126
2127 /* do nothing if we're not in faulty state, or if the queue is empty */
2128 if ((pci_cfg_status & FLUSH_DESC_REQUIRED) && tdlen) {
2129 /* flush desc ring */
2130 e1000_flush_tx_ring(dev);
2131 ret = rte_pci_read_config(pci_dev, &pci_cfg_status,
2132 sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
2133 if (ret < 0) {
2134 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
2135 PCI_CFG_STATUS_REG);
2136 return;
2137 }
2138
2139 if (pci_cfg_status & FLUSH_DESC_REQUIRED)
2140 e1000_flush_rx_ring(dev);
2141 }
2142 }
2143