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Searched refs:hw_cap (Results 1 – 10 of 10) sorted by relevance

/f-stack/dpdk/drivers/net/ipn3ke/
H A Dipn3ke_ethdev.c141 hw->hw_cap.classy_size = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
157 hw->hw_cap.dmac_map_size = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
159 hw->hw_cap.qm_offset = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
161 hw->hw_cap.qm_size = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
163 hw->hw_cap.ccb_offset = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
167 hw->hw_cap.qos_offset = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
169 hw->hw_cap.qos_size = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
172 hw->hw_cap.num_rx_flow = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
178 hw->hw_cap.num_dmac_map = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
181 hw->hw_cap.num_tx_flow = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
[all …]
H A Dipn3ke_ethdev.h159 (IPN3KE_HW_BASE + hw->hw_cap.capability_registers_block_offset)
162 (IPN3KE_HW_BASE + hw->hw_cap.status_registers_block_offset)
165 (IPN3KE_HW_BASE + hw->hw_cap.control_registers_block_offset)
171 (IPN3KE_HW_BASE + hw->hw_cap.classify_offset)
174 (IPN3KE_HW_BASE + hw->hw_cap.policer_offset)
177 (IPN3KE_HW_BASE + hw->hw_cap.rss_key_array_offset)
183 (IPN3KE_HW_BASE + hw->hw_cap.dmac_map_offset)
186 (IPN3KE_HW_BASE + hw->hw_cap.qm_offset)
189 (IPN3KE_HW_BASE + hw->hw_cap.ccb_offset)
192 (IPN3KE_HW_BASE + hw->hw_cap.qos_offset)
[all …]
/f-stack/freebsd/x86/iommu/
H A Dintel_fault.c143 frir = (DMAR_CAP_FRO(unit->hw_cap) + fri) * 16; in dmar_fault_intr()
161 if (fri >= DMAR_CAP_NFR(unit->hw_cap)) in dmar_fault_intr()
252 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { in dmar_clear_faults()
253 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16; in dmar_clear_faults()
H A Dintel_utils.c116 if ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0) in dmar_pglvl_supported()
128 sagaw = DMAR_CAP_SAGAW(domain->dmar->hw_cap); in domain_set_agaw()
157 (DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0) in dmar_maxaddr2mgaw()
163 } while ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) in dmar_maxaddr2mgaw()
206 cap_sps = DMAR_CAP_SPS(domain->dmar->hw_cap); in domain_is_sp_lvl()
244 for (am = DMAR_CAP_MAMV(unit->hw_cap);; am--) { in calc_am()
484 KASSERT((unit->hw_cap & DMAR_CAP_RWBF) != 0, in dmar_flush_write_bufs()
H A Dintel_quirks.c155 unit->hw_cap &= ~(DMAR_CAP_PHMR | DMAR_CAP_PLMR); in nb_5400_no_low_high_prot_mem()
212 unit->hw_cap &= ~(0x3fULL << 48); in cpu_e5_am9()
213 unit->hw_cap |= (9ULL << 48); in cpu_e5_am9()
H A Dintel_drv.c383 caphi = unit->hw_cap >> 32; in dmar_print_caps()
384 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, in dmar_print_caps()
388 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), in dmar_print_caps()
389 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), in dmar_print_caps()
390 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap)); in dmar_print_caps()
391 if ((unit->hw_cap & DMAR_CAP_PSI) != 0) in dmar_print_caps()
392 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap)); in dmar_print_caps()
428 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG); in dmar_attach()
482 if ((unit->hw_cap & DMAR_CAP_CM) != 0) in dmar_attach()
1259 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { in dmar_print_one()
[all …]
H A Dintel_idpgtbl.c265 if ((unit->hw_cap & DMAR_CAP_RWBF) != 0) { in domain_get_idmap_pgtbl()
558 if ((unit->hw_cap & DMAR_CAP_CM) != 0) in domain_map_buf()
560 else if ((unit->hw_cap & DMAR_CAP_RWBF) != 0) { in domain_map_buf()
784 if ((unit->hw_cap & DMAR_CAP_PSI) == 0 || size > 2 * 1024 * 1024) { in domain_flush_iotlb_sync()
H A Dintel_qi.c377 if (!DMAR_HAS_QI(unit) || (unit->hw_cap & DMAR_CAP_CM) != 0) in dmar_init_qi()
H A Dintel_dmar.h141 uint64_t hw_cap; member
H A Dintel_ctx.c219 if ((dmar->hw_cap & DMAR_CAP_CM) == 0 && !force) in dmar_flush_for_ctx_entry()