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Searched refs:hw (Results 1 – 25 of 569) sorted by relevance

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/f-stack/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_api.c40 hw->mac.ops.get_rtrup2tc(hw, map); in ixgbe_dcb_get_rtrup2tc()
232 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), in ixgbe_init_hw()
245 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), in ixgbe_reset_hw()
261 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), in ixgbe_start_hw()
399 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), in ixgbe_get_bus_info()
436 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), in ixgbe_stop_adapter()
476 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), in ixgbe_identify_phy()
497 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), in ixgbe_reset_phy()
564 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), in ixgbe_setup_phy_link()
1038 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), in ixgbe_enable_mc()
[all …]
H A Dixgbe_phy.c504 status = hw->phy.ops.read_reg(hw, in ixgbe_reset_phy_generic()
516 status = hw->phy.ops.read_reg(hw, in ixgbe_reset_phy_generic()
983 status = hw->phy.ops.read_reg(hw, in ixgbe_check_phy_link_tnx()
1280 hw->mac.ops.set_lan_id(hw); in ixgbe_identify_sfp_module_generic()
1561 hw->phy.ops.identify_sfp(hw); in ixgbe_get_supported_phy_sfp_layer_generic()
1580 hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_get_supported_phy_sfp_layer_generic()
1582 hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_get_supported_phy_sfp_layer_generic()
1595 hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_get_supported_phy_sfp_layer_generic()
1639 hw->mac.ops.set_lan_id(hw); in ixgbe_identify_qsfp_module_generic()
1686 hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_identify_qsfp_module_generic()
[all …]
H A Dixgbe_common.c365 hw->phy.media_type = hw->mac.ops.get_media_type(hw); in ixgbe_start_hw_generic()
370 hw->mac.ops.clear_vfta(hw); in ixgbe_start_hw_generic()
373 hw->mac.ops.clear_hw_cntrs(hw); in ixgbe_start_hw_generic()
1273 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_buffer_bit_bang_generic()
1410 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_generic()
1440 hw->eeprom.ops.init_params(hw); in ixgbe_read_eeprom_buffer_bit_bang_generic()
2450 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); in ixgbe_init_rx_addrs_generic()
2466 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); in ixgbe_init_rx_addrs_generic()
2801 hw->mac.ops.fc_autoneg(hw); in ixgbe_fc_enable_generic()
3564 hw->mac.ops.set_lan_id(hw); in ixgbe_get_san_mac_addr_generic()
[all …]
H A Dixgbe_x540.c187 status = hw->mac.ops.stop_adapter(hw); in ixgbe_reset_hw_X540()
205 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in ixgbe_reset_hw_X540()
236 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); in ixgbe_reset_hw_X540()
244 hw->mac.ops.init_rx_addrs(hw); in ixgbe_reset_hw_X540()
247 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); in ixgbe_reset_hw_X540()
254 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, in ixgbe_reset_hw_X540()
258 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, in ixgbe_reset_hw_X540()
266 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, in ixgbe_reset_hw_X540()
341 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); in ixgbe_init_eeprom_params_X540()
564 status = hw->eeprom.ops.calc_checksum(hw); in ixgbe_validate_eeprom_checksum_X540()
[all …]
H A Dixgbe_api.h12 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw);
23 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw);
24 s32 ixgbe_init_hw(struct ixgbe_hw *hw);
25 s32 ixgbe_reset_hw(struct ixgbe_hw *hw);
26 s32 ixgbe_start_hw(struct ixgbe_hw *hw);
31 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw);
34 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw);
39 s32 ixgbe_reset_phy(struct ixgbe_hw *hw);
96 s32 ixgbe_enable_mc(struct ixgbe_hw *hw);
104 s32 ixgbe_fc_enable(struct ixgbe_hw *hw);
[all …]
H A Dixgbe_x550.c86 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); in ixgbe_read_cs4227()
99 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); in ixgbe_write_cs4227()
318 hw->mac.ops.set_lan_id(hw); in ixgbe_identify_phy_x550em()
747 return hw->phy.ops.setup_link(hw); in ixgbe_setup_eee_fw()
2257 hw->mac.ops.set_lan_id(hw); in ixgbe_init_phy_ops_X550em()
2426 status = hw->phy.ops.init(hw); in ixgbe_reset_hw_X550em()
2512 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); in ixgbe_reset_hw_X550em()
2519 hw->mac.ops.init_rx_addrs(hw); in ixgbe_reset_hw_X550em()
3408 hw->eeprom.ops.init_params(hw); in ixgbe_calc_checksum_X550()
3616 hw->phy.ops.identify(hw); in ixgbe_get_supported_physical_layer_X550em()
[all …]
/f-stack/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_phy.c59 hw->phy.media_type = hw->phy.get_media_type(hw); in txgbe_read_phy_if()
364 hw->mac.release_swfw_sync(hw, gssr); in txgbe_read_phy_reg()
424 hw->mac.release_swfw_sync(hw, gssr); in txgbe_write_phy_reg()
556 hw->phy.setup_link(hw); in txgbe_setup_phy_link_speed()
643 err = hw->phy.read_reg(hw, in txgbe_check_phy_link_tnx()
850 err = hw->phy.read_i2c_eeprom(hw, in txgbe_identify_sfp_module()
897 err = hw->phy.read_i2c_eeprom(hw, in txgbe_identify_sfp_module()
902 err = hw->phy.read_i2c_eeprom(hw, in txgbe_identify_sfp_module()
1053 hw->phy.read_i2c_eeprom(hw, in txgbe_identify_qsfp_module()
1057 hw->phy.read_i2c_eeprom(hw, in txgbe_identify_qsfp_module()
[all …]
H A Dtxgbe_hw.c250 hw->phy.media_type = hw->phy.get_media_type(hw); in txgbe_start_hw()
253 hw->mac.clear_vfta(hw); in txgbe_start_hw()
753 hw->mac.get_mac_addr(hw, hw->mac.addr); in txgbe_init_rx_addrs()
769 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true); in txgbe_init_rx_addrs()
971 hw->mac.fc_autoneg(hw); in txgbe_fc_enable()
3558 hw->phy.reset(hw); in txgbe_reset_hw()
3608 hw->mac.orig_autoc = hw->mac.autoc_read(hw); in txgbe_reset_hw()
3609 hw->mac.autoc_write(hw, hw->mac.orig_autoc); in txgbe_reset_hw()
3616 hw->mac.get_mac_addr(hw, hw->mac.perm_addr); in txgbe_reset_hw()
3627 hw->mac.get_san_mac_addr(hw, hw->mac.san_addr); in txgbe_reset_hw()
[all …]
/f-stack/dpdk/drivers/net/e1000/base/
H A De1000_api.c19 ret_val = hw->mac.ops.init_params(hw); in e1000_init_mac_params()
45 ret_val = hw->nvm.ops.init_params(hw); in e1000_init_nvm_params()
71 ret_val = hw->phy.ops.init_params(hw); in e1000_init_phy_params()
530 hw->mac.ops.clear_vfta(hw); in e1000_clear_vfta()
647 return hw->mac.ops.init_hw(hw); in e1000_init_hw()
758 return hw->mac.ops.led_on(hw); in e1000_led_on()
991 hw->phy.ops.release(hw); in e1000_release_phy()
1093 return hw->phy.ops.reset(hw); in e1000_phy_hw_reset()
1259 hw->nvm.ops.reload(hw); in e1000_reload_nvm()
1324 hw->phy.ops.power_up(hw); in e1000_power_up_phy()
[all …]
H A De1000_82543.c717 if (!hw->mac.autoneg && (hw->mac.forced_speed_duplex & in e1000_phy_force_speed_duplex_82543()
768 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); in e1000_polarity_reversal_workaround_82543()
772 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); in e1000_polarity_reversal_workaround_82543()
856 ret_val = hw->phy.ops.get_cfg_done(hw); in e1000_phy_hw_reset_82543()
906 hw->nvm.ops.reload(hw); in e1000_reset_hw_82543()
1001 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); in e1000_setup_link_82543()
1044 ret_val = hw->phy.ops.reset(hw); in e1000_setup_copper_link_82543()
1092 hw->mac.ops.config_collision_dist(hw); in e1000_setup_copper_link_82543()
1126 hw->mac.ops.config_collision_dist(hw); in e1000_setup_fiber_link_82543()
1224 hw->mac.ops.config_collision_dist(hw); in e1000_check_for_copper_link_82543()
[all …]
H A De1000_ich8lan.c206 hw->phy.ops.release(hw); in e1000_phy_is_accessible_pchlan()
210 hw->phy.ops.acquire(hw); in e1000_phy_is_accessible_pchlan()
374 hw->phy.ops.release(hw); in e1000_init_phy_workarounds_pchlan()
974 hw->phy.ops.release(hw); in e1000_set_eee_pchlan()
1026 hw->phy.ops.release(hw); in e1000_k1_workaround_lpt_lp()
1229 hw->phy.ops.release(hw); in e1000_enable_ulp_lpt_lp()
1433 hw->phy.ops.release(hw); in e1000_disable_ulp_lpt_lp()
1435 hw->phy.ops.reset(hw); in e1000_disable_ulp_lpt_lp()
2114 hw->phy.ops.release(hw); in e1000_update_mc_addr_list_pch2lan()
2307 hw->phy.ops.release(hw); in e1000_sw_lcd_config_ich8lan()
[all …]
H A De1000_80003es2lan.c239 hw->mac.ops.set_lan_id(hw); in e1000_init_mac_params_80003es2lan()
657 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
666 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
696 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, in e1000_phy_force_speed_duplex_80003es2lan()
714 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, in e1000_phy_force_speed_duplex_80003es2lan()
773 hw->phy.ops.cfg_on_link_up(hw); in e1000_get_link_up_info_80003es2lan()
1073 ret_val = hw->phy.ops.commit(hw); in e1000_copper_link_setup_gg82563_80003es2lan()
1117 if (!hw->mac.ops.check_mng_mode(hw)) { in e1000_copper_link_setup_gg82563_80003es2lan()
1120 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, in e1000_copper_link_setup_gg82563_80003es2lan()
1442 if (!(hw->mac.ops.check_mng_mode(hw) || in e1000_power_down_phy_copper_80003es2lan()
[all …]
H A De1000_82571.c87 switch (hw->mac.type) { in e1000_init_phy_params_82571()
145 switch (hw->mac.type) { in e1000_init_phy_params_82571()
200 switch (hw->mac.type) { in e1000_init_nvm_params_82571()
232 switch (hw->mac.type) { in e1000_init_nvm_params_82571()
337 switch (hw->mac.type) { in e1000_init_mac_params_82571()
1435 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); in e1000_check_mng_mode_82574()
1487 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER, in e1000_check_phy_82574()
1492 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS, in e1000_check_phy_82574()
1792 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); in e1000_valid_led_default_82571()
1855 hw->mac.ops.rar_set(hw, hw->mac.addr, in e1000_set_laa_state_82571()
[all …]
H A De1000_mac.c352 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); in e1000_init_rx_addrs_generic()
357 hw->mac.ops.rar_set(hw, mac_addr, i); in e1000_init_rx_addrs_generic()
416 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); in e1000_check_alt_mac_addr_generic()
436 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); in e1000_check_alt_mac_addr_generic()
937 ret_val = hw->nvm.ops.read(hw, in e1000_set_default_fc_generic()
942 ret_val = hw->nvm.ops.read(hw, in e1000_set_default_fc_generic()
983 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) in e1000_setup_link_generic()
998 hw->fc.current_mode = hw->fc.requested_mode; in e1000_setup_link_generic()
1004 ret_val = hw->mac.ops.setup_physical_interface(hw); in e1000_setup_link_generic()
1160 hw->mac.ops.config_collision_dist(hw); in e1000_setup_fiber_serdes_link_generic()
[all …]
H A De1000_82575.c410 hw->mac.ops.set_lan_id(hw); in e1000_init_mac_params_82575()
535 ret_val = hw->phy.ops.acquire(hw); in e1000_read_phy_reg_sgmii_82575()
541 hw->phy.ops.release(hw); in e1000_read_phy_reg_sgmii_82575()
568 ret_val = hw->phy.ops.acquire(hw); in e1000_write_phy_reg_sgmii_82575()
574 hw->phy.ops.release(hw); in e1000_write_phy_reg_sgmii_82575()
714 ret_val = hw->phy.ops.commit(hw); in e1000_phy_hw_reset_sgmii_82575()
1492 ret_val = hw->phy.ops.reset(hw); in e1000_setup_copper_link_82575()
2193 ret_val = hw->phy.ops.acquire(hw); in e1000_read_phy_reg_82580()
2199 hw->phy.ops.release(hw); in e1000_read_phy_reg_82580()
2219 ret_val = hw->phy.ops.acquire(hw); in e1000_write_phy_reg_82580()
[all …]
H A De1000_82540.c400 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, in e1000_setup_copper_link_82540()
405 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, in e1000_setup_copper_link_82540()
476 ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data); in e1000_adjust_serdes_amplitude_82540()
483 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL, in e1000_adjust_serdes_amplitude_82540()
509 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT, in e1000_set_vco_speed_82540()
542 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, in e1000_set_vco_speed_82540()
568 ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data); in e1000_set_phy_mode_82540()
575 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, in e1000_set_phy_mode_82540()
581 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, in e1000_set_phy_mode_82540()
670 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); in e1000_read_mac_addr_82540()
[all …]
H A De1000_api.h24 s32 e1000_set_mac_type(struct e1000_hw *hw);
30 s32 e1000_get_bus_info(struct e1000_hw *hw);
31 void e1000_clear_vfta(struct e1000_hw *hw);
35 s32 e1000_reset_hw(struct e1000_hw *hw);
36 s32 e1000_init_hw(struct e1000_hw *hw);
37 s32 e1000_setup_link(struct e1000_hw *hw);
45 s32 e1000_setup_led(struct e1000_hw *hw);
48 s32 e1000_blink_led(struct e1000_hw *hw);
49 s32 e1000_led_on(struct e1000_hw *hw);
50 s32 e1000_led_off(struct e1000_hw *hw);
[all …]
/f-stack/dpdk/drivers/net/igc/base/
H A Digc_api.c1011 hw->mac.ops.clear_vfta(hw); in igc_clear_vfta()
1128 return hw->mac.ops.init_hw(hw); in igc_init_hw()
1239 return hw->mac.ops.led_on(hw); in igc_led_on()
1254 return hw->mac.ops.led_off(hw); in igc_led_off()
1472 hw->phy.ops.release(hw); in igc_release_phy()
1574 return hw->phy.ops.reset(hw); in igc_phy_hw_reset()
1589 return hw->phy.ops.commit(hw); in igc_phy_commit()
1725 return hw->nvm.ops.update(hw); in igc_update_nvm_checksum()
1740 hw->nvm.ops.reload(hw); in igc_reload_nvm()
1805 hw->phy.ops.power_up(hw); in igc_power_up_phy()
[all …]
H A Digc_mac.c350 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); in igc_init_rx_addrs_generic()
355 hw->mac.ops.rar_set(hw, mac_addr, i); in igc_init_rx_addrs_generic()
434 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); in igc_check_alt_mac_addr_generic()
935 ret_val = hw->nvm.ops.read(hw, in igc_set_default_fc_generic()
940 ret_val = hw->nvm.ops.read(hw, in igc_set_default_fc_generic()
980 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) in igc_setup_link_generic()
992 hw->fc.current_mode = hw->fc.requested_mode; in igc_setup_link_generic()
998 ret_val = hw->mac.ops.setup_physical_interface(hw); in igc_setup_link_generic()
1012 IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time); in igc_setup_link_generic()
1153 hw->mac.ops.config_collision_dist(hw); in igc_setup_fiber_serdes_link_generic()
[all …]
H A Digc_api.h22 s32 igc_set_i2c_bb(struct igc_hw *hw);
27 void igc_i2c_bus_clear(struct igc_hw *hw);
51 void igc_clear_vfta(struct igc_hw *hw);
55 s32 igc_reset_hw(struct igc_hw *hw);
56 s32 igc_init_hw(struct igc_hw *hw);
57 s32 igc_setup_link(struct igc_hw *hw);
65 s32 igc_setup_led(struct igc_hw *hw);
68 s32 igc_blink_led(struct igc_hw *hw);
69 s32 igc_led_on(struct igc_hw *hw);
70 s32 igc_led_off(struct igc_hw *hw);
[all …]
/f-stack/dpdk/drivers/net/i40e/base/
H A Di40e_adminq.c277 wr32(hw, hw->aq.asq.head, 0); in i40e_config_asq_regs()
284 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
287 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
294 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
297 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
331 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
334 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
341 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
344 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
352 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); in i40e_config_arq_regs()
[all …]
/f-stack/dpdk/drivers/net/fm10k/base/
H A Dfm10k_api.c102 return fm10k_call_func(hw, hw->mac.ops.reset_hw, (hw), in fm10k_reset_hw()
114 return fm10k_call_func(hw, hw->mac.ops.init_hw, (hw), in fm10k_init_hw()
126 return fm10k_call_func(hw, hw->mac.ops.stop_hw, (hw), in fm10k_stop_hw()
139 return fm10k_call_func(hw, hw->mac.ops.start_hw, (hw), in fm10k_start_hw()
151 return fm10k_call_func(hw, hw->mac.ops.get_bus_info, (hw), in fm10k_get_bus_info()
166 return hw->mac.ops.is_slot_appropriate(hw); in fm10k_is_slot_appropriate()
183 return fm10k_call_func(hw, hw->mac.ops.update_vlan, (hw, vid, idx, set), in fm10k_update_vlan()
196 return fm10k_call_func(hw, hw->mac.ops.read_mac_addr, (hw), in fm10k_read_mac_addr()
263 hw->mac.ops.set_dma_mask(hw, dma_mask); in fm10k_set_dma_mask()
279 return fm10k_call_func(hw, hw->mac.ops.get_fault, (hw, type, fault), in fm10k_get_fault()
[all …]
/f-stack/dpdk/drivers/common/iavf/
H A Diavf_adminq.c262 wr32(hw, hw->aq.asq.head, 0); in iavf_config_asq_regs()
263 wr32(hw, hw->aq.asq.tail, 0); in iavf_config_asq_regs()
266 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in iavf_config_asq_regs()
291 wr32(hw, hw->aq.arq.head, 0); in iavf_config_arq_regs()
292 wr32(hw, hw->aq.arq.tail, 0); in iavf_config_arq_regs()
295 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in iavf_config_arq_regs()
301 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); in iavf_config_arq_regs()
453 wr32(hw, hw->aq.asq.len, 0); in iavf_shutdown_asq()
454 wr32(hw, hw->aq.asq.bal, 0); in iavf_shutdown_asq()
455 wr32(hw, hw->aq.asq.bah, 0); in iavf_shutdown_asq()
[all …]
/f-stack/dpdk/drivers/net/ipn3ke/
H A Dipn3ke_ethdev.c159 hw->hw_cap.qm_offset = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
161 hw->hw_cap.qm_size = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
163 hw->hw_cap.ccb_offset = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
169 hw->hw_cap.qos_size = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
232 if (!(*hw->f_mac_read) || !(*hw->f_mac_write)) in ipn3ke_mtu_set()
235 (*hw->f_mac_read)(hw, in ipn3ke_mtu_set()
241 (*hw->f_mac_read)(hw, in ipn3ke_mtu_set()
249 (*hw->f_mac_write)(hw, in ipn3ke_mtu_set()
255 (*hw->f_mac_write)(hw, in ipn3ke_mtu_set()
323 hw->port_num = hw->retimer.port_num; in ipn3ke_hw_init()
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/f-stack/dpdk/drivers/net/hns3/
H A Dhns3_dcb.c703 hw->num_tc = hw->dcb_info.num_tc; in hns3_dcb_update_tc_queue_mapping()
1353 struct hns3_hw *hw = &hns->hw; in hns3_dcb_cfg_validate() local
1392 struct hns3_hw *hw = &hns->hw; in hns3_dcb_info_cfg() local
1447 struct hns3_hw *hw = &hns->hw; in hns3_dcb_info_update() local
1488 struct hns3_hw *hw = &hns->hw; in hns3_dcb_hw_configure() local
1559 struct hns3_hw *hw = &hns->hw; in hns3_dcb_configure() local
1620 hw->current_mode = hw->requested_mode; in hns3_dcb_init()
1665 struct hns3_hw *hw = &hns->hw; in hns3_update_queue_map_configure() local
1686 struct hns3_hw *hw = &hns->hw; in hns3_dcb_cfg_update() local
1729 hw->current_mode = hw->requested_mode; in hns3_dcb_pfc_enable()
[all …]

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