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Searched refs:hv (Results 1 – 25 of 40) sorted by relevance

12

/f-stack/dpdk/drivers/net/netvsc/
H A Dhn_vf.c60 if (hn_vf_attached(hv)) { in hn_vf_attach()
84 hv->vf_port = port_id; in hn_vf_attach()
99 err = hn_vf_attach(hv, port); in hn_vf_add()
110 if (!hn_vf_attached(hv)) { in hn_vf_remove()
117 rte_eth_dev_owner_unset(hv->vf_port, hv->owner.id); in hn_vf_remove()
148 hn_vf_add(dev, hv); in hn_nvs_handle_vfassoc()
150 hn_vf_remove(hv); in hn_nvs_handle_vfassoc()
212 vf_dev = hn_get_vf_dev(hv); in hn_vf_info_get()
254 vf_dev = hn_get_vf_dev(hv); in hn_vf_supported_ptypes()
269 vf_dev = hn_get_vf_dev(hv); in hn_vf_start()
[all …]
H A Dhn_nvs.c194 hv->rxbuf_res->addr, in hn_nvs_conn_rxbuf()
231 hv->rxbuf_section_cnt, in hn_nvs_conn_rxbuf()
275 if (hv->chim_cnt != 0) { in hn_nvs_disconn_chim()
291 hv->chim_cnt = 0; in hn_nvs_disconn_chim()
315 hv->chim_res->addr, in hn_nvs_conn_chim()
342 hv->chim_szmax = sectsz; in hn_nvs_conn_chim()
346 len, hv->chim_szmax, hv->chim_cnt); in hn_nvs_conn_chim()
352 hn_nvs_disconn_chim(hv); in hn_nvs_conn_chim()
431 hv->nvs_ver, NDIS_VERSION_MAJOR(hv->ndis_ver), in hn_nvs_init()
449 error = hn_nvs_init(hv); in hn_nvs_attach()
[all …]
H A Dhn_ethdev.c526 rte_vmbus_set_latency(hv->vmbus, new_sc, hv->latency); in hn_subchan_configure()
933 hn_nvs_detach(hv); in hn_attach()
941 hn_nvs_detach(hv); in hn_detach()
982 hv->vmbus = vmbus; in eth_hn_dev_init()
990 hv->max_queues = 1; in eth_hn_dev_init()
1012 rte_vmbus_set_latency(hv->vmbus, hv->channels[0], hv->latency); in eth_hn_dev_init()
1014 hv->primary = hn_rx_queue_alloc(hv, 0, in eth_hn_dev_init()
1017 if (!hv->primary) in eth_hn_dev_init()
1047 if (hv->vf_present && !hn_vf_attached(hv)) { in eth_hn_dev_init()
1061 hn_detach(hv); in eth_hn_dev_init()
[all …]
H A Dhn_rndis.h7 void hn_rndis_receive_response(struct hn_data *hv,
10 int hn_rndis_attach(struct hn_data *hv);
11 void hn_rndis_detach(struct hn_data *hv);
12 int hn_rndis_get_eaddr(struct hn_data *hv, uint8_t *eaddr);
13 int hn_rndis_get_linkstatus(struct hn_data *hv);
14 int hn_rndis_get_linkspeed(struct hn_data *hv);
18 int hn_rndis_get_offload(struct hn_data *hv,
20 int hn_rndis_conf_offload(struct hn_data *hv,
23 int hn_rndis_query_rsscaps(struct hn_data *hv,
25 int hn_rndis_query_rss(struct hn_data *hv,
[all …]
H A Dhn_rndis.c57 hn_rndis_rid(struct hn_data *hv) in hn_rndis_rid() argument
407 if (hv->closed) in hn_rndis_exec1()
489 rid = hn_rndis_rid(hv); in hn_rndis_query()
558 halt->rid = hn_rndis_rid(hv); in hn_rndis_halt()
711 hv->rss_offloads = 0; in hn_rndis_query_rsscaps()
743 rid = hn_rndis_rid(hv); in hn_rndis_set()
1045 rid = hn_rndis_rid(hv); in hn_rndis_init()
1087 hv->rndis_agg_size, hv->rndis_agg_pkts, in hn_rndis_init()
1088 hv->rndis_agg_align); in hn_rndis_init()
1131 return hn_rndis_init(hv); in hn_rndis_attach()
[all …]
H A Dhn_rxtx.c180 hv->chim_bmap = rte_bitmap_init(hv->chim_cnt, in hn_chim_init()
199 rte_free(hv->chim_bmem); in hn_chim_uninit()
200 hv->chim_bmem = NULL; in hn_chim_uninit()
271 txq->hv = hv; in hn_dev_tx_queue_setup()
304 txq->agg_szmax = RTE_MIN(hv->chim_szmax, hv->rndis_agg_size); in hn_dev_tx_queue_setup()
556 struct hn_data *hv = rxq->hv; in hn_rxpkt() local
573 if (hv->rx_extmbuf_enable && dlen > hv->rx_copybreak && in hn_rxpkt()
883 rxq->hv = hv; in hn_rx_queue_alloc()
943 rxq = hv->primary; in hn_dev_rx_queue_setup()
1476 struct hn_data *hv = txq->hv; in hn_xmit_pkts() local
[all …]
H A Dhn_var.h56 struct hn_data *hv; member
81 struct hn_data *hv; member
159 hn_primary_chan(const struct hn_data *hv) in hn_primary_chan() argument
161 return hv->channels[0]; in hn_primary_chan()
184 struct hn_rx_queue *hn_rx_queue_alloc(struct hn_data *hv,
201 hn_vf_attached(const struct hn_data *hv) in hn_vf_attached() argument
203 return hv->vf_port != HN_INVALID_PORT; in hn_vf_attached()
211 hn_get_vf_dev(const struct hn_data *hv) in hn_get_vf_dev() argument
213 uint16_t vf_port = hv->vf_port; in hn_get_vf_dev()
221 int hn_vf_info_get(struct hn_data *hv,
[all …]
H A Dhn_nvs.h211 int hn_nvs_attach(struct hn_data *hv, unsigned int mtu);
212 void hn_nvs_detach(struct hn_data *hv);
214 int hn_nvs_alloc_subchans(struct hn_data *hv, uint32_t *nsubch);
215 void hn_nvs_set_datapath(struct hn_data *hv, uint32_t path);
/f-stack/freebsd/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.txt61 hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv
64 dsif spi ufs dmic-hv
65 edp sdmmc1-hv sdmmc3-hv conn
66 audio-hv ao-hv
81 for ao-hv. Following pads have software configurable signaling
82 voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv,
83 ao-hv.
97 pins = "sdmmc1-hv";
102 pins = "sdmmc1-hv";
/f-stack/app/nginx-1.16.1/src/http/modules/
H A Dngx_http_headers_filter_module.c16 ngx_http_header_val_t *hv, ngx_str_t *value);
555 h->key = hv->key; in ngx_http_add_header()
589 h->key = hv->key; in ngx_http_add_multi_header_lines()
648 h->key = hv->key; in ngx_http_set_response_header()
813 hv = ngx_array_push(*headers); in ngx_http_headers_add()
814 if (hv == NULL) { in ngx_http_headers_add()
818 hv->key = value[1]; in ngx_http_headers_add()
819 hv->handler = NULL; in ngx_http_headers_add()
820 hv->offset = 0; in ngx_http_headers_add()
821 hv->always = 0; in ngx_http_headers_add()
[all …]
/f-stack/freebsd/contrib/ipfilter/netinet/
H A Dip_state.c1073 u_int hv; local
1659 hv = DOUBLE_HASH(hv);
2691 u_int hv; local
2829 hv = DOUBLE_HASH(hv);
2860 hv = DOUBLE_HASH(hv);
2973 u_int hv;
3161 hv = DOUBLE_HASH(hv);
4466 u_int hv; local
4550 hv = DOUBLE_HASH(hv);
4616 hv = DOUBLE_HASH(hv);
[all …]
H A Dip_sync.c669 u_int hv; local
728 if (softs->syncstatetab[hv] != NULL)
730 softs->syncstatetab[hv] = sl;
905 u_int hv = 0; local
943 if (softs->syncnattab[hv] != NULL)
945 softs->syncnattab[hv] = sl;
1008 u_int hv, sz; local
1047 hv = softs->ipf_sync_num &
1052 softs->syncstatetab[hv] = sl;
1064 hv = softs->ipf_sync_num &
[all …]
H A Dip_nat6.c217 u_int hv; local
233 hv = 0;
243 n->in_hv[0] = hv;
266 u_int hv; local
276 hv = 0;
379 u_int hv; local
432 hm->hm_hv = hv;
1918 u_int hv; local
2038 hv = NAT_HASH_FN6(src, hv, softn->ipf_nat_table_sz);
2237 u_int hv; local
[all …]
H A Dip_htable.c911 u_int hv; local
938 hv = IPE_V6_HASH_FN(ipe->ipe_addr.i6,
949 ipe->ipe_hnext = iph->iph_table[hv];
950 ipe->ipe_phnext = iph->iph_table + hv;
952 if (iph->iph_table[hv] != NULL)
954 iph->iph_table[hv] = ipe;
1044 u_int hv; local
1060 hv = IPE_V4_HASH_FN(ipe.ipe_addr.in4_addr,
1066 hv = IPE_V6_HASH_FN(ipe.ipe_addr.i6,
1188 u_int hv; local
[all …]
H A Dip_nat.c638 u_int hv; local
680 u_int hv; local
780 u_int hv, rhv; local
785 rhv = hv;
4090 u_int hv, rhv; local
4215 hv = NAT_HASH_FN(src.s_addr, hv, softn->ipf_nat_table_sz);
4422 u_int hv; local
4538 hv = NAT_HASH_FN(dst.s_addr, hv, softn->ipf_nat_table_sz);
8045 u_int hv; local
8230 u_int hv; local
[all …]
/f-stack/freebsd/contrib/device-tree/src/powerpc/fsl/
H A Dinterlaken-lac.dtsi41 lac-hv@228000 {
42 compatible = "fsl,interlaken-lac-hv";
44 fsl,non-hv-node = <&lac>;
H A De6500_power_isa.dtsi45 power-isa-e.hv; // Embedded.Hypervisor
58 power-isa-e.hv.lrat; // Embedded.Hypervisor.LRAT
/f-stack/freebsd/contrib/device-tree/src/arm64/nvidia/
H A Dtegra210-p2595.dtsi18 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
27 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
36 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
45 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
54 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
308 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
317 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
473 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
482 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
491 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
[all …]
H A Dtegra210-p2571.dts22 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
31 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
40 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
49 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
58 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
312 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
321 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
482 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
491 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
500 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
[all …]
H A Dtegra210-p2894.dtsi37 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
46 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
55 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
64 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
73 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
326 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
335 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
498 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
516 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
525 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
[all …]
H A Dtegra210-p2597.dtsi52 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
61 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
70 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
79 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
88 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
332 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
341 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
499 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
508 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
517 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
[all …]
H A Dtegra210-smaug.dts50 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
59 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
68 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
77 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
86 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
335 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
344 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
504 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
513 nvidia,io-hv = <TEGRA_PIN_DISABLE>;
522 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
[all …]
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Dtegra114-tn7.dts103 regulator-name = "va-lcd-hv";
175 regulator-name = "vd-ts-hv";
183 regulator-name = "va-cam2-hv";
189 regulator-name = "va-sns-hv";
195 regulator-name = "va-cam1-hv";
/f-stack/freebsd/contrib/device-tree/Bindings/powerpc/fsl/
H A Dinterlaken-lac.txt54 "fsl,interlaken-lac-hv". This node represents the protected
58 - fsl,non-hv-node
59 Usage: required in "fsl,interlaken-lac-hv"
71 Usage: required in non-hv node only
82 lac-hv@228000 {
83 compatible = "fsl,interlaken-lac-hv"
85 fsl,non-hv-node = <&lac>;
/f-stack/freebsd/contrib/device-tree/Bindings/powerpc/
H A Dibm,powerpc-cpu-features.txt110 - hv-support
153 This property exists when the hv-support property HFSCR bit is set. This
227 hv-support = <0>;
234 hv-support = <0>;

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