1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
3 */
4
5 /* 82562G 10/100 Network Connection
6 * 82562G-2 10/100 Network Connection
7 * 82562GT 10/100 Network Connection
8 * 82562GT-2 10/100 Network Connection
9 * 82562V 10/100 Network Connection
10 * 82562V-2 10/100 Network Connection
11 * 82566DC-2 Gigabit Network Connection
12 * 82566DC Gigabit Network Connection
13 * 82566DM-2 Gigabit Network Connection
14 * 82566DM Gigabit Network Connection
15 * 82566MC Gigabit Network Connection
16 * 82566MM Gigabit Network Connection
17 * 82567LM Gigabit Network Connection
18 * 82567LF Gigabit Network Connection
19 * 82567V Gigabit Network Connection
20 * 82567LM-2 Gigabit Network Connection
21 * 82567LF-2 Gigabit Network Connection
22 * 82567V-2 Gigabit Network Connection
23 * 82567LF-3 Gigabit Network Connection
24 * 82567LM-3 Gigabit Network Connection
25 * 82567LM-4 Gigabit Network Connection
26 * 82577LM Gigabit Network Connection
27 * 82577LC Gigabit Network Connection
28 * 82578DM Gigabit Network Connection
29 * 82578DC Gigabit Network Connection
30 * 82579LM Gigabit Network Connection
31 * 82579V Gigabit Network Connection
32 * Ethernet Connection I217-LM
33 * Ethernet Connection I217-V
34 * Ethernet Connection I218-V
35 * Ethernet Connection I218-LM
36 * Ethernet Connection (2) I218-LM
37 * Ethernet Connection (2) I218-V
38 * Ethernet Connection (3) I218-LM
39 * Ethernet Connection (3) I218-V
40 */
41
42 #include "e1000_api.h"
43
44 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
45 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
46 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
47 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
48 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
49 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
50 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
51 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
52 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
53 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
54 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
55 u8 *mc_addr_list,
56 u32 mc_addr_count);
57 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
58 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
59 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
60 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
61 bool active);
62 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
63 bool active);
64 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
65 u16 words, u16 *data);
66 STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
67 u16 *data);
68 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
69 u16 words, u16 *data);
70 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
71 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
72 STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
73 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
74 u16 *data);
75 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
76 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
77 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
78 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
79 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
80 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
81 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
82 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
83 u16 *speed, u16 *duplex);
84 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
85 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
86 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
87 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
88 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
89 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
90 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw);
91 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw);
92 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
93 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
94 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
95 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
96 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
97 u32 offset, u8 *data);
98 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
99 u8 size, u16 *data);
100 STATIC s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
101 u32 *data);
102 STATIC s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
103 u32 offset, u32 *data);
104 STATIC s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
105 u32 offset, u32 data);
106 STATIC s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
107 u32 offset, u32 dword);
108 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
109 u32 offset, u16 *data);
110 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
111 u32 offset, u8 byte);
112 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
113 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
114 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
115 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
116 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
117 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
118
119 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
120 /* Offset 04h HSFSTS */
121 union ich8_hws_flash_status {
122 struct ich8_hsfsts {
123 u16 flcdone:1; /* bit 0 Flash Cycle Done */
124 u16 flcerr:1; /* bit 1 Flash Cycle Error */
125 u16 dael:1; /* bit 2 Direct Access error Log */
126 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
127 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
128 u16 reserved1:2; /* bit 13:6 Reserved */
129 u16 reserved2:6; /* bit 13:6 Reserved */
130 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
131 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
132 } hsf_status;
133 u16 regval;
134 };
135
136 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
137 /* Offset 06h FLCTL */
138 union ich8_hws_flash_ctrl {
139 struct ich8_hsflctl {
140 u16 flcgo:1; /* 0 Flash Cycle Go */
141 u16 flcycle:2; /* 2:1 Flash Cycle */
142 u16 reserved:5; /* 7:3 Reserved */
143 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
144 u16 flockdn:6; /* 15:10 Reserved */
145 } hsf_ctrl;
146 u16 regval;
147 };
148
149 /* ICH Flash Region Access Permissions */
150 union ich8_hws_flash_regacc {
151 struct ich8_flracc {
152 u32 grra:8; /* 0:7 GbE region Read Access */
153 u32 grwa:8; /* 8:15 GbE region Write Access */
154 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
155 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
156 } hsf_flregacc;
157 u16 regval;
158 };
159
160 /**
161 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
162 * @hw: pointer to the HW structure
163 *
164 * Test access to the PHY registers by reading the PHY ID registers. If
165 * the PHY ID is already known (e.g. resume path) compare it with known ID,
166 * otherwise assume the read PHY ID is correct if it is valid.
167 *
168 * Assumes the sw/fw/hw semaphore is already acquired.
169 **/
e1000_phy_is_accessible_pchlan(struct e1000_hw * hw)170 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
171 {
172 u16 phy_reg = 0;
173 u32 phy_id = 0;
174 s32 ret_val = 0;
175 u16 retry_count;
176 u32 mac_reg = 0;
177
178 for (retry_count = 0; retry_count < 2; retry_count++) {
179 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
180 if (ret_val || (phy_reg == 0xFFFF))
181 continue;
182 phy_id = (u32)(phy_reg << 16);
183
184 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
185 if (ret_val || (phy_reg == 0xFFFF)) {
186 phy_id = 0;
187 continue;
188 }
189 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
190 break;
191 }
192
193 if (hw->phy.id) {
194 if (hw->phy.id == phy_id)
195 goto out;
196 } else if (phy_id) {
197 hw->phy.id = phy_id;
198 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
199 goto out;
200 }
201
202 /* In case the PHY needs to be in mdio slow mode,
203 * set slow mode and try to get the PHY id again.
204 */
205 if (hw->mac.type < e1000_pch_lpt) {
206 hw->phy.ops.release(hw);
207 ret_val = e1000_set_mdio_slow_mode_hv(hw);
208 if (!ret_val)
209 ret_val = e1000_get_phy_id(hw);
210 hw->phy.ops.acquire(hw);
211 }
212
213 if (ret_val)
214 return false;
215 out:
216 if (hw->mac.type >= e1000_pch_lpt) {
217 /* Only unforce SMBus if ME is not active */
218 if (!(E1000_READ_REG(hw, E1000_FWSM) &
219 E1000_ICH_FWSM_FW_VALID)) {
220 /* Unforce SMBus mode in PHY */
221 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
222 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
223 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
224
225 /* Unforce SMBus mode in MAC */
226 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
227 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
228 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
229 }
230 }
231
232 return true;
233 }
234
235 /**
236 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
237 * @hw: pointer to the HW structure
238 *
239 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
240 * used to reset the PHY to a quiescent state when necessary.
241 **/
e1000_toggle_lanphypc_pch_lpt(struct e1000_hw * hw)242 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
243 {
244 u32 mac_reg;
245
246 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
247
248 /* Set Phy Config Counter to 50msec */
249 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
250 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
251 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
252 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
253
254 /* Toggle LANPHYPC Value bit */
255 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
256 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
257 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
258 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
259 E1000_WRITE_FLUSH(hw);
260 msec_delay(1);
261 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
262 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
263 E1000_WRITE_FLUSH(hw);
264
265 if (hw->mac.type < e1000_pch_lpt) {
266 msec_delay(50);
267 } else {
268 u16 count = 20;
269
270 do {
271 msec_delay(5);
272 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
273 E1000_CTRL_EXT_LPCD) && count--);
274
275 msec_delay(30);
276 }
277 }
278
279 /**
280 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
281 * @hw: pointer to the HW structure
282 *
283 * Workarounds/flow necessary for PHY initialization during driver load
284 * and resume paths.
285 **/
e1000_init_phy_workarounds_pchlan(struct e1000_hw * hw)286 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
287 {
288 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
289 s32 ret_val;
290
291 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
292
293 /* Gate automatic PHY configuration by hardware on managed and
294 * non-managed 82579 and newer adapters.
295 */
296 e1000_gate_hw_phy_config_ich8lan(hw, true);
297
298 /* It is not possible to be certain of the current state of ULP
299 * so forcibly disable it.
300 */
301 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
302
303 ret_val = hw->phy.ops.acquire(hw);
304 if (ret_val) {
305 DEBUGOUT("Failed to initialize PHY flow\n");
306 goto out;
307 }
308
309 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
310 * inaccessible and resetting the PHY is not blocked, toggle the
311 * LANPHYPC Value bit to force the interconnect to PCIe mode.
312 */
313 switch (hw->mac.type) {
314 case e1000_pch_lpt:
315 case e1000_pch_spt:
316 case e1000_pch_cnp:
317 case e1000_pch_adp:
318 if (e1000_phy_is_accessible_pchlan(hw))
319 break;
320
321 /* Before toggling LANPHYPC, see if PHY is accessible by
322 * forcing MAC to SMBus mode first.
323 */
324 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
325 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
326 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
327
328 /* Wait 50 milliseconds for MAC to finish any retries
329 * that it might be trying to perform from previous
330 * attempts to acknowledge any phy read requests.
331 */
332 msec_delay(50);
333
334 /* fall-through */
335 case e1000_pch2lan:
336 if (e1000_phy_is_accessible_pchlan(hw))
337 break;
338
339 /* fall-through */
340 case e1000_pchlan:
341 if ((hw->mac.type == e1000_pchlan) &&
342 (fwsm & E1000_ICH_FWSM_FW_VALID))
343 break;
344
345 if (hw->phy.ops.check_reset_block(hw)) {
346 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
347 ret_val = -E1000_ERR_PHY;
348 break;
349 }
350
351 /* Toggle LANPHYPC Value bit */
352 e1000_toggle_lanphypc_pch_lpt(hw);
353 if (hw->mac.type >= e1000_pch_lpt) {
354 if (e1000_phy_is_accessible_pchlan(hw))
355 break;
356
357 /* Toggling LANPHYPC brings the PHY out of SMBus mode
358 * so ensure that the MAC is also out of SMBus mode
359 */
360 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
361 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
362 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
363
364 if (e1000_phy_is_accessible_pchlan(hw))
365 break;
366
367 ret_val = -E1000_ERR_PHY;
368 }
369 break;
370 default:
371 break;
372 }
373
374 hw->phy.ops.release(hw);
375 if (!ret_val) {
376
377 /* Check to see if able to reset PHY. Print error if not */
378 if (hw->phy.ops.check_reset_block(hw)) {
379 ERROR_REPORT("Reset blocked by ME\n");
380 goto out;
381 }
382
383 /* Reset the PHY before any access to it. Doing so, ensures
384 * that the PHY is in a known good state before we read/write
385 * PHY registers. The generic reset is sufficient here,
386 * because we haven't determined the PHY type yet.
387 */
388 ret_val = e1000_phy_hw_reset_generic(hw);
389 if (ret_val)
390 goto out;
391
392 /* On a successful reset, possibly need to wait for the PHY
393 * to quiesce to an accessible state before returning control
394 * to the calling function. If the PHY does not quiesce, then
395 * return E1000E_BLK_PHY_RESET, as this is the condition that
396 * the PHY is in.
397 */
398 ret_val = hw->phy.ops.check_reset_block(hw);
399 if (ret_val)
400 ERROR_REPORT("ME blocked access to PHY after reset\n");
401 }
402
403 out:
404 /* Ungate automatic PHY configuration on non-managed 82579 */
405 if ((hw->mac.type == e1000_pch2lan) &&
406 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
407 msec_delay(10);
408 e1000_gate_hw_phy_config_ich8lan(hw, false);
409 }
410
411 return ret_val;
412 }
413
414 /**
415 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
416 * @hw: pointer to the HW structure
417 *
418 * Initialize family-specific PHY parameters and function pointers.
419 **/
e1000_init_phy_params_pchlan(struct e1000_hw * hw)420 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
421 {
422 struct e1000_phy_info *phy = &hw->phy;
423 s32 ret_val;
424
425 DEBUGFUNC("e1000_init_phy_params_pchlan");
426
427 phy->addr = 1;
428 phy->reset_delay_us = 100;
429
430 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
431 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
432 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
433 phy->ops.set_page = e1000_set_page_igp;
434 phy->ops.read_reg = e1000_read_phy_reg_hv;
435 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
436 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
437 phy->ops.release = e1000_release_swflag_ich8lan;
438 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
439 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
440 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
441 phy->ops.write_reg = e1000_write_phy_reg_hv;
442 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
443 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
444 phy->ops.power_up = e1000_power_up_phy_copper;
445 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
446 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
447
448 phy->id = e1000_phy_unknown;
449
450 ret_val = e1000_init_phy_workarounds_pchlan(hw);
451 if (ret_val)
452 return ret_val;
453
454 if (phy->id == e1000_phy_unknown)
455 switch (hw->mac.type) {
456 default:
457 ret_val = e1000_get_phy_id(hw);
458 if (ret_val)
459 return ret_val;
460 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
461 break;
462 /* fall-through */
463 case e1000_pch2lan:
464 case e1000_pch_lpt:
465 case e1000_pch_spt:
466 case e1000_pch_cnp:
467 case e1000_pch_adp:
468 /* In case the PHY needs to be in mdio slow mode,
469 * set slow mode and try to get the PHY id again.
470 */
471 ret_val = e1000_set_mdio_slow_mode_hv(hw);
472 if (ret_val)
473 return ret_val;
474 ret_val = e1000_get_phy_id(hw);
475 if (ret_val)
476 return ret_val;
477 break;
478 }
479 phy->type = e1000_get_phy_type_from_id(phy->id);
480
481 switch (phy->type) {
482 case e1000_phy_82577:
483 case e1000_phy_82579:
484 case e1000_phy_i217:
485 phy->ops.check_polarity = e1000_check_polarity_82577;
486 phy->ops.force_speed_duplex =
487 e1000_phy_force_speed_duplex_82577;
488 phy->ops.get_cable_length = e1000_get_cable_length_82577;
489 phy->ops.get_info = e1000_get_phy_info_82577;
490 phy->ops.commit = e1000_phy_sw_reset_generic;
491 break;
492 case e1000_phy_82578:
493 phy->ops.check_polarity = e1000_check_polarity_m88;
494 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
495 phy->ops.get_cable_length = e1000_get_cable_length_m88;
496 phy->ops.get_info = e1000_get_phy_info_m88;
497 break;
498 default:
499 ret_val = -E1000_ERR_PHY;
500 break;
501 }
502
503 return ret_val;
504 }
505
506 /**
507 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
508 * @hw: pointer to the HW structure
509 *
510 * Initialize family-specific PHY parameters and function pointers.
511 **/
e1000_init_phy_params_ich8lan(struct e1000_hw * hw)512 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
513 {
514 struct e1000_phy_info *phy = &hw->phy;
515 s32 ret_val;
516 u16 i = 0;
517
518 DEBUGFUNC("e1000_init_phy_params_ich8lan");
519
520 phy->addr = 1;
521 phy->reset_delay_us = 100;
522
523 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
524 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
525 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
526 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
527 phy->ops.read_reg = e1000_read_phy_reg_igp;
528 phy->ops.release = e1000_release_swflag_ich8lan;
529 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
530 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
531 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
532 phy->ops.write_reg = e1000_write_phy_reg_igp;
533 phy->ops.power_up = e1000_power_up_phy_copper;
534 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
535
536 /* We may need to do this twice - once for IGP and if that fails,
537 * we'll set BM func pointers and try again
538 */
539 ret_val = e1000_determine_phy_address(hw);
540 if (ret_val) {
541 phy->ops.write_reg = e1000_write_phy_reg_bm;
542 phy->ops.read_reg = e1000_read_phy_reg_bm;
543 ret_val = e1000_determine_phy_address(hw);
544 if (ret_val) {
545 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
546 return ret_val;
547 }
548 }
549
550 phy->id = 0;
551 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
552 (i++ < 100)) {
553 msec_delay(1);
554 ret_val = e1000_get_phy_id(hw);
555 if (ret_val)
556 return ret_val;
557 }
558
559 /* Verify phy id */
560 switch (phy->id) {
561 case IGP03E1000_E_PHY_ID:
562 phy->type = e1000_phy_igp_3;
563 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
564 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
565 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
566 phy->ops.get_info = e1000_get_phy_info_igp;
567 phy->ops.check_polarity = e1000_check_polarity_igp;
568 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
569 break;
570 case IFE_E_PHY_ID:
571 case IFE_PLUS_E_PHY_ID:
572 case IFE_C_E_PHY_ID:
573 phy->type = e1000_phy_ife;
574 phy->autoneg_mask = E1000_ALL_NOT_GIG;
575 phy->ops.get_info = e1000_get_phy_info_ife;
576 phy->ops.check_polarity = e1000_check_polarity_ife;
577 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
578 break;
579 case BME1000_E_PHY_ID:
580 phy->type = e1000_phy_bm;
581 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
582 phy->ops.read_reg = e1000_read_phy_reg_bm;
583 phy->ops.write_reg = e1000_write_phy_reg_bm;
584 phy->ops.commit = e1000_phy_sw_reset_generic;
585 phy->ops.get_info = e1000_get_phy_info_m88;
586 phy->ops.check_polarity = e1000_check_polarity_m88;
587 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
588 break;
589 default:
590 return -E1000_ERR_PHY;
591 break;
592 }
593
594 return E1000_SUCCESS;
595 }
596
597 /**
598 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
599 * @hw: pointer to the HW structure
600 *
601 * Initialize family-specific NVM parameters and function
602 * pointers.
603 **/
e1000_init_nvm_params_ich8lan(struct e1000_hw * hw)604 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
605 {
606 struct e1000_nvm_info *nvm = &hw->nvm;
607 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
608 u32 gfpreg, sector_base_addr, sector_end_addr;
609 u16 i;
610 u32 nvm_size;
611
612 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
613
614 nvm->type = e1000_nvm_flash_sw;
615
616 if (hw->mac.type >= e1000_pch_spt) {
617 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
618 * STRAP register. This is because in SPT the GbE Flash region
619 * is no longer accessed through the flash registers. Instead,
620 * the mechanism has changed, and the Flash region access
621 * registers are now implemented in GbE memory space.
622 */
623 nvm->flash_base_addr = 0;
624 nvm_size =
625 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
626 * NVM_SIZE_MULTIPLIER;
627 nvm->flash_bank_size = nvm_size / 2;
628 /* Adjust to word count */
629 nvm->flash_bank_size /= sizeof(u16);
630 /* Set the base address for flash register access */
631 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
632 } else {
633 /* Can't read flash registers if register set isn't mapped. */
634 if (!hw->flash_address) {
635 DEBUGOUT("ERROR: Flash registers not mapped\n");
636 return -E1000_ERR_CONFIG;
637 }
638
639 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
640
641 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
642 * Add 1 to sector_end_addr since this sector is included in
643 * the overall size.
644 */
645 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
646 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
647
648 /* flash_base_addr is byte-aligned */
649 nvm->flash_base_addr = sector_base_addr
650 << FLASH_SECTOR_ADDR_SHIFT;
651
652 /* find total size of the NVM, then cut in half since the total
653 * size represents two separate NVM banks.
654 */
655 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
656 << FLASH_SECTOR_ADDR_SHIFT);
657 nvm->flash_bank_size /= 2;
658 /* Adjust to word count */
659 nvm->flash_bank_size /= sizeof(u16);
660 }
661
662 nvm->word_size = E1000_SHADOW_RAM_WORDS;
663
664 /* Clear shadow ram */
665 for (i = 0; i < nvm->word_size; i++) {
666 dev_spec->shadow_ram[i].modified = false;
667 dev_spec->shadow_ram[i].value = 0xFFFF;
668 }
669
670 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
671 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
672
673 /* Function Pointers */
674 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
675 nvm->ops.release = e1000_release_nvm_ich8lan;
676 if (hw->mac.type >= e1000_pch_spt) {
677 nvm->ops.read = e1000_read_nvm_spt;
678 nvm->ops.update = e1000_update_nvm_checksum_spt;
679 } else {
680 nvm->ops.read = e1000_read_nvm_ich8lan;
681 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
682 }
683 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
684 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
685 nvm->ops.write = e1000_write_nvm_ich8lan;
686
687 return E1000_SUCCESS;
688 }
689
690 /**
691 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
692 * @hw: pointer to the HW structure
693 *
694 * Initialize family-specific MAC parameters and function
695 * pointers.
696 **/
e1000_init_mac_params_ich8lan(struct e1000_hw * hw)697 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
698 {
699 struct e1000_mac_info *mac = &hw->mac;
700 u16 pci_cfg;
701
702 DEBUGFUNC("e1000_init_mac_params_ich8lan");
703
704 /* Set media type function pointer */
705 hw->phy.media_type = e1000_media_type_copper;
706
707 /* Set mta register count */
708 mac->mta_reg_count = 32;
709 /* Set rar entry count */
710 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
711 if (mac->type == e1000_ich8lan)
712 mac->rar_entry_count--;
713 /* Set if part includes ASF firmware */
714 mac->asf_firmware_present = true;
715 /* FWSM register */
716 mac->has_fwsm = true;
717 /* ARC subsystem not supported */
718 mac->arc_subsystem_valid = false;
719 /* Adaptive IFS supported */
720 mac->adaptive_ifs = true;
721
722 /* Function pointers */
723
724 /* bus type/speed/width */
725 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
726 /* function id */
727 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
728 /* reset */
729 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
730 /* hw initialization */
731 mac->ops.init_hw = e1000_init_hw_ich8lan;
732 /* link setup */
733 mac->ops.setup_link = e1000_setup_link_ich8lan;
734 /* physical interface setup */
735 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
736 /* check for link */
737 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
738 /* link info */
739 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
740 /* multicast address update */
741 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
742 /* clear hardware counters */
743 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
744
745 /* LED and other operations */
746 switch (mac->type) {
747 case e1000_ich8lan:
748 case e1000_ich9lan:
749 case e1000_ich10lan:
750 /* check management mode */
751 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
752 /* ID LED init */
753 mac->ops.id_led_init = e1000_id_led_init_generic;
754 /* blink LED */
755 mac->ops.blink_led = e1000_blink_led_generic;
756 /* setup LED */
757 mac->ops.setup_led = e1000_setup_led_generic;
758 /* cleanup LED */
759 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
760 /* turn on/off LED */
761 mac->ops.led_on = e1000_led_on_ich8lan;
762 mac->ops.led_off = e1000_led_off_ich8lan;
763 break;
764 case e1000_pch2lan:
765 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
766 mac->ops.rar_set = e1000_rar_set_pch2lan;
767 /* fall-through */
768 case e1000_pch_lpt:
769 case e1000_pch_spt:
770 case e1000_pch_cnp:
771 case e1000_pch_adp:
772 /* multicast address update for pch2 */
773 mac->ops.update_mc_addr_list =
774 e1000_update_mc_addr_list_pch2lan;
775 /* fall-through */
776 case e1000_pchlan:
777 /* save PCH revision_id */
778 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
779 /* SPT uses full byte for revision ID,
780 * as opposed to previous generations
781 */
782 if (hw->mac.type >= e1000_pch_spt)
783 hw->revision_id = (u8)(pci_cfg &= 0x00FF);
784 else
785 hw->revision_id = (u8)(pci_cfg &= 0x000F);
786 /* check management mode */
787 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
788 /* ID LED init */
789 mac->ops.id_led_init = e1000_id_led_init_pchlan;
790 /* setup LED */
791 mac->ops.setup_led = e1000_setup_led_pchlan;
792 /* cleanup LED */
793 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
794 /* turn on/off LED */
795 mac->ops.led_on = e1000_led_on_pchlan;
796 mac->ops.led_off = e1000_led_off_pchlan;
797 break;
798 default:
799 break;
800 }
801
802 if (mac->type >= e1000_pch_lpt) {
803 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
804 mac->ops.rar_set = e1000_rar_set_pch_lpt;
805 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
806 }
807
808 /* Enable PCS Lock-loss workaround for ICH8 */
809 if (mac->type == e1000_ich8lan)
810 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
811
812 return E1000_SUCCESS;
813 }
814
815 /**
816 * __e1000_access_emi_reg_locked - Read/write EMI register
817 * @hw: pointer to the HW structure
818 * @address: EMI address to program
819 * @data: pointer to value to read/write from/to the EMI address
820 * @read: boolean flag to indicate read or write
821 *
822 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
823 **/
__e1000_access_emi_reg_locked(struct e1000_hw * hw,u16 address,u16 * data,bool read)824 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
825 u16 *data, bool read)
826 {
827 s32 ret_val;
828
829 DEBUGFUNC("__e1000_access_emi_reg_locked");
830
831 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
832 if (ret_val)
833 return ret_val;
834
835 if (read)
836 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
837 data);
838 else
839 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
840 *data);
841
842 return ret_val;
843 }
844
845 /**
846 * e1000_read_emi_reg_locked - Read Extended Management Interface register
847 * @hw: pointer to the HW structure
848 * @addr: EMI address to program
849 * @data: value to be read from the EMI address
850 *
851 * Assumes the SW/FW/HW Semaphore is already acquired.
852 **/
e1000_read_emi_reg_locked(struct e1000_hw * hw,u16 addr,u16 * data)853 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
854 {
855 DEBUGFUNC("e1000_read_emi_reg_locked");
856
857 return __e1000_access_emi_reg_locked(hw, addr, data, true);
858 }
859
860 /**
861 * e1000_write_emi_reg_locked - Write Extended Management Interface register
862 * @hw: pointer to the HW structure
863 * @addr: EMI address to program
864 * @data: value to be written to the EMI address
865 *
866 * Assumes the SW/FW/HW Semaphore is already acquired.
867 **/
e1000_write_emi_reg_locked(struct e1000_hw * hw,u16 addr,u16 data)868 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
869 {
870 DEBUGFUNC("e1000_read_emi_reg_locked");
871
872 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
873 }
874
875 /**
876 * e1000_set_eee_pchlan - Enable/disable EEE support
877 * @hw: pointer to the HW structure
878 *
879 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
880 * the link and the EEE capabilities of the link partner. The LPI Control
881 * register bits will remain set only if/when link is up.
882 *
883 * EEE LPI must not be asserted earlier than one second after link is up.
884 * On 82579, EEE LPI should not be enabled until such time otherwise there
885 * can be link issues with some switches. Other devices can have EEE LPI
886 * enabled immediately upon link up since they have a timer in hardware which
887 * prevents LPI from being asserted too early.
888 **/
e1000_set_eee_pchlan(struct e1000_hw * hw)889 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
890 {
891 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
892 s32 ret_val;
893 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
894
895 DEBUGFUNC("e1000_set_eee_pchlan");
896
897 switch (hw->phy.type) {
898 case e1000_phy_82579:
899 lpa = I82579_EEE_LP_ABILITY;
900 pcs_status = I82579_EEE_PCS_STATUS;
901 adv_addr = I82579_EEE_ADVERTISEMENT;
902 break;
903 case e1000_phy_i217:
904 lpa = I217_EEE_LP_ABILITY;
905 pcs_status = I217_EEE_PCS_STATUS;
906 adv_addr = I217_EEE_ADVERTISEMENT;
907 break;
908 default:
909 return E1000_SUCCESS;
910 }
911
912 ret_val = hw->phy.ops.acquire(hw);
913 if (ret_val)
914 return ret_val;
915
916 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
917 if (ret_val)
918 goto release;
919
920 /* Clear bits that enable EEE in various speeds */
921 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
922
923 /* Enable EEE if not disabled by user */
924 if (!dev_spec->eee_disable) {
925 /* Save off link partner's EEE ability */
926 ret_val = e1000_read_emi_reg_locked(hw, lpa,
927 &dev_spec->eee_lp_ability);
928 if (ret_val)
929 goto release;
930
931 /* Read EEE advertisement */
932 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
933 if (ret_val)
934 goto release;
935
936 /* Enable EEE only for speeds in which the link partner is
937 * EEE capable and for which we advertise EEE.
938 */
939 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
940 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
941
942 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
943 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
944 if (data & NWAY_LPAR_100TX_FD_CAPS)
945 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
946 else
947 /* EEE is not supported in 100Half, so ignore
948 * partner's EEE in 100 ability if full-duplex
949 * is not advertised.
950 */
951 dev_spec->eee_lp_ability &=
952 ~I82579_EEE_100_SUPPORTED;
953 }
954 }
955
956 if (hw->phy.type == e1000_phy_82579) {
957 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
958 &data);
959 if (ret_val)
960 goto release;
961
962 data &= ~I82579_LPI_100_PLL_SHUT;
963 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
964 data);
965 }
966
967 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
968 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
969 if (ret_val)
970 goto release;
971
972 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
973 release:
974 hw->phy.ops.release(hw);
975
976 return ret_val;
977 }
978
979 /**
980 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
981 * @hw: pointer to the HW structure
982 * @link: link up bool flag
983 *
984 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
985 * preventing further DMA write requests. Workaround the issue by disabling
986 * the de-assertion of the clock request when in 1Gpbs mode.
987 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
988 * speeds in order to avoid Tx hangs.
989 **/
e1000_k1_workaround_lpt_lp(struct e1000_hw * hw,bool link)990 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
991 {
992 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
993 u32 status = E1000_READ_REG(hw, E1000_STATUS);
994 s32 ret_val = E1000_SUCCESS;
995 u16 reg;
996
997 if (link && (status & E1000_STATUS_SPEED_1000)) {
998 ret_val = hw->phy.ops.acquire(hw);
999 if (ret_val)
1000 return ret_val;
1001
1002 ret_val =
1003 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1004 ®);
1005 if (ret_val)
1006 goto release;
1007
1008 ret_val =
1009 e1000_write_kmrn_reg_locked(hw,
1010 E1000_KMRNCTRLSTA_K1_CONFIG,
1011 reg &
1012 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1013 if (ret_val)
1014 goto release;
1015
1016 usec_delay(10);
1017
1018 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1019 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1020
1021 ret_val =
1022 e1000_write_kmrn_reg_locked(hw,
1023 E1000_KMRNCTRLSTA_K1_CONFIG,
1024 reg);
1025 release:
1026 hw->phy.ops.release(hw);
1027 } else {
1028 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1029 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1030
1031 if ((hw->phy.revision > 5) || !link ||
1032 ((status & E1000_STATUS_SPEED_100) &&
1033 (status & E1000_STATUS_FD)))
1034 goto update_fextnvm6;
1035
1036 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1037 if (ret_val)
1038 return ret_val;
1039
1040 /* Clear link status transmit timeout */
1041 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1042
1043 if (status & E1000_STATUS_SPEED_100) {
1044 /* Set inband Tx timeout to 5x10us for 100Half */
1045 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1046
1047 /* Do not extend the K1 entry latency for 100Half */
1048 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1049 } else {
1050 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1051 reg |= 50 <<
1052 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1053
1054 /* Extend the K1 entry latency for 10 Mbps */
1055 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1056 }
1057
1058 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1059 if (ret_val)
1060 return ret_val;
1061
1062 update_fextnvm6:
1063 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1064 }
1065
1066 return ret_val;
1067 }
1068
1069 /**
1070 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1071 * @hw: pointer to the HW structure
1072 * @to_sx: boolean indicating a system power state transition to Sx
1073 *
1074 * When link is down, configure ULP mode to significantly reduce the power
1075 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1076 * ME firmware to start the ULP configuration. If not on an ME enabled
1077 * system, configure the ULP mode by software.
1078 */
e1000_enable_ulp_lpt_lp(struct e1000_hw * hw,bool to_sx)1079 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1080 {
1081 u32 mac_reg;
1082 s32 ret_val = E1000_SUCCESS;
1083 u16 phy_reg;
1084 u16 oem_reg = 0;
1085
1086 if ((hw->mac.type < e1000_pch_lpt) ||
1087 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1088 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1089 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1090 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1091 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1092 return 0;
1093
1094 if (!to_sx) {
1095 int i = 0;
1096 /* Poll up to 5 seconds for Cable Disconnected indication */
1097 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1098 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1099 /* Bail if link is re-acquired */
1100 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1101 return -E1000_ERR_PHY;
1102 if (i++ == 100)
1103 break;
1104
1105 msec_delay(50);
1106 }
1107 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1108 (E1000_READ_REG(hw, E1000_FEXT) &
1109 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1110 i * 50);
1111 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1112 E1000_FEXT_PHY_CABLE_DISCONNECTED))
1113 return 0;
1114 }
1115
1116 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1117 /* Request ME configure ULP mode in the PHY */
1118 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1119 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1120 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1121
1122 goto out;
1123 }
1124
1125 ret_val = hw->phy.ops.acquire(hw);
1126 if (ret_val)
1127 goto out;
1128
1129 /* During S0 Idle keep the phy in PCI-E mode */
1130 if (hw->dev_spec.ich8lan.smbus_disable)
1131 goto skip_smbus;
1132
1133 /* Force SMBus mode in PHY */
1134 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1135 if (ret_val)
1136 goto release;
1137 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1138 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1139
1140 /* Force SMBus mode in MAC */
1141 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1142 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1143 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1144
1145 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1146 * LPLU and disable Gig speed when entering ULP
1147 */
1148 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1149 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1150 &oem_reg);
1151 if (ret_val)
1152 goto release;
1153
1154 phy_reg = oem_reg;
1155 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1156
1157 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1158 phy_reg);
1159
1160 if (ret_val)
1161 goto release;
1162 }
1163
1164 skip_smbus:
1165 if (!to_sx) {
1166 /* Change the 'Link Status Change' interrupt to trigger
1167 * on 'Cable Status Change'
1168 */
1169 ret_val = e1000_read_kmrn_reg_locked(hw,
1170 E1000_KMRNCTRLSTA_OP_MODES,
1171 &phy_reg);
1172 if (ret_val)
1173 goto release;
1174 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1175 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1176 phy_reg);
1177 }
1178
1179 /* Set Inband ULP Exit, Reset to SMBus mode and
1180 * Disable SMBus Release on PERST# in PHY
1181 */
1182 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1183 if (ret_val)
1184 goto release;
1185 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1186 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1187 if (to_sx) {
1188 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1189 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1190 else
1191 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1192
1193 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1194 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1195 } else {
1196 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1197 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1198 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1199 }
1200 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1201
1202 /* Set Disable SMBus Release on PERST# in MAC */
1203 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1204 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1205 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1206
1207 /* Commit ULP changes in PHY by starting auto ULP configuration */
1208 phy_reg |= I218_ULP_CONFIG1_START;
1209 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1210
1211 if (!to_sx) {
1212 /* Disable Tx so that the MAC doesn't send any (buffered)
1213 * packets to the PHY.
1214 */
1215 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1216 mac_reg &= ~E1000_TCTL_EN;
1217 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1218 }
1219
1220 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1221 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1222 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1223 oem_reg);
1224 if (ret_val)
1225 goto release;
1226 }
1227
1228 release:
1229 hw->phy.ops.release(hw);
1230 out:
1231 if (ret_val)
1232 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1233 else
1234 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1235
1236 return ret_val;
1237 }
1238
1239 /**
1240 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1241 * @hw: pointer to the HW structure
1242 * @force: boolean indicating whether or not to force disabling ULP
1243 *
1244 * Un-configure ULP mode when link is up, the system is transitioned from
1245 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1246 * system, poll for an indication from ME that ULP has been un-configured.
1247 * If not on an ME enabled system, un-configure the ULP mode by software.
1248 *
1249 * During nominal operation, this function is called when link is acquired
1250 * to disable ULP mode (force=false); otherwise, for example when unloading
1251 * the driver or during Sx->S0 transitions, this is called with force=true
1252 * to forcibly disable ULP.
1253
1254 * When the cable is plugged in while the device is in D0, a Cable Status
1255 * Change interrupt is generated which causes this function to be called
1256 * to partially disable ULP mode and restart autonegotiation. This function
1257 * is then called again due to the resulting Link Status Change interrupt
1258 * to finish cleaning up after the ULP flow.
1259 */
e1000_disable_ulp_lpt_lp(struct e1000_hw * hw,bool force)1260 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1261 {
1262 s32 ret_val = E1000_SUCCESS;
1263 u8 ulp_exit_timeout = 30;
1264 u32 mac_reg;
1265 u16 phy_reg;
1266 int i = 0;
1267
1268 if ((hw->mac.type < e1000_pch_lpt) ||
1269 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1270 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1271 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1272 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1273 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1274 return 0;
1275
1276 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1277 if (force) {
1278 /* Request ME un-configure ULP mode in the PHY */
1279 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1280 mac_reg &= ~E1000_H2ME_ULP;
1281 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1282 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1283 }
1284
1285 if (hw->mac.type == e1000_pch_cnp)
1286 ulp_exit_timeout = 100;
1287
1288 while (E1000_READ_REG(hw, E1000_FWSM) &
1289 E1000_FWSM_ULP_CFG_DONE) {
1290 if (i++ == ulp_exit_timeout) {
1291 ret_val = -E1000_ERR_PHY;
1292 goto out;
1293 }
1294
1295 msec_delay(10);
1296 }
1297 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1298
1299 if (force) {
1300 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1301 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1302 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1303 } else {
1304 /* Clear H2ME.ULP after ME ULP configuration */
1305 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1306 mac_reg &= ~E1000_H2ME_ULP;
1307 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1308
1309 /* Restore link speed advertisements and restart
1310 * Auto-negotiation
1311 */
1312 if (hw->mac.autoneg) {
1313 ret_val = e1000_phy_setup_autoneg(hw);
1314 if (ret_val)
1315 goto out;
1316 } else {
1317 ret_val = e1000_setup_copper_link_generic(hw);
1318 if (ret_val)
1319 goto out;
1320 }
1321 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1322 }
1323
1324 goto out;
1325 }
1326
1327 ret_val = hw->phy.ops.acquire(hw);
1328 if (ret_val)
1329 goto out;
1330
1331 /* Revert the change to the 'Link Status Change'
1332 * interrupt to trigger on 'Cable Status Change'
1333 */
1334 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1335 &phy_reg);
1336 if (ret_val)
1337 goto release;
1338 phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1339 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1340
1341 if (force)
1342 /* Toggle LANPHYPC Value bit */
1343 e1000_toggle_lanphypc_pch_lpt(hw);
1344
1345 /* Unforce SMBus mode in PHY */
1346 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1347 if (ret_val) {
1348 /* The MAC might be in PCIe mode, so temporarily force to
1349 * SMBus mode in order to access the PHY.
1350 */
1351 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1352 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1353 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1354
1355 msec_delay(50);
1356
1357 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1358 &phy_reg);
1359 if (ret_val)
1360 goto release;
1361 }
1362 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1363 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1364
1365 /* Unforce SMBus mode in MAC */
1366 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1367 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1368 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1369
1370 /* When ULP mode was previously entered, K1 was disabled by the
1371 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1372 */
1373 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1374 if (ret_val)
1375 goto release;
1376 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1377 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1378
1379 /* Clear ULP enabled configuration */
1380 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1381 if (ret_val)
1382 goto release;
1383 /* CSC interrupt received due to ULP Indication */
1384 if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1385 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1386 I218_ULP_CONFIG1_STICKY_ULP |
1387 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1388 I218_ULP_CONFIG1_WOL_HOST |
1389 I218_ULP_CONFIG1_INBAND_EXIT |
1390 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1391 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1392 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1393 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1394
1395 /* Commit ULP changes by starting auto ULP configuration */
1396 phy_reg |= I218_ULP_CONFIG1_START;
1397 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1398
1399 /* Clear Disable SMBus Release on PERST# in MAC */
1400 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1401 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1402 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1403
1404 if (!force) {
1405 hw->phy.ops.release(hw);
1406
1407 if (hw->mac.autoneg)
1408 e1000_phy_setup_autoneg(hw);
1409 else
1410 e1000_setup_copper_link_generic(hw);
1411
1412 e1000_sw_lcd_config_ich8lan(hw);
1413
1414 e1000_oem_bits_config_ich8lan(hw, true);
1415
1416 /* Set ULP state to unknown and return non-zero to
1417 * indicate no link (yet) and re-enter on the next LSC
1418 * to finish disabling ULP flow.
1419 */
1420 hw->dev_spec.ich8lan.ulp_state =
1421 e1000_ulp_state_unknown;
1422
1423 return 1;
1424 }
1425 }
1426
1427 /* Re-enable Tx */
1428 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1429 mac_reg |= E1000_TCTL_EN;
1430 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1431
1432 release:
1433 hw->phy.ops.release(hw);
1434 if (force) {
1435 hw->phy.ops.reset(hw);
1436 msec_delay(50);
1437 }
1438 out:
1439 if (ret_val)
1440 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1441 else
1442 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1443
1444 return ret_val;
1445 }
1446
1447
1448
1449 /**
1450 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1451 * @hw: pointer to the HW structure
1452 *
1453 * Checks to see of the link status of the hardware has changed. If a
1454 * change in link status has been detected, then we read the PHY registers
1455 * to get the current speed/duplex if link exists.
1456 **/
e1000_check_for_copper_link_ich8lan(struct e1000_hw * hw)1457 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1458 {
1459 struct e1000_mac_info *mac = &hw->mac;
1460 s32 ret_val, tipg_reg = 0;
1461 u16 emi_addr, emi_val = 0;
1462 bool link = false;
1463 u16 phy_reg;
1464
1465 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1466
1467 /* We only want to go out to the PHY registers to see if Auto-Neg
1468 * has completed and/or if our link status has changed. The
1469 * get_link_status flag is set upon receiving a Link Status
1470 * Change or Rx Sequence Error interrupt.
1471 */
1472 if (!mac->get_link_status)
1473 return E1000_SUCCESS;
1474
1475 if ((hw->mac.type < e1000_pch_lpt) ||
1476 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1477 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1478 /* First we want to see if the MII Status Register reports
1479 * link. If so, then we want to get the current speed/duplex
1480 * of the PHY.
1481 */
1482 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1483 if (ret_val)
1484 return ret_val;
1485 } else {
1486 /* Check the MAC's STATUS register to determine link state
1487 * since the PHY could be inaccessible while in ULP mode.
1488 */
1489 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1490 if (link)
1491 ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1492 else
1493 ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1494 if (ret_val)
1495 return ret_val;
1496 }
1497
1498 if (hw->mac.type == e1000_pchlan) {
1499 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1500 if (ret_val)
1501 return ret_val;
1502 }
1503
1504 /* When connected at 10Mbps half-duplex, some parts are excessively
1505 * aggressive resulting in many collisions. To avoid this, increase
1506 * the IPG and reduce Rx latency in the PHY.
1507 */
1508 if ((hw->mac.type >= e1000_pch2lan) && link) {
1509 u16 speed, duplex;
1510
1511 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1512 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1513 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1514
1515 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1516 tipg_reg |= 0xFF;
1517 /* Reduce Rx latency in analog PHY */
1518 emi_val = 0;
1519 } else if (hw->mac.type >= e1000_pch_spt &&
1520 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1521 tipg_reg |= 0xC;
1522 emi_val = 1;
1523 } else {
1524 /* Roll back the default values */
1525 tipg_reg |= 0x08;
1526 emi_val = 1;
1527 }
1528
1529 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1530
1531 ret_val = hw->phy.ops.acquire(hw);
1532 if (ret_val)
1533 return ret_val;
1534
1535 if (hw->mac.type == e1000_pch2lan)
1536 emi_addr = I82579_RX_CONFIG;
1537 else
1538 emi_addr = I217_RX_CONFIG;
1539 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1540
1541
1542 if (hw->mac.type >= e1000_pch_lpt) {
1543 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1544 &phy_reg);
1545 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1546 if (speed == SPEED_100 || speed == SPEED_10)
1547 phy_reg |= 0x3E8;
1548 else
1549 phy_reg |= 0xFA;
1550 hw->phy.ops.write_reg_locked(hw,
1551 I217_PLL_CLOCK_GATE_REG,
1552 phy_reg);
1553
1554 if (speed == SPEED_1000) {
1555 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1556 &phy_reg);
1557
1558 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1559
1560 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1561 phy_reg);
1562 }
1563 }
1564 hw->phy.ops.release(hw);
1565
1566 if (ret_val)
1567 return ret_val;
1568
1569 if (hw->mac.type >= e1000_pch_spt) {
1570 u16 data;
1571 u16 ptr_gap;
1572
1573 if (speed == SPEED_1000) {
1574 ret_val = hw->phy.ops.acquire(hw);
1575 if (ret_val)
1576 return ret_val;
1577
1578 ret_val = hw->phy.ops.read_reg_locked(hw,
1579 PHY_REG(776, 20),
1580 &data);
1581 if (ret_val) {
1582 hw->phy.ops.release(hw);
1583 return ret_val;
1584 }
1585
1586 ptr_gap = (data & (0x3FF << 2)) >> 2;
1587 if (ptr_gap < 0x18) {
1588 data &= ~(0x3FF << 2);
1589 data |= (0x18 << 2);
1590 ret_val =
1591 hw->phy.ops.write_reg_locked(hw,
1592 PHY_REG(776, 20), data);
1593 }
1594 hw->phy.ops.release(hw);
1595 if (ret_val)
1596 return ret_val;
1597 } else {
1598 ret_val = hw->phy.ops.acquire(hw);
1599 if (ret_val)
1600 return ret_val;
1601
1602 ret_val = hw->phy.ops.write_reg_locked(hw,
1603 PHY_REG(776, 20),
1604 0xC023);
1605 hw->phy.ops.release(hw);
1606 if (ret_val)
1607 return ret_val;
1608
1609 }
1610 }
1611 }
1612
1613 /* I217 Packet Loss issue:
1614 * ensure that FEXTNVM4 Beacon Duration is set correctly
1615 * on power up.
1616 * Set the Beacon Duration for I217 to 8 usec
1617 */
1618 if (hw->mac.type >= e1000_pch_lpt) {
1619 u32 mac_reg;
1620
1621 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1622 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1623 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1624 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1625 }
1626
1627 /* Work-around I218 hang issue */
1628 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1629 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1630 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1631 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1632 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1633 if (ret_val)
1634 return ret_val;
1635 }
1636 /* Clear link partner's EEE ability */
1637 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1638
1639 /* Configure K0s minimum time */
1640 if (hw->mac.type >= e1000_pch_lpt) {
1641 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1642 }
1643
1644 if (hw->mac.type >= e1000_pch_lpt) {
1645 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1646
1647 if (hw->mac.type == e1000_pch_spt) {
1648 /* FEXTNVM6 K1-off workaround - for SPT only */
1649 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1650
1651 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1652 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1653 else
1654 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1655 }
1656
1657 if (hw->dev_spec.ich8lan.disable_k1_off == true)
1658 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1659
1660 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1661 }
1662
1663 if (!link)
1664 return E1000_SUCCESS; /* No link detected */
1665
1666 mac->get_link_status = false;
1667
1668 switch (hw->mac.type) {
1669 case e1000_pch2lan:
1670 ret_val = e1000_k1_workaround_lv(hw);
1671 if (ret_val)
1672 return ret_val;
1673 /* fall-thru */
1674 case e1000_pchlan:
1675 if (hw->phy.type == e1000_phy_82578) {
1676 ret_val = e1000_link_stall_workaround_hv(hw);
1677 if (ret_val)
1678 return ret_val;
1679 }
1680
1681 /* Workaround for PCHx parts in half-duplex:
1682 * Set the number of preambles removed from the packet
1683 * when it is passed from the PHY to the MAC to prevent
1684 * the MAC from misinterpreting the packet type.
1685 */
1686 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1687 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1688
1689 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1690 E1000_STATUS_FD)
1691 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1692
1693 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1694 break;
1695 default:
1696 break;
1697 }
1698
1699 /* Check if there was DownShift, must be checked
1700 * immediately after link-up
1701 */
1702 e1000_check_downshift_generic(hw);
1703
1704 /* Enable/Disable EEE after link up */
1705 if (hw->phy.type > e1000_phy_82579) {
1706 ret_val = e1000_set_eee_pchlan(hw);
1707 if (ret_val)
1708 return ret_val;
1709 }
1710
1711 /* If we are forcing speed/duplex, then we simply return since
1712 * we have already determined whether we have link or not.
1713 */
1714 if (!mac->autoneg)
1715 return -E1000_ERR_CONFIG;
1716
1717 /* Auto-Neg is enabled. Auto Speed Detection takes care
1718 * of MAC speed/duplex configuration. So we only need to
1719 * configure Collision Distance in the MAC.
1720 */
1721 mac->ops.config_collision_dist(hw);
1722
1723 /* Configure Flow Control now that Auto-Neg has completed.
1724 * First, we need to restore the desired flow control
1725 * settings because we may have had to re-autoneg with a
1726 * different link partner.
1727 */
1728 ret_val = e1000_config_fc_after_link_up_generic(hw);
1729 if (ret_val)
1730 DEBUGOUT("Error configuring flow control\n");
1731
1732 return ret_val;
1733 }
1734
1735 /**
1736 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1737 * @hw: pointer to the HW structure
1738 *
1739 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1740 **/
e1000_init_function_pointers_ich8lan(struct e1000_hw * hw)1741 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1742 {
1743 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1744
1745 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1746 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1747 switch (hw->mac.type) {
1748 case e1000_ich8lan:
1749 case e1000_ich9lan:
1750 case e1000_ich10lan:
1751 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1752 break;
1753 case e1000_pchlan:
1754 case e1000_pch2lan:
1755 case e1000_pch_lpt:
1756 case e1000_pch_spt:
1757 case e1000_pch_cnp:
1758 case e1000_pch_adp:
1759 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1760 break;
1761 default:
1762 break;
1763 }
1764 }
1765
1766 /**
1767 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1768 * @hw: pointer to the HW structure
1769 *
1770 * Acquires the mutex for performing NVM operations.
1771 **/
e1000_acquire_nvm_ich8lan(struct e1000_hw * hw)1772 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1773 {
1774 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1775
1776 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1777
1778 return E1000_SUCCESS;
1779 }
1780
1781 /**
1782 * e1000_release_nvm_ich8lan - Release NVM mutex
1783 * @hw: pointer to the HW structure
1784 *
1785 * Releases the mutex used while performing NVM operations.
1786 **/
e1000_release_nvm_ich8lan(struct e1000_hw * hw)1787 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1788 {
1789 DEBUGFUNC("e1000_release_nvm_ich8lan");
1790
1791 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1792
1793 return;
1794 }
1795
1796 /**
1797 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1798 * @hw: pointer to the HW structure
1799 *
1800 * Acquires the software control flag for performing PHY and select
1801 * MAC CSR accesses.
1802 **/
e1000_acquire_swflag_ich8lan(struct e1000_hw * hw)1803 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1804 {
1805 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1806 s32 ret_val = E1000_SUCCESS;
1807
1808 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1809
1810 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1811
1812 while (timeout) {
1813 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1814 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1815 break;
1816
1817 msec_delay_irq(1);
1818 timeout--;
1819 }
1820
1821 if (!timeout) {
1822 DEBUGOUT("SW has already locked the resource.\n");
1823 ret_val = -E1000_ERR_CONFIG;
1824 goto out;
1825 }
1826
1827 timeout = SW_FLAG_TIMEOUT;
1828
1829 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1830 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1831
1832 while (timeout) {
1833 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1834 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1835 break;
1836
1837 msec_delay_irq(1);
1838 timeout--;
1839 }
1840
1841 if (!timeout) {
1842 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1843 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1844 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1845 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1846 ret_val = -E1000_ERR_CONFIG;
1847 goto out;
1848 }
1849
1850 out:
1851 if (ret_val)
1852 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1853
1854 return ret_val;
1855 }
1856
1857 /**
1858 * e1000_release_swflag_ich8lan - Release software control flag
1859 * @hw: pointer to the HW structure
1860 *
1861 * Releases the software control flag for performing PHY and select
1862 * MAC CSR accesses.
1863 **/
e1000_release_swflag_ich8lan(struct e1000_hw * hw)1864 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1865 {
1866 u32 extcnf_ctrl;
1867
1868 DEBUGFUNC("e1000_release_swflag_ich8lan");
1869
1870 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1871
1872 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1873 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1874 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1875 } else {
1876 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1877 }
1878
1879 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1880
1881 return;
1882 }
1883
1884 /**
1885 * e1000_check_mng_mode_ich8lan - Checks management mode
1886 * @hw: pointer to the HW structure
1887 *
1888 * This checks if the adapter has any manageability enabled.
1889 * This is a function pointer entry point only called by read/write
1890 * routines for the PHY and NVM parts.
1891 **/
e1000_check_mng_mode_ich8lan(struct e1000_hw * hw)1892 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1893 {
1894 u32 fwsm;
1895
1896 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1897
1898 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1899
1900 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1901 ((fwsm & E1000_FWSM_MODE_MASK) ==
1902 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1903 }
1904
1905 /**
1906 * e1000_check_mng_mode_pchlan - Checks management mode
1907 * @hw: pointer to the HW structure
1908 *
1909 * This checks if the adapter has iAMT enabled.
1910 * This is a function pointer entry point only called by read/write
1911 * routines for the PHY and NVM parts.
1912 **/
e1000_check_mng_mode_pchlan(struct e1000_hw * hw)1913 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1914 {
1915 u32 fwsm;
1916
1917 DEBUGFUNC("e1000_check_mng_mode_pchlan");
1918
1919 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1920
1921 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1922 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1923 }
1924
1925 /**
1926 * e1000_rar_set_pch2lan - Set receive address register
1927 * @hw: pointer to the HW structure
1928 * @addr: pointer to the receive address
1929 * @index: receive address array register
1930 *
1931 * Sets the receive address array register at index to the address passed
1932 * in by addr. For 82579, RAR[0] is the base address register that is to
1933 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1934 * Use SHRA[0-3] in place of those reserved for ME.
1935 **/
e1000_rar_set_pch2lan(struct e1000_hw * hw,u8 * addr,u32 index)1936 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1937 {
1938 u32 rar_low, rar_high;
1939
1940 DEBUGFUNC("e1000_rar_set_pch2lan");
1941
1942 /* HW expects these in little endian so we reverse the byte order
1943 * from network order (big endian) to little endian
1944 */
1945 rar_low = ((u32) addr[0] |
1946 ((u32) addr[1] << 8) |
1947 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1948
1949 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1950
1951 /* If MAC address zero, no need to set the AV bit */
1952 if (rar_low || rar_high)
1953 rar_high |= E1000_RAH_AV;
1954
1955 if (index == 0) {
1956 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1957 E1000_WRITE_FLUSH(hw);
1958 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1959 E1000_WRITE_FLUSH(hw);
1960 return E1000_SUCCESS;
1961 }
1962
1963 /* RAR[1-6] are owned by manageability. Skip those and program the
1964 * next address into the SHRA register array.
1965 */
1966 if (index < (u32) (hw->mac.rar_entry_count)) {
1967 s32 ret_val;
1968
1969 ret_val = e1000_acquire_swflag_ich8lan(hw);
1970 if (ret_val)
1971 goto out;
1972
1973 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1974 E1000_WRITE_FLUSH(hw);
1975 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1976 E1000_WRITE_FLUSH(hw);
1977
1978 e1000_release_swflag_ich8lan(hw);
1979
1980 /* verify the register updates */
1981 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1982 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1983 return E1000_SUCCESS;
1984
1985 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1986 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1987 }
1988
1989 out:
1990 DEBUGOUT1("Failed to write receive address at index %d\n", index);
1991 return -E1000_ERR_CONFIG;
1992 }
1993
1994 /**
1995 * e1000_rar_set_pch_lpt - Set receive address registers
1996 * @hw: pointer to the HW structure
1997 * @addr: pointer to the receive address
1998 * @index: receive address array register
1999 *
2000 * Sets the receive address register array at index to the address passed
2001 * in by addr. For LPT, RAR[0] is the base address register that is to
2002 * contain the MAC address. SHRA[0-10] are the shared receive address
2003 * registers that are shared between the Host and manageability engine (ME).
2004 **/
e1000_rar_set_pch_lpt(struct e1000_hw * hw,u8 * addr,u32 index)2005 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2006 {
2007 u32 rar_low, rar_high;
2008 u32 wlock_mac;
2009
2010 DEBUGFUNC("e1000_rar_set_pch_lpt");
2011
2012 /* HW expects these in little endian so we reverse the byte order
2013 * from network order (big endian) to little endian
2014 */
2015 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2016 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2017
2018 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2019
2020 /* If MAC address zero, no need to set the AV bit */
2021 if (rar_low || rar_high)
2022 rar_high |= E1000_RAH_AV;
2023
2024 if (index == 0) {
2025 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2026 E1000_WRITE_FLUSH(hw);
2027 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2028 E1000_WRITE_FLUSH(hw);
2029 return E1000_SUCCESS;
2030 }
2031
2032 /* The manageability engine (ME) can lock certain SHRAR registers that
2033 * it is using - those registers are unavailable for use.
2034 */
2035 if (index < hw->mac.rar_entry_count) {
2036 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2037 E1000_FWSM_WLOCK_MAC_MASK;
2038 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2039
2040 /* Check if all SHRAR registers are locked */
2041 if (wlock_mac == 1)
2042 goto out;
2043
2044 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2045 s32 ret_val;
2046
2047 ret_val = e1000_acquire_swflag_ich8lan(hw);
2048
2049 if (ret_val)
2050 goto out;
2051
2052 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2053 rar_low);
2054 E1000_WRITE_FLUSH(hw);
2055 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2056 rar_high);
2057 E1000_WRITE_FLUSH(hw);
2058
2059 e1000_release_swflag_ich8lan(hw);
2060
2061 /* verify the register updates */
2062 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2063 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2064 return E1000_SUCCESS;
2065 }
2066 }
2067
2068 out:
2069 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2070 return -E1000_ERR_CONFIG;
2071 }
2072
2073 /**
2074 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2075 * @hw: pointer to the HW structure
2076 * @mc_addr_list: array of multicast addresses to program
2077 * @mc_addr_count: number of multicast addresses to program
2078 *
2079 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2080 * The caller must have a packed mc_addr_list of multicast addresses.
2081 **/
e1000_update_mc_addr_list_pch2lan(struct e1000_hw * hw,u8 * mc_addr_list,u32 mc_addr_count)2082 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2083 u8 *mc_addr_list,
2084 u32 mc_addr_count)
2085 {
2086 u16 phy_reg = 0;
2087 int i;
2088 s32 ret_val;
2089
2090 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2091
2092 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2093
2094 ret_val = hw->phy.ops.acquire(hw);
2095 if (ret_val)
2096 return;
2097
2098 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2099 if (ret_val)
2100 goto release;
2101
2102 for (i = 0; i < hw->mac.mta_reg_count; i++) {
2103 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2104 (u16)(hw->mac.mta_shadow[i] &
2105 0xFFFF));
2106 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2107 (u16)((hw->mac.mta_shadow[i] >> 16) &
2108 0xFFFF));
2109 }
2110
2111 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2112
2113 release:
2114 hw->phy.ops.release(hw);
2115 }
2116
2117 /**
2118 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2119 * @hw: pointer to the HW structure
2120 *
2121 * Checks if firmware is blocking the reset of the PHY.
2122 * This is a function pointer entry point only called by
2123 * reset routines.
2124 **/
e1000_check_reset_block_ich8lan(struct e1000_hw * hw)2125 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2126 {
2127 u32 fwsm;
2128 bool blocked = false;
2129 int i = 0;
2130
2131 DEBUGFUNC("e1000_check_reset_block_ich8lan");
2132
2133 do {
2134 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2135 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2136 blocked = true;
2137 msec_delay(10);
2138 continue;
2139 }
2140 blocked = false;
2141 } while (blocked && (i++ < 30));
2142 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2143 }
2144
2145 /**
2146 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2147 * @hw: pointer to the HW structure
2148 *
2149 * Assumes semaphore already acquired.
2150 *
2151 **/
e1000_write_smbus_addr(struct e1000_hw * hw)2152 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2153 {
2154 u16 phy_data;
2155 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2156 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2157 E1000_STRAP_SMT_FREQ_SHIFT;
2158 s32 ret_val;
2159
2160 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2161
2162 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2163 if (ret_val)
2164 return ret_val;
2165
2166 phy_data &= ~HV_SMB_ADDR_MASK;
2167 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2168 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2169
2170 if (hw->phy.type == e1000_phy_i217) {
2171 /* Restore SMBus frequency */
2172 if (freq--) {
2173 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2174 phy_data |= (freq & (1 << 0)) <<
2175 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2176 phy_data |= (freq & (1 << 1)) <<
2177 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2178 } else {
2179 DEBUGOUT("Unsupported SMB frequency in PHY\n");
2180 }
2181 }
2182
2183 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2184 }
2185
2186 /**
2187 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2188 * @hw: pointer to the HW structure
2189 *
2190 * SW should configure the LCD from the NVM extended configuration region
2191 * as a workaround for certain parts.
2192 **/
e1000_sw_lcd_config_ich8lan(struct e1000_hw * hw)2193 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2194 {
2195 struct e1000_phy_info *phy = &hw->phy;
2196 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2197 s32 ret_val = E1000_SUCCESS;
2198 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2199
2200 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2201
2202 /* Initialize the PHY from the NVM on ICH platforms. This
2203 * is needed due to an issue where the NVM configuration is
2204 * not properly autoloaded after power transitions.
2205 * Therefore, after each PHY reset, we will load the
2206 * configuration data out of the NVM manually.
2207 */
2208 switch (hw->mac.type) {
2209 case e1000_ich8lan:
2210 if (phy->type != e1000_phy_igp_3)
2211 return ret_val;
2212
2213 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2214 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2215 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2216 break;
2217 }
2218 /* Fall-thru */
2219 case e1000_pchlan:
2220 case e1000_pch2lan:
2221 case e1000_pch_lpt:
2222 case e1000_pch_spt:
2223 case e1000_pch_cnp:
2224 case e1000_pch_adp:
2225 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2226 break;
2227 default:
2228 return ret_val;
2229 }
2230
2231 ret_val = hw->phy.ops.acquire(hw);
2232 if (ret_val)
2233 return ret_val;
2234
2235 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2236 if (!(data & sw_cfg_mask))
2237 goto release;
2238
2239 /* Make sure HW does not configure LCD from PHY
2240 * extended configuration before SW configuration
2241 */
2242 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2243 if ((hw->mac.type < e1000_pch2lan) &&
2244 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2245 goto release;
2246
2247 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2248 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2249 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2250 if (!cnf_size)
2251 goto release;
2252
2253 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2254 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2255
2256 if (((hw->mac.type == e1000_pchlan) &&
2257 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2258 (hw->mac.type > e1000_pchlan)) {
2259 /* HW configures the SMBus address and LEDs when the
2260 * OEM and LCD Write Enable bits are set in the NVM.
2261 * When both NVM bits are cleared, SW will configure
2262 * them instead.
2263 */
2264 ret_val = e1000_write_smbus_addr(hw);
2265 if (ret_val)
2266 goto release;
2267
2268 data = E1000_READ_REG(hw, E1000_LEDCTL);
2269 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2270 (u16)data);
2271 if (ret_val)
2272 goto release;
2273 }
2274
2275 /* Configure LCD from extended configuration region. */
2276
2277 /* cnf_base_addr is in DWORD */
2278 word_addr = (u16)(cnf_base_addr << 1);
2279
2280 for (i = 0; i < cnf_size; i++) {
2281 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2282 ®_data);
2283 if (ret_val)
2284 goto release;
2285
2286 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2287 1, ®_addr);
2288 if (ret_val)
2289 goto release;
2290
2291 /* Save off the PHY page for future writes. */
2292 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2293 phy_page = reg_data;
2294 continue;
2295 }
2296
2297 reg_addr &= PHY_REG_MASK;
2298 reg_addr |= phy_page;
2299
2300 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2301 reg_data);
2302 if (ret_val)
2303 goto release;
2304 }
2305
2306 release:
2307 hw->phy.ops.release(hw);
2308 return ret_val;
2309 }
2310
2311 /**
2312 * e1000_k1_gig_workaround_hv - K1 Si workaround
2313 * @hw: pointer to the HW structure
2314 * @link: link up bool flag
2315 *
2316 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2317 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2318 * If link is down, the function will restore the default K1 setting located
2319 * in the NVM.
2320 **/
e1000_k1_gig_workaround_hv(struct e1000_hw * hw,bool link)2321 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2322 {
2323 s32 ret_val = E1000_SUCCESS;
2324 u16 status_reg = 0;
2325 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2326
2327 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2328
2329 if (hw->mac.type != e1000_pchlan)
2330 return E1000_SUCCESS;
2331
2332 /* Wrap the whole flow with the sw flag */
2333 ret_val = hw->phy.ops.acquire(hw);
2334 if (ret_val)
2335 return ret_val;
2336
2337 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2338 if (link) {
2339 if (hw->phy.type == e1000_phy_82578) {
2340 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2341 &status_reg);
2342 if (ret_val)
2343 goto release;
2344
2345 status_reg &= (BM_CS_STATUS_LINK_UP |
2346 BM_CS_STATUS_RESOLVED |
2347 BM_CS_STATUS_SPEED_MASK);
2348
2349 if (status_reg == (BM_CS_STATUS_LINK_UP |
2350 BM_CS_STATUS_RESOLVED |
2351 BM_CS_STATUS_SPEED_1000))
2352 k1_enable = false;
2353 }
2354
2355 if (hw->phy.type == e1000_phy_82577) {
2356 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2357 &status_reg);
2358 if (ret_val)
2359 goto release;
2360
2361 status_reg &= (HV_M_STATUS_LINK_UP |
2362 HV_M_STATUS_AUTONEG_COMPLETE |
2363 HV_M_STATUS_SPEED_MASK);
2364
2365 if (status_reg == (HV_M_STATUS_LINK_UP |
2366 HV_M_STATUS_AUTONEG_COMPLETE |
2367 HV_M_STATUS_SPEED_1000))
2368 k1_enable = false;
2369 }
2370
2371 /* Link stall fix for link up */
2372 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2373 0x0100);
2374 if (ret_val)
2375 goto release;
2376
2377 } else {
2378 /* Link stall fix for link down */
2379 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2380 0x4100);
2381 if (ret_val)
2382 goto release;
2383 }
2384
2385 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2386
2387 release:
2388 hw->phy.ops.release(hw);
2389
2390 return ret_val;
2391 }
2392
2393 /**
2394 * e1000_configure_k1_ich8lan - Configure K1 power state
2395 * @hw: pointer to the HW structure
2396 * @k1_enable: K1 state to configure
2397 *
2398 * Configure the K1 power state based on the provided parameter.
2399 * Assumes semaphore already acquired.
2400 *
2401 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2402 **/
e1000_configure_k1_ich8lan(struct e1000_hw * hw,bool k1_enable)2403 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2404 {
2405 s32 ret_val;
2406 u32 ctrl_reg = 0;
2407 u32 ctrl_ext = 0;
2408 u32 reg = 0;
2409 u16 kmrn_reg = 0;
2410
2411 DEBUGFUNC("e1000_configure_k1_ich8lan");
2412
2413 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2414 &kmrn_reg);
2415 if (ret_val)
2416 return ret_val;
2417
2418 if (k1_enable)
2419 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2420 else
2421 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2422
2423 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2424 kmrn_reg);
2425 if (ret_val)
2426 return ret_val;
2427
2428 usec_delay(20);
2429 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2430 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2431
2432 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2433 reg |= E1000_CTRL_FRCSPD;
2434 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2435
2436 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2437 E1000_WRITE_FLUSH(hw);
2438 usec_delay(20);
2439 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2440 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2441 E1000_WRITE_FLUSH(hw);
2442 usec_delay(20);
2443
2444 return E1000_SUCCESS;
2445 }
2446
2447 /**
2448 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2449 * @hw: pointer to the HW structure
2450 * @d0_state: boolean if entering d0 or d3 device state
2451 *
2452 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2453 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2454 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2455 **/
e1000_oem_bits_config_ich8lan(struct e1000_hw * hw,bool d0_state)2456 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2457 {
2458 s32 ret_val = 0;
2459 u32 mac_reg;
2460 u16 oem_reg;
2461
2462 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2463
2464 if (hw->mac.type < e1000_pchlan)
2465 return ret_val;
2466
2467 ret_val = hw->phy.ops.acquire(hw);
2468 if (ret_val)
2469 return ret_val;
2470
2471 if (hw->mac.type == e1000_pchlan) {
2472 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2473 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2474 goto release;
2475 }
2476
2477 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2478 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2479 goto release;
2480
2481 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2482
2483 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2484 if (ret_val)
2485 goto release;
2486
2487 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2488
2489 if (d0_state) {
2490 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2491 oem_reg |= HV_OEM_BITS_GBE_DIS;
2492
2493 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2494 oem_reg |= HV_OEM_BITS_LPLU;
2495 } else {
2496 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2497 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2498 oem_reg |= HV_OEM_BITS_GBE_DIS;
2499
2500 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2501 E1000_PHY_CTRL_NOND0A_LPLU))
2502 oem_reg |= HV_OEM_BITS_LPLU;
2503 }
2504
2505 /* Set Restart auto-neg to activate the bits */
2506 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2507 !hw->phy.ops.check_reset_block(hw))
2508 oem_reg |= HV_OEM_BITS_RESTART_AN;
2509
2510 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2511
2512 release:
2513 hw->phy.ops.release(hw);
2514
2515 return ret_val;
2516 }
2517
2518
2519 /**
2520 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2521 * @hw: pointer to the HW structure
2522 **/
e1000_set_mdio_slow_mode_hv(struct e1000_hw * hw)2523 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2524 {
2525 s32 ret_val;
2526 u16 data;
2527
2528 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2529
2530 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2531 if (ret_val)
2532 return ret_val;
2533
2534 data |= HV_KMRN_MDIO_SLOW;
2535
2536 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2537
2538 return ret_val;
2539 }
2540
2541 /**
2542 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2543 * done after every PHY reset.
2544 * @hw: pointer to the HW structure
2545 **/
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw * hw)2546 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2547 {
2548 s32 ret_val = E1000_SUCCESS;
2549 u16 phy_data;
2550
2551 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2552
2553 if (hw->mac.type != e1000_pchlan)
2554 return E1000_SUCCESS;
2555
2556 /* Set MDIO slow mode before any other MDIO access */
2557 if (hw->phy.type == e1000_phy_82577) {
2558 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2559 if (ret_val)
2560 return ret_val;
2561 }
2562
2563 if (((hw->phy.type == e1000_phy_82577) &&
2564 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2565 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2566 /* Disable generation of early preamble */
2567 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2568 if (ret_val)
2569 return ret_val;
2570
2571 /* Preamble tuning for SSC */
2572 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2573 0xA204);
2574 if (ret_val)
2575 return ret_val;
2576 }
2577
2578 if (hw->phy.type == e1000_phy_82578) {
2579 /* Return registers to default by doing a soft reset then
2580 * writing 0x3140 to the control register.
2581 */
2582 if (hw->phy.revision < 2) {
2583 e1000_phy_sw_reset_generic(hw);
2584 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2585 0x3140);
2586 }
2587 }
2588
2589 /* Select page 0 */
2590 ret_val = hw->phy.ops.acquire(hw);
2591 if (ret_val)
2592 return ret_val;
2593
2594 hw->phy.addr = 1;
2595 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2596 hw->phy.ops.release(hw);
2597 if (ret_val)
2598 return ret_val;
2599
2600 /* Configure the K1 Si workaround during phy reset assuming there is
2601 * link so that it disables K1 if link is in 1Gbps.
2602 */
2603 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2604 if (ret_val)
2605 return ret_val;
2606
2607 /* Workaround for link disconnects on a busy hub in half duplex */
2608 ret_val = hw->phy.ops.acquire(hw);
2609 if (ret_val)
2610 return ret_val;
2611 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2612 if (ret_val)
2613 goto release;
2614 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2615 phy_data & 0x00FF);
2616 if (ret_val)
2617 goto release;
2618
2619 /* set MSE higher to enable link to stay up when noise is high */
2620 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2621 release:
2622 hw->phy.ops.release(hw);
2623
2624 return ret_val;
2625 }
2626
2627 /**
2628 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2629 * @hw: pointer to the HW structure
2630 **/
e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw * hw)2631 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2632 {
2633 u32 mac_reg;
2634 u16 i, phy_reg = 0;
2635 s32 ret_val;
2636
2637 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2638
2639 ret_val = hw->phy.ops.acquire(hw);
2640 if (ret_val)
2641 return;
2642 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2643 if (ret_val)
2644 goto release;
2645
2646 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2647 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2648 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2649 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2650 (u16)(mac_reg & 0xFFFF));
2651 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2652 (u16)((mac_reg >> 16) & 0xFFFF));
2653
2654 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2655 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2656 (u16)(mac_reg & 0xFFFF));
2657 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2658 (u16)((mac_reg & E1000_RAH_AV)
2659 >> 16));
2660 }
2661
2662 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2663
2664 release:
2665 hw->phy.ops.release(hw);
2666 }
2667
e1000_calc_rx_da_crc(u8 mac[])2668 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2669 {
2670 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2671 u32 i, j, mask, crc;
2672
2673 DEBUGFUNC("e1000_calc_rx_da_crc");
2674
2675 crc = 0xffffffff;
2676 for (i = 0; i < 6; i++) {
2677 crc = crc ^ mac[i];
2678 for (j = 8; j > 0; j--) {
2679 mask = (crc & 1) * (-1);
2680 crc = (crc >> 1) ^ (poly & mask);
2681 }
2682 }
2683 return ~crc;
2684 }
2685
2686 /**
2687 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2688 * with 82579 PHY
2689 * @hw: pointer to the HW structure
2690 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2691 **/
e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw * hw,bool enable)2692 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2693 {
2694 s32 ret_val = E1000_SUCCESS;
2695 u16 phy_reg, data;
2696 u32 mac_reg;
2697 u16 i;
2698
2699 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2700
2701 if (hw->mac.type < e1000_pch2lan)
2702 return E1000_SUCCESS;
2703
2704 /* disable Rx path while enabling/disabling workaround */
2705 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2706 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2707 phy_reg | (1 << 14));
2708 if (ret_val)
2709 return ret_val;
2710
2711 if (enable) {
2712 /* Write Rx addresses (rar_entry_count for RAL/H, and
2713 * SHRAL/H) and initial CRC values to the MAC
2714 */
2715 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2716 u8 mac_addr[ETH_ADDR_LEN] = {0};
2717 u32 addr_high, addr_low;
2718
2719 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2720 if (!(addr_high & E1000_RAH_AV))
2721 continue;
2722 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2723 mac_addr[0] = (addr_low & 0xFF);
2724 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2725 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2726 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2727 mac_addr[4] = (addr_high & 0xFF);
2728 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2729
2730 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2731 e1000_calc_rx_da_crc(mac_addr));
2732 }
2733
2734 /* Write Rx addresses to the PHY */
2735 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2736
2737 /* Enable jumbo frame workaround in the MAC */
2738 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2739 mac_reg &= ~(1 << 14);
2740 mac_reg |= (7 << 15);
2741 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2742
2743 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2744 mac_reg |= E1000_RCTL_SECRC;
2745 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2746
2747 ret_val = e1000_read_kmrn_reg_generic(hw,
2748 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2749 &data);
2750 if (ret_val)
2751 return ret_val;
2752 ret_val = e1000_write_kmrn_reg_generic(hw,
2753 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2754 data | (1 << 0));
2755 if (ret_val)
2756 return ret_val;
2757 ret_val = e1000_read_kmrn_reg_generic(hw,
2758 E1000_KMRNCTRLSTA_HD_CTRL,
2759 &data);
2760 if (ret_val)
2761 return ret_val;
2762 data &= ~(0xF << 8);
2763 data |= (0xB << 8);
2764 ret_val = e1000_write_kmrn_reg_generic(hw,
2765 E1000_KMRNCTRLSTA_HD_CTRL,
2766 data);
2767 if (ret_val)
2768 return ret_val;
2769
2770 /* Enable jumbo frame workaround in the PHY */
2771 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2772 data &= ~(0x7F << 5);
2773 data |= (0x37 << 5);
2774 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2775 if (ret_val)
2776 return ret_val;
2777 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2778 data &= ~(1 << 13);
2779 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2780 if (ret_val)
2781 return ret_val;
2782 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2783 data &= ~(0x3FF << 2);
2784 data |= (E1000_TX_PTR_GAP << 2);
2785 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2786 if (ret_val)
2787 return ret_val;
2788 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2789 if (ret_val)
2790 return ret_val;
2791 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2792 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2793 (1 << 10));
2794 if (ret_val)
2795 return ret_val;
2796 } else {
2797 /* Write MAC register values back to h/w defaults */
2798 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2799 mac_reg &= ~(0xF << 14);
2800 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2801
2802 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2803 mac_reg &= ~E1000_RCTL_SECRC;
2804 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2805
2806 ret_val = e1000_read_kmrn_reg_generic(hw,
2807 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2808 &data);
2809 if (ret_val)
2810 return ret_val;
2811 ret_val = e1000_write_kmrn_reg_generic(hw,
2812 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2813 data & ~(1 << 0));
2814 if (ret_val)
2815 return ret_val;
2816 ret_val = e1000_read_kmrn_reg_generic(hw,
2817 E1000_KMRNCTRLSTA_HD_CTRL,
2818 &data);
2819 if (ret_val)
2820 return ret_val;
2821 data &= ~(0xF << 8);
2822 data |= (0xB << 8);
2823 ret_val = e1000_write_kmrn_reg_generic(hw,
2824 E1000_KMRNCTRLSTA_HD_CTRL,
2825 data);
2826 if (ret_val)
2827 return ret_val;
2828
2829 /* Write PHY register values back to h/w defaults */
2830 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2831 data &= ~(0x7F << 5);
2832 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2833 if (ret_val)
2834 return ret_val;
2835 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2836 data |= (1 << 13);
2837 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2838 if (ret_val)
2839 return ret_val;
2840 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2841 data &= ~(0x3FF << 2);
2842 data |= (0x8 << 2);
2843 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2844 if (ret_val)
2845 return ret_val;
2846 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2847 if (ret_val)
2848 return ret_val;
2849 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2850 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2851 ~(1 << 10));
2852 if (ret_val)
2853 return ret_val;
2854 }
2855
2856 /* re-enable Rx path after enabling/disabling workaround */
2857 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2858 ~(1 << 14));
2859 }
2860
2861 /**
2862 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2863 * done after every PHY reset.
2864 * @hw: pointer to the HW structure
2865 **/
e1000_lv_phy_workarounds_ich8lan(struct e1000_hw * hw)2866 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2867 {
2868 s32 ret_val = E1000_SUCCESS;
2869
2870 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2871
2872 if (hw->mac.type != e1000_pch2lan)
2873 return E1000_SUCCESS;
2874
2875 /* Set MDIO slow mode before any other MDIO access */
2876 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2877 if (ret_val)
2878 return ret_val;
2879
2880 ret_val = hw->phy.ops.acquire(hw);
2881 if (ret_val)
2882 return ret_val;
2883 /* set MSE higher to enable link to stay up when noise is high */
2884 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2885 if (ret_val)
2886 goto release;
2887 /* drop link after 5 times MSE threshold was reached */
2888 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2889 release:
2890 hw->phy.ops.release(hw);
2891
2892 return ret_val;
2893 }
2894
2895 /**
2896 * e1000_k1_gig_workaround_lv - K1 Si workaround
2897 * @hw: pointer to the HW structure
2898 *
2899 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2900 * Disable K1 for 1000 and 100 speeds
2901 **/
e1000_k1_workaround_lv(struct e1000_hw * hw)2902 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2903 {
2904 s32 ret_val = E1000_SUCCESS;
2905 u16 status_reg = 0;
2906
2907 DEBUGFUNC("e1000_k1_workaround_lv");
2908
2909 if (hw->mac.type != e1000_pch2lan)
2910 return E1000_SUCCESS;
2911
2912 /* Set K1 beacon duration based on 10Mbs speed */
2913 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2914 if (ret_val)
2915 return ret_val;
2916
2917 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2918 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2919 if (status_reg &
2920 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2921 u16 pm_phy_reg;
2922
2923 /* LV 1G/100 Packet drop issue wa */
2924 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2925 &pm_phy_reg);
2926 if (ret_val)
2927 return ret_val;
2928 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2929 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2930 pm_phy_reg);
2931 if (ret_val)
2932 return ret_val;
2933 } else {
2934 u32 mac_reg;
2935 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2936 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2937 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2938 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2939 }
2940 }
2941
2942 return ret_val;
2943 }
2944
2945 /**
2946 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2947 * @hw: pointer to the HW structure
2948 * @gate: boolean set to true to gate, false to ungate
2949 *
2950 * Gate/ungate the automatic PHY configuration via hardware; perform
2951 * the configuration via software instead.
2952 **/
e1000_gate_hw_phy_config_ich8lan(struct e1000_hw * hw,bool gate)2953 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2954 {
2955 u32 extcnf_ctrl;
2956
2957 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2958
2959 if (hw->mac.type < e1000_pch2lan)
2960 return;
2961
2962 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2963
2964 if (gate)
2965 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2966 else
2967 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2968
2969 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2970 }
2971
2972 /**
2973 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2974 * @hw: pointer to the HW structure
2975 *
2976 * Check the appropriate indication the MAC has finished configuring the
2977 * PHY after a software reset.
2978 **/
e1000_lan_init_done_ich8lan(struct e1000_hw * hw)2979 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2980 {
2981 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2982
2983 DEBUGFUNC("e1000_lan_init_done_ich8lan");
2984
2985 /* Wait for basic configuration completes before proceeding */
2986 do {
2987 data = E1000_READ_REG(hw, E1000_STATUS);
2988 data &= E1000_STATUS_LAN_INIT_DONE;
2989 usec_delay(100);
2990 } while ((!data) && --loop);
2991
2992 /* If basic configuration is incomplete before the above loop
2993 * count reaches 0, loading the configuration from NVM will
2994 * leave the PHY in a bad state possibly resulting in no link.
2995 */
2996 if (loop == 0)
2997 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2998
2999 /* Clear the Init Done bit for the next init event */
3000 data = E1000_READ_REG(hw, E1000_STATUS);
3001 data &= ~E1000_STATUS_LAN_INIT_DONE;
3002 E1000_WRITE_REG(hw, E1000_STATUS, data);
3003 }
3004
3005 /**
3006 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3007 * @hw: pointer to the HW structure
3008 **/
e1000_post_phy_reset_ich8lan(struct e1000_hw * hw)3009 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3010 {
3011 s32 ret_val = E1000_SUCCESS;
3012 u16 reg;
3013
3014 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3015
3016 if (hw->phy.ops.check_reset_block(hw))
3017 return E1000_SUCCESS;
3018
3019 /* Allow time for h/w to get to quiescent state after reset */
3020 msec_delay(10);
3021
3022 /* Perform any necessary post-reset workarounds */
3023 switch (hw->mac.type) {
3024 case e1000_pchlan:
3025 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3026 if (ret_val)
3027 return ret_val;
3028 break;
3029 case e1000_pch2lan:
3030 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3031 if (ret_val)
3032 return ret_val;
3033 break;
3034 default:
3035 break;
3036 }
3037
3038 /* Clear the host wakeup bit after lcd reset */
3039 if (hw->mac.type >= e1000_pchlan) {
3040 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
3041 reg &= ~BM_WUC_HOST_WU_BIT;
3042 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3043 }
3044
3045 /* Configure the LCD with the extended configuration region in NVM */
3046 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3047 if (ret_val)
3048 return ret_val;
3049
3050 /* Configure the LCD with the OEM bits in NVM */
3051 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
3052
3053 if (hw->mac.type == e1000_pch2lan) {
3054 /* Ungate automatic PHY configuration on non-managed 82579 */
3055 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3056 E1000_ICH_FWSM_FW_VALID)) {
3057 msec_delay(10);
3058 e1000_gate_hw_phy_config_ich8lan(hw, false);
3059 }
3060
3061 /* Set EEE LPI Update Timer to 200usec */
3062 ret_val = hw->phy.ops.acquire(hw);
3063 if (ret_val)
3064 return ret_val;
3065 ret_val = e1000_write_emi_reg_locked(hw,
3066 I82579_LPI_UPDATE_TIMER,
3067 0x1387);
3068 hw->phy.ops.release(hw);
3069 }
3070
3071 return ret_val;
3072 }
3073
3074 /**
3075 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3076 * @hw: pointer to the HW structure
3077 *
3078 * Resets the PHY
3079 * This is a function pointer entry point called by drivers
3080 * or other shared routines.
3081 **/
e1000_phy_hw_reset_ich8lan(struct e1000_hw * hw)3082 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3083 {
3084 s32 ret_val = E1000_SUCCESS;
3085
3086 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3087
3088 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3089 if ((hw->mac.type == e1000_pch2lan) &&
3090 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3091 e1000_gate_hw_phy_config_ich8lan(hw, true);
3092
3093 ret_val = e1000_phy_hw_reset_generic(hw);
3094 if (ret_val)
3095 return ret_val;
3096
3097 return e1000_post_phy_reset_ich8lan(hw);
3098 }
3099
3100 /**
3101 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3102 * @hw: pointer to the HW structure
3103 * @active: true to enable LPLU, false to disable
3104 *
3105 * Sets the LPLU state according to the active flag. For PCH, if OEM write
3106 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3107 * the phy speed. This function will manually set the LPLU bit and restart
3108 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3109 * since it configures the same bit.
3110 **/
e1000_set_lplu_state_pchlan(struct e1000_hw * hw,bool active)3111 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3112 {
3113 s32 ret_val;
3114 u16 oem_reg;
3115
3116 DEBUGFUNC("e1000_set_lplu_state_pchlan");
3117 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3118 if (ret_val)
3119 return ret_val;
3120
3121 if (active)
3122 oem_reg |= HV_OEM_BITS_LPLU;
3123 else
3124 oem_reg &= ~HV_OEM_BITS_LPLU;
3125
3126 if (!hw->phy.ops.check_reset_block(hw))
3127 oem_reg |= HV_OEM_BITS_RESTART_AN;
3128
3129 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3130 }
3131
3132 /**
3133 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3134 * @hw: pointer to the HW structure
3135 * @active: true to enable LPLU, false to disable
3136 *
3137 * Sets the LPLU D0 state according to the active flag. When
3138 * activating LPLU this function also disables smart speed
3139 * and vice versa. LPLU will not be activated unless the
3140 * device autonegotiation advertisement meets standards of
3141 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3142 * This is a function pointer entry point only called by
3143 * PHY setup routines.
3144 **/
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw * hw,bool active)3145 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3146 {
3147 struct e1000_phy_info *phy = &hw->phy;
3148 u32 phy_ctrl;
3149 s32 ret_val = E1000_SUCCESS;
3150 u16 data;
3151
3152 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3153
3154 if (phy->type == e1000_phy_ife)
3155 return E1000_SUCCESS;
3156
3157 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3158
3159 if (active) {
3160 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3161 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3162
3163 if (phy->type != e1000_phy_igp_3)
3164 return E1000_SUCCESS;
3165
3166 /* Call gig speed drop workaround on LPLU before accessing
3167 * any PHY registers
3168 */
3169 if (hw->mac.type == e1000_ich8lan)
3170 e1000_gig_downshift_workaround_ich8lan(hw);
3171
3172 /* When LPLU is enabled, we should disable SmartSpeed */
3173 ret_val = phy->ops.read_reg(hw,
3174 IGP01E1000_PHY_PORT_CONFIG,
3175 &data);
3176 if (ret_val)
3177 return ret_val;
3178 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3179 ret_val = phy->ops.write_reg(hw,
3180 IGP01E1000_PHY_PORT_CONFIG,
3181 data);
3182 if (ret_val)
3183 return ret_val;
3184 } else {
3185 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3186 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3187
3188 if (phy->type != e1000_phy_igp_3)
3189 return E1000_SUCCESS;
3190
3191 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3192 * during Dx states where the power conservation is most
3193 * important. During driver activity we should enable
3194 * SmartSpeed, so performance is maintained.
3195 */
3196 if (phy->smart_speed == e1000_smart_speed_on) {
3197 ret_val = phy->ops.read_reg(hw,
3198 IGP01E1000_PHY_PORT_CONFIG,
3199 &data);
3200 if (ret_val)
3201 return ret_val;
3202
3203 data |= IGP01E1000_PSCFR_SMART_SPEED;
3204 ret_val = phy->ops.write_reg(hw,
3205 IGP01E1000_PHY_PORT_CONFIG,
3206 data);
3207 if (ret_val)
3208 return ret_val;
3209 } else if (phy->smart_speed == e1000_smart_speed_off) {
3210 ret_val = phy->ops.read_reg(hw,
3211 IGP01E1000_PHY_PORT_CONFIG,
3212 &data);
3213 if (ret_val)
3214 return ret_val;
3215
3216 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3217 ret_val = phy->ops.write_reg(hw,
3218 IGP01E1000_PHY_PORT_CONFIG,
3219 data);
3220 if (ret_val)
3221 return ret_val;
3222 }
3223 }
3224
3225 return E1000_SUCCESS;
3226 }
3227
3228 /**
3229 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3230 * @hw: pointer to the HW structure
3231 * @active: true to enable LPLU, false to disable
3232 *
3233 * Sets the LPLU D3 state according to the active flag. When
3234 * activating LPLU this function also disables smart speed
3235 * and vice versa. LPLU will not be activated unless the
3236 * device autonegotiation advertisement meets standards of
3237 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3238 * This is a function pointer entry point only called by
3239 * PHY setup routines.
3240 **/
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw * hw,bool active)3241 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3242 {
3243 struct e1000_phy_info *phy = &hw->phy;
3244 u32 phy_ctrl;
3245 s32 ret_val = E1000_SUCCESS;
3246 u16 data;
3247
3248 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3249
3250 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3251
3252 if (!active) {
3253 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3254 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3255
3256 if (phy->type != e1000_phy_igp_3)
3257 return E1000_SUCCESS;
3258
3259 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3260 * during Dx states where the power conservation is most
3261 * important. During driver activity we should enable
3262 * SmartSpeed, so performance is maintained.
3263 */
3264 if (phy->smart_speed == e1000_smart_speed_on) {
3265 ret_val = phy->ops.read_reg(hw,
3266 IGP01E1000_PHY_PORT_CONFIG,
3267 &data);
3268 if (ret_val)
3269 return ret_val;
3270
3271 data |= IGP01E1000_PSCFR_SMART_SPEED;
3272 ret_val = phy->ops.write_reg(hw,
3273 IGP01E1000_PHY_PORT_CONFIG,
3274 data);
3275 if (ret_val)
3276 return ret_val;
3277 } else if (phy->smart_speed == e1000_smart_speed_off) {
3278 ret_val = phy->ops.read_reg(hw,
3279 IGP01E1000_PHY_PORT_CONFIG,
3280 &data);
3281 if (ret_val)
3282 return ret_val;
3283
3284 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3285 ret_val = phy->ops.write_reg(hw,
3286 IGP01E1000_PHY_PORT_CONFIG,
3287 data);
3288 if (ret_val)
3289 return ret_val;
3290 }
3291 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3292 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3293 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3294 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3295 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3296
3297 if (phy->type != e1000_phy_igp_3)
3298 return E1000_SUCCESS;
3299
3300 /* Call gig speed drop workaround on LPLU before accessing
3301 * any PHY registers
3302 */
3303 if (hw->mac.type == e1000_ich8lan)
3304 e1000_gig_downshift_workaround_ich8lan(hw);
3305
3306 /* When LPLU is enabled, we should disable SmartSpeed */
3307 ret_val = phy->ops.read_reg(hw,
3308 IGP01E1000_PHY_PORT_CONFIG,
3309 &data);
3310 if (ret_val)
3311 return ret_val;
3312
3313 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3314 ret_val = phy->ops.write_reg(hw,
3315 IGP01E1000_PHY_PORT_CONFIG,
3316 data);
3317 }
3318
3319 return ret_val;
3320 }
3321
3322 /**
3323 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3324 * @hw: pointer to the HW structure
3325 * @bank: pointer to the variable that returns the active bank
3326 *
3327 * Reads signature byte from the NVM using the flash access registers.
3328 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3329 **/
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw * hw,u32 * bank)3330 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3331 {
3332 u32 eecd;
3333 struct e1000_nvm_info *nvm = &hw->nvm;
3334 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3335 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3336 u32 nvm_dword = 0;
3337 u8 sig_byte = 0;
3338 s32 ret_val;
3339
3340 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3341
3342 switch (hw->mac.type) {
3343 case e1000_pch_spt:
3344 case e1000_pch_cnp:
3345 case e1000_pch_adp:
3346 bank1_offset = nvm->flash_bank_size;
3347 act_offset = E1000_ICH_NVM_SIG_WORD;
3348
3349 /* set bank to 0 in case flash read fails */
3350 *bank = 0;
3351
3352 /* Check bank 0 */
3353 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3354 &nvm_dword);
3355 if (ret_val)
3356 return ret_val;
3357 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3358 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3359 E1000_ICH_NVM_SIG_VALUE) {
3360 *bank = 0;
3361 return E1000_SUCCESS;
3362 }
3363
3364 /* Check bank 1 */
3365 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3366 bank1_offset,
3367 &nvm_dword);
3368 if (ret_val)
3369 return ret_val;
3370 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3371 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3372 E1000_ICH_NVM_SIG_VALUE) {
3373 *bank = 1;
3374 return E1000_SUCCESS;
3375 }
3376
3377 DEBUGOUT("ERROR: No valid NVM bank present\n");
3378 return -E1000_ERR_NVM;
3379 case e1000_ich8lan:
3380 case e1000_ich9lan:
3381 eecd = E1000_READ_REG(hw, E1000_EECD);
3382 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3383 E1000_EECD_SEC1VAL_VALID_MASK) {
3384 if (eecd & E1000_EECD_SEC1VAL)
3385 *bank = 1;
3386 else
3387 *bank = 0;
3388
3389 return E1000_SUCCESS;
3390 }
3391 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3392 /* fall-thru */
3393 default:
3394 /* set bank to 0 in case flash read fails */
3395 *bank = 0;
3396
3397 /* Check bank 0 */
3398 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3399 &sig_byte);
3400 if (ret_val)
3401 return ret_val;
3402 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3403 E1000_ICH_NVM_SIG_VALUE) {
3404 *bank = 0;
3405 return E1000_SUCCESS;
3406 }
3407
3408 /* Check bank 1 */
3409 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3410 bank1_offset,
3411 &sig_byte);
3412 if (ret_val)
3413 return ret_val;
3414 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3415 E1000_ICH_NVM_SIG_VALUE) {
3416 *bank = 1;
3417 return E1000_SUCCESS;
3418 }
3419
3420 DEBUGOUT("ERROR: No valid NVM bank present\n");
3421 return -E1000_ERR_NVM;
3422 }
3423 }
3424
3425 /**
3426 * e1000_read_nvm_spt - NVM access for SPT
3427 * @hw: pointer to the HW structure
3428 * @offset: The offset (in bytes) of the word(s) to read.
3429 * @words: Size of data to read in words.
3430 * @data: pointer to the word(s) to read at offset.
3431 *
3432 * Reads a word(s) from the NVM
3433 **/
e1000_read_nvm_spt(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3434 STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3435 u16 *data)
3436 {
3437 struct e1000_nvm_info *nvm = &hw->nvm;
3438 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3439 u32 act_offset;
3440 s32 ret_val = E1000_SUCCESS;
3441 u32 bank = 0;
3442 u32 dword = 0;
3443 u16 offset_to_read;
3444 u16 i;
3445
3446 DEBUGFUNC("e1000_read_nvm_spt");
3447
3448 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3449 (words == 0)) {
3450 DEBUGOUT("nvm parameter(s) out of bounds\n");
3451 ret_val = -E1000_ERR_NVM;
3452 goto out;
3453 }
3454
3455 nvm->ops.acquire(hw);
3456
3457 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3458 if (ret_val != E1000_SUCCESS) {
3459 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3460 bank = 0;
3461 }
3462
3463 act_offset = (bank) ? nvm->flash_bank_size : 0;
3464 act_offset += offset;
3465
3466 ret_val = E1000_SUCCESS;
3467
3468 for (i = 0; i < words; i += 2) {
3469 if (words - i == 1) {
3470 if (dev_spec->shadow_ram[offset + i].modified) {
3471 data[i] =
3472 dev_spec->shadow_ram[offset + i].value;
3473 } else {
3474 offset_to_read = act_offset + i -
3475 ((act_offset + i) % 2);
3476 ret_val =
3477 e1000_read_flash_dword_ich8lan(hw,
3478 offset_to_read,
3479 &dword);
3480 if (ret_val)
3481 break;
3482 if ((act_offset + i) % 2 == 0)
3483 data[i] = (u16)(dword & 0xFFFF);
3484 else
3485 data[i] = (u16)((dword >> 16) & 0xFFFF);
3486 }
3487 } else {
3488 offset_to_read = act_offset + i;
3489 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3490 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3491 ret_val =
3492 e1000_read_flash_dword_ich8lan(hw,
3493 offset_to_read,
3494 &dword);
3495 if (ret_val)
3496 break;
3497 }
3498 if (dev_spec->shadow_ram[offset + i].modified)
3499 data[i] =
3500 dev_spec->shadow_ram[offset + i].value;
3501 else
3502 data[i] = (u16)(dword & 0xFFFF);
3503 if (dev_spec->shadow_ram[offset + i + 1].modified)
3504 data[i + 1] =
3505 dev_spec->shadow_ram[offset + i + 1].value;
3506 else
3507 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3508 }
3509 }
3510
3511 nvm->ops.release(hw);
3512
3513 out:
3514 if (ret_val)
3515 DEBUGOUT1("NVM read error: %d\n", ret_val);
3516
3517 return ret_val;
3518 }
3519
3520 /**
3521 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3522 * @hw: pointer to the HW structure
3523 * @offset: The offset (in bytes) of the word(s) to read.
3524 * @words: Size of data to read in words
3525 * @data: Pointer to the word(s) to read at offset.
3526 *
3527 * Reads a word(s) from the NVM using the flash access registers.
3528 **/
e1000_read_nvm_ich8lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3529 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3530 u16 *data)
3531 {
3532 struct e1000_nvm_info *nvm = &hw->nvm;
3533 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3534 u32 act_offset;
3535 s32 ret_val = E1000_SUCCESS;
3536 u32 bank = 0;
3537 u16 i, word;
3538
3539 DEBUGFUNC("e1000_read_nvm_ich8lan");
3540
3541 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3542 (words == 0)) {
3543 DEBUGOUT("nvm parameter(s) out of bounds\n");
3544 ret_val = -E1000_ERR_NVM;
3545 goto out;
3546 }
3547
3548 nvm->ops.acquire(hw);
3549
3550 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3551 if (ret_val != E1000_SUCCESS) {
3552 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3553 bank = 0;
3554 }
3555
3556 act_offset = (bank) ? nvm->flash_bank_size : 0;
3557 act_offset += offset;
3558
3559 ret_val = E1000_SUCCESS;
3560 for (i = 0; i < words; i++) {
3561 if (dev_spec->shadow_ram[offset + i].modified) {
3562 data[i] = dev_spec->shadow_ram[offset + i].value;
3563 } else {
3564 ret_val = e1000_read_flash_word_ich8lan(hw,
3565 act_offset + i,
3566 &word);
3567 if (ret_val)
3568 break;
3569 data[i] = word;
3570 }
3571 }
3572
3573 nvm->ops.release(hw);
3574
3575 out:
3576 if (ret_val)
3577 DEBUGOUT1("NVM read error: %d\n", ret_val);
3578
3579 return ret_val;
3580 }
3581
3582 /**
3583 * e1000_flash_cycle_init_ich8lan - Initialize flash
3584 * @hw: pointer to the HW structure
3585 *
3586 * This function does initial flash setup so that a new read/write/erase cycle
3587 * can be started.
3588 **/
e1000_flash_cycle_init_ich8lan(struct e1000_hw * hw)3589 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3590 {
3591 union ich8_hws_flash_status hsfsts;
3592 s32 ret_val = -E1000_ERR_NVM;
3593
3594 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3595
3596 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3597
3598 /* Check if the flash descriptor is valid */
3599 if (!hsfsts.hsf_status.fldesvalid) {
3600 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3601 return -E1000_ERR_NVM;
3602 }
3603
3604 /* Clear FCERR and DAEL in hw status by writing 1 */
3605 hsfsts.hsf_status.flcerr = 1;
3606 hsfsts.hsf_status.dael = 1;
3607 if (hw->mac.type >= e1000_pch_spt)
3608 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3609 hsfsts.regval & 0xFFFF);
3610 else
3611 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3612
3613 /* Either we should have a hardware SPI cycle in progress
3614 * bit to check against, in order to start a new cycle or
3615 * FDONE bit should be changed in the hardware so that it
3616 * is 1 after hardware reset, which can then be used as an
3617 * indication whether a cycle is in progress or has been
3618 * completed.
3619 */
3620
3621 if (!hsfsts.hsf_status.flcinprog) {
3622 /* There is no cycle running at present,
3623 * so we can start a cycle.
3624 * Begin by setting Flash Cycle Done.
3625 */
3626 hsfsts.hsf_status.flcdone = 1;
3627 if (hw->mac.type >= e1000_pch_spt)
3628 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3629 hsfsts.regval & 0xFFFF);
3630 else
3631 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3632 hsfsts.regval);
3633 ret_val = E1000_SUCCESS;
3634 } else {
3635 s32 i;
3636
3637 /* Otherwise poll for sometime so the current
3638 * cycle has a chance to end before giving up.
3639 */
3640 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3641 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3642 ICH_FLASH_HSFSTS);
3643 if (!hsfsts.hsf_status.flcinprog) {
3644 ret_val = E1000_SUCCESS;
3645 break;
3646 }
3647 usec_delay(1);
3648 }
3649 if (ret_val == E1000_SUCCESS) {
3650 /* Successful in waiting for previous cycle to timeout,
3651 * now set the Flash Cycle Done.
3652 */
3653 hsfsts.hsf_status.flcdone = 1;
3654 if (hw->mac.type >= e1000_pch_spt)
3655 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3656 hsfsts.regval & 0xFFFF);
3657 else
3658 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3659 hsfsts.regval);
3660 } else {
3661 DEBUGOUT("Flash controller busy, cannot get access\n");
3662 }
3663 }
3664
3665 return ret_val;
3666 }
3667
3668 /**
3669 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3670 * @hw: pointer to the HW structure
3671 * @timeout: maximum time to wait for completion
3672 *
3673 * This function starts a flash cycle and waits for its completion.
3674 **/
e1000_flash_cycle_ich8lan(struct e1000_hw * hw,u32 timeout)3675 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3676 {
3677 union ich8_hws_flash_ctrl hsflctl;
3678 union ich8_hws_flash_status hsfsts;
3679 u32 i = 0;
3680
3681 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3682
3683 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3684 if (hw->mac.type >= e1000_pch_spt)
3685 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3686 else
3687 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3688 hsflctl.hsf_ctrl.flcgo = 1;
3689
3690 if (hw->mac.type >= e1000_pch_spt)
3691 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3692 hsflctl.regval << 16);
3693 else
3694 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3695
3696 /* wait till FDONE bit is set to 1 */
3697 do {
3698 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3699 if (hsfsts.hsf_status.flcdone)
3700 break;
3701 usec_delay(1);
3702 } while (i++ < timeout);
3703
3704 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3705 return E1000_SUCCESS;
3706
3707 return -E1000_ERR_NVM;
3708 }
3709
3710 /**
3711 * e1000_read_flash_dword_ich8lan - Read dword from flash
3712 * @hw: pointer to the HW structure
3713 * @offset: offset to data location
3714 * @data: pointer to the location for storing the data
3715 *
3716 * Reads the flash dword at offset into data. Offset is converted
3717 * to bytes before read.
3718 **/
e1000_read_flash_dword_ich8lan(struct e1000_hw * hw,u32 offset,u32 * data)3719 STATIC s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3720 u32 *data)
3721 {
3722 DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3723
3724 if (!data)
3725 return -E1000_ERR_NVM;
3726
3727 /* Must convert word offset into bytes. */
3728 offset <<= 1;
3729
3730 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3731 }
3732
3733 /**
3734 * e1000_read_flash_word_ich8lan - Read word from flash
3735 * @hw: pointer to the HW structure
3736 * @offset: offset to data location
3737 * @data: pointer to the location for storing the data
3738 *
3739 * Reads the flash word at offset into data. Offset is converted
3740 * to bytes before read.
3741 **/
e1000_read_flash_word_ich8lan(struct e1000_hw * hw,u32 offset,u16 * data)3742 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3743 u16 *data)
3744 {
3745 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3746
3747 if (!data)
3748 return -E1000_ERR_NVM;
3749
3750 /* Must convert offset into bytes. */
3751 offset <<= 1;
3752
3753 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3754 }
3755
3756 /**
3757 * e1000_read_flash_byte_ich8lan - Read byte from flash
3758 * @hw: pointer to the HW structure
3759 * @offset: The offset of the byte to read.
3760 * @data: Pointer to a byte to store the value read.
3761 *
3762 * Reads a single byte from the NVM using the flash access registers.
3763 **/
e1000_read_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 * data)3764 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3765 u8 *data)
3766 {
3767 s32 ret_val;
3768 u16 word = 0;
3769
3770 /* In SPT, only 32 bits access is supported,
3771 * so this function should not be called.
3772 */
3773 if (hw->mac.type >= e1000_pch_spt)
3774 return -E1000_ERR_NVM;
3775 else
3776 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3777
3778 if (ret_val)
3779 return ret_val;
3780
3781 *data = (u8)word;
3782
3783 return E1000_SUCCESS;
3784 }
3785
3786 /**
3787 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3788 * @hw: pointer to the HW structure
3789 * @offset: The offset (in bytes) of the byte or word to read.
3790 * @size: Size of data to read, 1=byte 2=word
3791 * @data: Pointer to the word to store the value read.
3792 *
3793 * Reads a byte or word from the NVM using the flash access registers.
3794 **/
e1000_read_flash_data_ich8lan(struct e1000_hw * hw,u32 offset,u8 size,u16 * data)3795 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3796 u8 size, u16 *data)
3797 {
3798 union ich8_hws_flash_status hsfsts;
3799 union ich8_hws_flash_ctrl hsflctl;
3800 u32 flash_linear_addr;
3801 u32 flash_data = 0;
3802 s32 ret_val = -E1000_ERR_NVM;
3803 u8 count = 0;
3804
3805 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3806
3807 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3808 return -E1000_ERR_NVM;
3809 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3810 hw->nvm.flash_base_addr);
3811
3812 do {
3813 usec_delay(1);
3814 /* Steps */
3815 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3816 if (ret_val != E1000_SUCCESS)
3817 break;
3818 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3819
3820 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3821 hsflctl.hsf_ctrl.fldbcount = size - 1;
3822 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3823 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3824 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3825
3826 ret_val = e1000_flash_cycle_ich8lan(hw,
3827 ICH_FLASH_READ_COMMAND_TIMEOUT);
3828
3829 /* Check if FCERR is set to 1, if set to 1, clear it
3830 * and try the whole sequence a few more times, else
3831 * read in (shift in) the Flash Data0, the order is
3832 * least significant byte first msb to lsb
3833 */
3834 if (ret_val == E1000_SUCCESS) {
3835 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3836 if (size == 1)
3837 *data = (u8)(flash_data & 0x000000FF);
3838 else if (size == 2)
3839 *data = (u16)(flash_data & 0x0000FFFF);
3840 break;
3841 } else {
3842 /* If we've gotten here, then things are probably
3843 * completely hosed, but if the error condition is
3844 * detected, it won't hurt to give it another try...
3845 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3846 */
3847 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3848 ICH_FLASH_HSFSTS);
3849 if (hsfsts.hsf_status.flcerr) {
3850 /* Repeat for some time before giving up. */
3851 continue;
3852 } else if (!hsfsts.hsf_status.flcdone) {
3853 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3854 break;
3855 }
3856 }
3857 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3858
3859 return ret_val;
3860 }
3861
3862 /**
3863 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3864 * @hw: pointer to the HW structure
3865 * @offset: The offset (in bytes) of the dword to read.
3866 * @data: Pointer to the dword to store the value read.
3867 *
3868 * Reads a byte or word from the NVM using the flash access registers.
3869 **/
e1000_read_flash_data32_ich8lan(struct e1000_hw * hw,u32 offset,u32 * data)3870 STATIC s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3871 u32 *data)
3872 {
3873 union ich8_hws_flash_status hsfsts;
3874 union ich8_hws_flash_ctrl hsflctl;
3875 u32 flash_linear_addr;
3876 s32 ret_val = -E1000_ERR_NVM;
3877 u8 count = 0;
3878
3879 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3880
3881 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3882 hw->mac.type < e1000_pch_spt)
3883 return -E1000_ERR_NVM;
3884 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3885 hw->nvm.flash_base_addr);
3886
3887 do {
3888 usec_delay(1);
3889 /* Steps */
3890 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3891 if (ret_val != E1000_SUCCESS)
3892 break;
3893 /* In SPT, This register is in Lan memory space, not flash.
3894 * Therefore, only 32 bit access is supported
3895 */
3896 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3897
3898 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3899 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3900 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3901 /* In SPT, This register is in Lan memory space, not flash.
3902 * Therefore, only 32 bit access is supported
3903 */
3904 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3905 (u32)hsflctl.regval << 16);
3906 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3907
3908 ret_val = e1000_flash_cycle_ich8lan(hw,
3909 ICH_FLASH_READ_COMMAND_TIMEOUT);
3910
3911 /* Check if FCERR is set to 1, if set to 1, clear it
3912 * and try the whole sequence a few more times, else
3913 * read in (shift in) the Flash Data0, the order is
3914 * least significant byte first msb to lsb
3915 */
3916 if (ret_val == E1000_SUCCESS) {
3917 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3918 break;
3919 } else {
3920 /* If we've gotten here, then things are probably
3921 * completely hosed, but if the error condition is
3922 * detected, it won't hurt to give it another try...
3923 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3924 */
3925 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3926 ICH_FLASH_HSFSTS);
3927 if (hsfsts.hsf_status.flcerr) {
3928 /* Repeat for some time before giving up. */
3929 continue;
3930 } else if (!hsfsts.hsf_status.flcdone) {
3931 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3932 break;
3933 }
3934 }
3935 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3936
3937 return ret_val;
3938 }
3939
3940 /**
3941 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3942 * @hw: pointer to the HW structure
3943 * @offset: The offset (in bytes) of the word(s) to write.
3944 * @words: Size of data to write in words
3945 * @data: Pointer to the word(s) to write at offset.
3946 *
3947 * Writes a byte or word to the NVM using the flash access registers.
3948 **/
e1000_write_nvm_ich8lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3949 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3950 u16 *data)
3951 {
3952 struct e1000_nvm_info *nvm = &hw->nvm;
3953 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3954 u16 i;
3955
3956 DEBUGFUNC("e1000_write_nvm_ich8lan");
3957
3958 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3959 (words == 0)) {
3960 DEBUGOUT("nvm parameter(s) out of bounds\n");
3961 return -E1000_ERR_NVM;
3962 }
3963
3964 nvm->ops.acquire(hw);
3965
3966 for (i = 0; i < words; i++) {
3967 dev_spec->shadow_ram[offset + i].modified = true;
3968 dev_spec->shadow_ram[offset + i].value = data[i];
3969 }
3970
3971 nvm->ops.release(hw);
3972
3973 return E1000_SUCCESS;
3974 }
3975
3976 /**
3977 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3978 * @hw: pointer to the HW structure
3979 *
3980 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3981 * which writes the checksum to the shadow ram. The changes in the shadow
3982 * ram are then committed to the EEPROM by processing each bank at a time
3983 * checking for the modified bit and writing only the pending changes.
3984 * After a successful commit, the shadow ram is cleared and is ready for
3985 * future writes.
3986 **/
e1000_update_nvm_checksum_spt(struct e1000_hw * hw)3987 STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3988 {
3989 struct e1000_nvm_info *nvm = &hw->nvm;
3990 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3991 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3992 s32 ret_val;
3993 u32 dword = 0;
3994
3995 DEBUGFUNC("e1000_update_nvm_checksum_spt");
3996
3997 ret_val = e1000_update_nvm_checksum_generic(hw);
3998 if (ret_val)
3999 goto out;
4000
4001 if (nvm->type != e1000_nvm_flash_sw)
4002 goto out;
4003
4004 nvm->ops.acquire(hw);
4005
4006 /* We're writing to the opposite bank so if we're on bank 1,
4007 * write to bank 0 etc. We also need to erase the segment that
4008 * is going to be written
4009 */
4010 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4011 if (ret_val != E1000_SUCCESS) {
4012 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4013 bank = 0;
4014 }
4015
4016 if (bank == 0) {
4017 new_bank_offset = nvm->flash_bank_size;
4018 old_bank_offset = 0;
4019 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4020 if (ret_val)
4021 goto release;
4022 } else {
4023 old_bank_offset = nvm->flash_bank_size;
4024 new_bank_offset = 0;
4025 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4026 if (ret_val)
4027 goto release;
4028 }
4029 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4030 /* Determine whether to write the value stored
4031 * in the other NVM bank or a modified value stored
4032 * in the shadow RAM
4033 */
4034 ret_val = e1000_read_flash_dword_ich8lan(hw,
4035 i + old_bank_offset,
4036 &dword);
4037
4038 if (dev_spec->shadow_ram[i].modified) {
4039 dword &= 0xffff0000;
4040 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4041 }
4042 if (dev_spec->shadow_ram[i + 1].modified) {
4043 dword &= 0x0000ffff;
4044 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4045 << 16);
4046 }
4047 if (ret_val)
4048 break;
4049
4050 /* If the word is 0x13, then make sure the signature bits
4051 * (15:14) are 11b until the commit has completed.
4052 * This will allow us to write 10b which indicates the
4053 * signature is valid. We want to do this after the write
4054 * has completed so that we don't mark the segment valid
4055 * while the write is still in progress
4056 */
4057 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4058 dword |= E1000_ICH_NVM_SIG_MASK << 16;
4059
4060 /* Convert offset to bytes. */
4061 act_offset = (i + new_bank_offset) << 1;
4062
4063 usec_delay(100);
4064
4065 /* Write the data to the new bank. Offset in words*/
4066 act_offset = i + new_bank_offset;
4067 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4068 dword);
4069 if (ret_val)
4070 break;
4071 }
4072
4073 /* Don't bother writing the segment valid bits if sector
4074 * programming failed.
4075 */
4076 if (ret_val) {
4077 DEBUGOUT("Flash commit failed.\n");
4078 goto release;
4079 }
4080
4081 /* Finally validate the new segment by setting bit 15:14
4082 * to 10b in word 0x13 , this can be done without an
4083 * erase as well since these bits are 11 to start with
4084 * and we need to change bit 14 to 0b
4085 */
4086 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4087
4088 /*offset in words but we read dword*/
4089 --act_offset;
4090 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4091
4092 if (ret_val)
4093 goto release;
4094
4095 dword &= 0xBFFFFFFF;
4096 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4097
4098 if (ret_val)
4099 goto release;
4100
4101 /* offset in words but we read dword*/
4102 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4103 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4104
4105 if (ret_val)
4106 goto release;
4107
4108 dword &= 0x00FFFFFF;
4109 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4110
4111 if (ret_val)
4112 goto release;
4113
4114 /* Great! Everything worked, we can now clear the cached entries. */
4115 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4116 dev_spec->shadow_ram[i].modified = false;
4117 dev_spec->shadow_ram[i].value = 0xFFFF;
4118 }
4119
4120 release:
4121 nvm->ops.release(hw);
4122
4123 /* Reload the EEPROM, or else modifications will not appear
4124 * until after the next adapter reset.
4125 */
4126 if (!ret_val) {
4127 nvm->ops.reload(hw);
4128 msec_delay(10);
4129 }
4130
4131 out:
4132 if (ret_val)
4133 DEBUGOUT1("NVM update error: %d\n", ret_val);
4134
4135 return ret_val;
4136 }
4137
4138 /**
4139 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4140 * @hw: pointer to the HW structure
4141 *
4142 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4143 * which writes the checksum to the shadow ram. The changes in the shadow
4144 * ram are then committed to the EEPROM by processing each bank at a time
4145 * checking for the modified bit and writing only the pending changes.
4146 * After a successful commit, the shadow ram is cleared and is ready for
4147 * future writes.
4148 **/
e1000_update_nvm_checksum_ich8lan(struct e1000_hw * hw)4149 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4150 {
4151 struct e1000_nvm_info *nvm = &hw->nvm;
4152 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4153 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4154 s32 ret_val;
4155 u16 data = 0;
4156
4157 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4158
4159 ret_val = e1000_update_nvm_checksum_generic(hw);
4160 if (ret_val)
4161 goto out;
4162
4163 if (nvm->type != e1000_nvm_flash_sw)
4164 goto out;
4165
4166 nvm->ops.acquire(hw);
4167
4168 /* We're writing to the opposite bank so if we're on bank 1,
4169 * write to bank 0 etc. We also need to erase the segment that
4170 * is going to be written
4171 */
4172 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4173 if (ret_val != E1000_SUCCESS) {
4174 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4175 bank = 0;
4176 }
4177
4178 if (bank == 0) {
4179 new_bank_offset = nvm->flash_bank_size;
4180 old_bank_offset = 0;
4181 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4182 if (ret_val)
4183 goto release;
4184 } else {
4185 old_bank_offset = nvm->flash_bank_size;
4186 new_bank_offset = 0;
4187 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4188 if (ret_val)
4189 goto release;
4190 }
4191 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4192 if (dev_spec->shadow_ram[i].modified) {
4193 data = dev_spec->shadow_ram[i].value;
4194 } else {
4195 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4196 old_bank_offset,
4197 &data);
4198 if (ret_val)
4199 break;
4200 }
4201 /* If the word is 0x13, then make sure the signature bits
4202 * (15:14) are 11b until the commit has completed.
4203 * This will allow us to write 10b which indicates the
4204 * signature is valid. We want to do this after the write
4205 * has completed so that we don't mark the segment valid
4206 * while the write is still in progress
4207 */
4208 if (i == E1000_ICH_NVM_SIG_WORD)
4209 data |= E1000_ICH_NVM_SIG_MASK;
4210
4211 /* Convert offset to bytes. */
4212 act_offset = (i + new_bank_offset) << 1;
4213
4214 usec_delay(100);
4215
4216 /* Write the bytes to the new bank. */
4217 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4218 act_offset,
4219 (u8)data);
4220 if (ret_val)
4221 break;
4222
4223 usec_delay(100);
4224 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4225 act_offset + 1,
4226 (u8)(data >> 8));
4227 if (ret_val)
4228 break;
4229 }
4230
4231 /* Don't bother writing the segment valid bits if sector
4232 * programming failed.
4233 */
4234 if (ret_val) {
4235 DEBUGOUT("Flash commit failed.\n");
4236 goto release;
4237 }
4238
4239 /* Finally validate the new segment by setting bit 15:14
4240 * to 10b in word 0x13 , this can be done without an
4241 * erase as well since these bits are 11 to start with
4242 * and we need to change bit 14 to 0b
4243 */
4244 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4245 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4246 if (ret_val)
4247 goto release;
4248
4249 data &= 0xBFFF;
4250 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4251 (u8)(data >> 8));
4252 if (ret_val)
4253 goto release;
4254
4255 /* And invalidate the previously valid segment by setting
4256 * its signature word (0x13) high_byte to 0b. This can be
4257 * done without an erase because flash erase sets all bits
4258 * to 1's. We can write 1's to 0's without an erase
4259 */
4260 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4261
4262 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4263
4264 if (ret_val)
4265 goto release;
4266
4267 /* Great! Everything worked, we can now clear the cached entries. */
4268 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4269 dev_spec->shadow_ram[i].modified = false;
4270 dev_spec->shadow_ram[i].value = 0xFFFF;
4271 }
4272
4273 release:
4274 nvm->ops.release(hw);
4275
4276 /* Reload the EEPROM, or else modifications will not appear
4277 * until after the next adapter reset.
4278 */
4279 if (!ret_val) {
4280 nvm->ops.reload(hw);
4281 msec_delay(10);
4282 }
4283
4284 out:
4285 if (ret_val)
4286 DEBUGOUT1("NVM update error: %d\n", ret_val);
4287
4288 return ret_val;
4289 }
4290
4291 /**
4292 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4293 * @hw: pointer to the HW structure
4294 *
4295 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4296 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4297 * calculated, in which case we need to calculate the checksum and set bit 6.
4298 **/
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw * hw)4299 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4300 {
4301 s32 ret_val;
4302 u16 data;
4303 u16 word;
4304 u16 valid_csum_mask;
4305
4306 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4307
4308 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4309 * the checksum needs to be fixed. This bit is an indication that
4310 * the NVM was prepared by OEM software and did not calculate
4311 * the checksum...a likely scenario.
4312 */
4313 switch (hw->mac.type) {
4314 case e1000_pch_lpt:
4315 case e1000_pch_spt:
4316 case e1000_pch_cnp:
4317 case e1000_pch_adp:
4318 word = NVM_COMPAT;
4319 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4320 break;
4321 default:
4322 word = NVM_FUTURE_INIT_WORD1;
4323 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4324 break;
4325 }
4326
4327 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4328 if (ret_val)
4329 return ret_val;
4330
4331 if (!(data & valid_csum_mask)) {
4332 data |= valid_csum_mask;
4333 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4334 if (ret_val)
4335 return ret_val;
4336 ret_val = hw->nvm.ops.update(hw);
4337 if (ret_val)
4338 return ret_val;
4339 }
4340
4341 return e1000_validate_nvm_checksum_generic(hw);
4342 }
4343
4344 /**
4345 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4346 * @hw: pointer to the HW structure
4347 * @offset: The offset (in bytes) of the byte/word to read.
4348 * @size: Size of data to read, 1=byte 2=word
4349 * @data: The byte(s) to write to the NVM.
4350 *
4351 * Writes one/two bytes to the NVM using the flash access registers.
4352 **/
e1000_write_flash_data_ich8lan(struct e1000_hw * hw,u32 offset,u8 size,u16 data)4353 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4354 u8 size, u16 data)
4355 {
4356 union ich8_hws_flash_status hsfsts;
4357 union ich8_hws_flash_ctrl hsflctl;
4358 u32 flash_linear_addr;
4359 u32 flash_data = 0;
4360 s32 ret_val;
4361 u8 count = 0;
4362
4363 DEBUGFUNC("e1000_write_ich8_data");
4364
4365 if (hw->mac.type >= e1000_pch_spt) {
4366 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4367 return -E1000_ERR_NVM;
4368 } else {
4369 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4370 return -E1000_ERR_NVM;
4371 }
4372
4373 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4374 hw->nvm.flash_base_addr);
4375
4376 do {
4377 usec_delay(1);
4378 /* Steps */
4379 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4380 if (ret_val != E1000_SUCCESS)
4381 break;
4382 /* In SPT, This register is in Lan memory space, not
4383 * flash. Therefore, only 32 bit access is supported
4384 */
4385 if (hw->mac.type >= e1000_pch_spt)
4386 hsflctl.regval =
4387 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4388 else
4389 hsflctl.regval =
4390 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4391
4392 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4393 hsflctl.hsf_ctrl.fldbcount = size - 1;
4394 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4395 /* In SPT, This register is in Lan memory space,
4396 * not flash. Therefore, only 32 bit access is
4397 * supported
4398 */
4399 if (hw->mac.type >= e1000_pch_spt)
4400 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4401 hsflctl.regval << 16);
4402 else
4403 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4404 hsflctl.regval);
4405
4406 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4407
4408 if (size == 1)
4409 flash_data = (u32)data & 0x00FF;
4410 else
4411 flash_data = (u32)data;
4412
4413 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4414
4415 /* check if FCERR is set to 1 , if set to 1, clear it
4416 * and try the whole sequence a few more times else done
4417 */
4418 ret_val =
4419 e1000_flash_cycle_ich8lan(hw,
4420 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4421 if (ret_val == E1000_SUCCESS)
4422 break;
4423
4424 /* If we're here, then things are most likely
4425 * completely hosed, but if the error condition
4426 * is detected, it won't hurt to give it another
4427 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4428 */
4429 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4430 if (hsfsts.hsf_status.flcerr)
4431 /* Repeat for some time before giving up. */
4432 continue;
4433 if (!hsfsts.hsf_status.flcdone) {
4434 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4435 break;
4436 }
4437 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4438
4439 return ret_val;
4440 }
4441
4442 /**
4443 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4444 * @hw: pointer to the HW structure
4445 * @offset: The offset (in bytes) of the dwords to read.
4446 * @data: The 4 bytes to write to the NVM.
4447 *
4448 * Writes one/two/four bytes to the NVM using the flash access registers.
4449 **/
e1000_write_flash_data32_ich8lan(struct e1000_hw * hw,u32 offset,u32 data)4450 STATIC s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4451 u32 data)
4452 {
4453 union ich8_hws_flash_status hsfsts;
4454 union ich8_hws_flash_ctrl hsflctl;
4455 u32 flash_linear_addr;
4456 s32 ret_val;
4457 u8 count = 0;
4458
4459 DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4460
4461 if (hw->mac.type >= e1000_pch_spt) {
4462 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4463 return -E1000_ERR_NVM;
4464 }
4465 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4466 hw->nvm.flash_base_addr);
4467 do {
4468 usec_delay(1);
4469 /* Steps */
4470 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4471 if (ret_val != E1000_SUCCESS)
4472 break;
4473
4474 /* In SPT, This register is in Lan memory space, not
4475 * flash. Therefore, only 32 bit access is supported
4476 */
4477 if (hw->mac.type >= e1000_pch_spt)
4478 hsflctl.regval = E1000_READ_FLASH_REG(hw,
4479 ICH_FLASH_HSFSTS)
4480 >> 16;
4481 else
4482 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4483 ICH_FLASH_HSFCTL);
4484
4485 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4486 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4487
4488 /* In SPT, This register is in Lan memory space,
4489 * not flash. Therefore, only 32 bit access is
4490 * supported
4491 */
4492 if (hw->mac.type >= e1000_pch_spt)
4493 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4494 hsflctl.regval << 16);
4495 else
4496 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4497 hsflctl.regval);
4498
4499 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4500
4501 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4502
4503 /* check if FCERR is set to 1 , if set to 1, clear it
4504 * and try the whole sequence a few more times else done
4505 */
4506 ret_val = e1000_flash_cycle_ich8lan(hw,
4507 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4508
4509 if (ret_val == E1000_SUCCESS)
4510 break;
4511
4512 /* If we're here, then things are most likely
4513 * completely hosed, but if the error condition
4514 * is detected, it won't hurt to give it another
4515 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4516 */
4517 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4518
4519 if (hsfsts.hsf_status.flcerr)
4520 /* Repeat for some time before giving up. */
4521 continue;
4522 if (!hsfsts.hsf_status.flcdone) {
4523 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4524 break;
4525 }
4526 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4527
4528 return ret_val;
4529 }
4530
4531 /**
4532 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4533 * @hw: pointer to the HW structure
4534 * @offset: The index of the byte to read.
4535 * @data: The byte to write to the NVM.
4536 *
4537 * Writes a single byte to the NVM using the flash access registers.
4538 **/
e1000_write_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 data)4539 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4540 u8 data)
4541 {
4542 u16 word = (u16)data;
4543
4544 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4545
4546 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4547 }
4548
4549 /**
4550 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4551 * @hw: pointer to the HW structure
4552 * @offset: The offset of the word to write.
4553 * @dword: The dword to write to the NVM.
4554 *
4555 * Writes a single dword to the NVM using the flash access registers.
4556 * Goes through a retry algorithm before giving up.
4557 **/
e1000_retry_write_flash_dword_ich8lan(struct e1000_hw * hw,u32 offset,u32 dword)4558 STATIC s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4559 u32 offset, u32 dword)
4560 {
4561 s32 ret_val;
4562 u16 program_retries;
4563
4564 DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4565
4566 /* Must convert word offset into bytes. */
4567 offset <<= 1;
4568
4569 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4570
4571 if (!ret_val)
4572 return ret_val;
4573 for (program_retries = 0; program_retries < 100; program_retries++) {
4574 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4575 usec_delay(100);
4576 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4577 if (ret_val == E1000_SUCCESS)
4578 break;
4579 }
4580 if (program_retries == 100)
4581 return -E1000_ERR_NVM;
4582
4583 return E1000_SUCCESS;
4584 }
4585
4586 /**
4587 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4588 * @hw: pointer to the HW structure
4589 * @offset: The offset of the byte to write.
4590 * @byte: The byte to write to the NVM.
4591 *
4592 * Writes a single byte to the NVM using the flash access registers.
4593 * Goes through a retry algorithm before giving up.
4594 **/
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 byte)4595 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4596 u32 offset, u8 byte)
4597 {
4598 s32 ret_val;
4599 u16 program_retries;
4600
4601 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4602
4603 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4604 if (!ret_val)
4605 return ret_val;
4606
4607 for (program_retries = 0; program_retries < 100; program_retries++) {
4608 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4609 usec_delay(100);
4610 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4611 if (ret_val == E1000_SUCCESS)
4612 break;
4613 }
4614 if (program_retries == 100)
4615 return -E1000_ERR_NVM;
4616
4617 return E1000_SUCCESS;
4618 }
4619
4620 /**
4621 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4622 * @hw: pointer to the HW structure
4623 * @bank: 0 for first bank, 1 for second bank, etc.
4624 *
4625 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4626 * bank N is 4096 * N + flash_reg_addr.
4627 **/
e1000_erase_flash_bank_ich8lan(struct e1000_hw * hw,u32 bank)4628 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4629 {
4630 struct e1000_nvm_info *nvm = &hw->nvm;
4631 union ich8_hws_flash_status hsfsts;
4632 union ich8_hws_flash_ctrl hsflctl;
4633 u32 flash_linear_addr;
4634 /* bank size is in 16bit words - adjust to bytes */
4635 u32 flash_bank_size = nvm->flash_bank_size * 2;
4636 s32 ret_val;
4637 s32 count = 0;
4638 s32 j, iteration, sector_size;
4639
4640 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4641
4642 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4643
4644 /* Determine HW Sector size: Read BERASE bits of hw flash status
4645 * register
4646 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4647 * consecutive sectors. The start index for the nth Hw sector
4648 * can be calculated as = bank * 4096 + n * 256
4649 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4650 * The start index for the nth Hw sector can be calculated
4651 * as = bank * 4096
4652 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4653 * (ich9 only, otherwise error condition)
4654 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4655 */
4656 switch (hsfsts.hsf_status.berasesz) {
4657 case 0:
4658 /* Hw sector size 256 */
4659 sector_size = ICH_FLASH_SEG_SIZE_256;
4660 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4661 break;
4662 case 1:
4663 sector_size = ICH_FLASH_SEG_SIZE_4K;
4664 iteration = 1;
4665 break;
4666 case 2:
4667 sector_size = ICH_FLASH_SEG_SIZE_8K;
4668 iteration = 1;
4669 break;
4670 case 3:
4671 sector_size = ICH_FLASH_SEG_SIZE_64K;
4672 iteration = 1;
4673 break;
4674 default:
4675 return -E1000_ERR_NVM;
4676 }
4677
4678 /* Start with the base address, then add the sector offset. */
4679 flash_linear_addr = hw->nvm.flash_base_addr;
4680 flash_linear_addr += (bank) ? flash_bank_size : 0;
4681
4682 for (j = 0; j < iteration; j++) {
4683 do {
4684 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4685
4686 /* Steps */
4687 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4688 if (ret_val)
4689 return ret_val;
4690
4691 /* Write a value 11 (block Erase) in Flash
4692 * Cycle field in hw flash control
4693 */
4694 if (hw->mac.type >= e1000_pch_spt)
4695 hsflctl.regval =
4696 E1000_READ_FLASH_REG(hw,
4697 ICH_FLASH_HSFSTS)>>16;
4698 else
4699 hsflctl.regval =
4700 E1000_READ_FLASH_REG16(hw,
4701 ICH_FLASH_HSFCTL);
4702
4703 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4704 if (hw->mac.type >= e1000_pch_spt)
4705 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4706 hsflctl.regval << 16);
4707 else
4708 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4709 hsflctl.regval);
4710
4711 /* Write the last 24 bits of an index within the
4712 * block into Flash Linear address field in Flash
4713 * Address.
4714 */
4715 flash_linear_addr += (j * sector_size);
4716 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4717 flash_linear_addr);
4718
4719 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4720 if (ret_val == E1000_SUCCESS)
4721 break;
4722
4723 /* Check if FCERR is set to 1. If 1,
4724 * clear it and try the whole sequence
4725 * a few more times else Done
4726 */
4727 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4728 ICH_FLASH_HSFSTS);
4729 if (hsfsts.hsf_status.flcerr)
4730 /* repeat for some time before giving up */
4731 continue;
4732 else if (!hsfsts.hsf_status.flcdone)
4733 return ret_val;
4734 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4735 }
4736
4737 return E1000_SUCCESS;
4738 }
4739
4740 /**
4741 * e1000_valid_led_default_ich8lan - Set the default LED settings
4742 * @hw: pointer to the HW structure
4743 * @data: Pointer to the LED settings
4744 *
4745 * Reads the LED default settings from the NVM to data. If the NVM LED
4746 * settings is all 0's or F's, set the LED default to a valid LED default
4747 * setting.
4748 **/
e1000_valid_led_default_ich8lan(struct e1000_hw * hw,u16 * data)4749 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4750 {
4751 s32 ret_val;
4752
4753 DEBUGFUNC("e1000_valid_led_default_ich8lan");
4754
4755 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4756 if (ret_val) {
4757 DEBUGOUT("NVM Read Error\n");
4758 return ret_val;
4759 }
4760
4761 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4762 *data = ID_LED_DEFAULT_ICH8LAN;
4763
4764 return E1000_SUCCESS;
4765 }
4766
4767 /**
4768 * e1000_id_led_init_pchlan - store LED configurations
4769 * @hw: pointer to the HW structure
4770 *
4771 * PCH does not control LEDs via the LEDCTL register, rather it uses
4772 * the PHY LED configuration register.
4773 *
4774 * PCH also does not have an "always on" or "always off" mode which
4775 * complicates the ID feature. Instead of using the "on" mode to indicate
4776 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4777 * use "link_up" mode. The LEDs will still ID on request if there is no
4778 * link based on logic in e1000_led_[on|off]_pchlan().
4779 **/
e1000_id_led_init_pchlan(struct e1000_hw * hw)4780 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4781 {
4782 struct e1000_mac_info *mac = &hw->mac;
4783 s32 ret_val;
4784 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4785 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4786 u16 data, i, temp, shift;
4787
4788 DEBUGFUNC("e1000_id_led_init_pchlan");
4789
4790 /* Get default ID LED modes */
4791 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4792 if (ret_val)
4793 return ret_val;
4794
4795 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4796 mac->ledctl_mode1 = mac->ledctl_default;
4797 mac->ledctl_mode2 = mac->ledctl_default;
4798
4799 for (i = 0; i < 4; i++) {
4800 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4801 shift = (i * 5);
4802 switch (temp) {
4803 case ID_LED_ON1_DEF2:
4804 case ID_LED_ON1_ON2:
4805 case ID_LED_ON1_OFF2:
4806 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4807 mac->ledctl_mode1 |= (ledctl_on << shift);
4808 break;
4809 case ID_LED_OFF1_DEF2:
4810 case ID_LED_OFF1_ON2:
4811 case ID_LED_OFF1_OFF2:
4812 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4813 mac->ledctl_mode1 |= (ledctl_off << shift);
4814 break;
4815 default:
4816 /* Do nothing */
4817 break;
4818 }
4819 switch (temp) {
4820 case ID_LED_DEF1_ON2:
4821 case ID_LED_ON1_ON2:
4822 case ID_LED_OFF1_ON2:
4823 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4824 mac->ledctl_mode2 |= (ledctl_on << shift);
4825 break;
4826 case ID_LED_DEF1_OFF2:
4827 case ID_LED_ON1_OFF2:
4828 case ID_LED_OFF1_OFF2:
4829 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4830 mac->ledctl_mode2 |= (ledctl_off << shift);
4831 break;
4832 default:
4833 /* Do nothing */
4834 break;
4835 }
4836 }
4837
4838 return E1000_SUCCESS;
4839 }
4840
4841 /**
4842 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4843 * @hw: pointer to the HW structure
4844 *
4845 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4846 * register, so the bus width is hard coded.
4847 **/
e1000_get_bus_info_ich8lan(struct e1000_hw * hw)4848 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4849 {
4850 struct e1000_bus_info *bus = &hw->bus;
4851 s32 ret_val;
4852
4853 DEBUGFUNC("e1000_get_bus_info_ich8lan");
4854
4855 ret_val = e1000_get_bus_info_pcie_generic(hw);
4856
4857 /* ICH devices are "PCI Express"-ish. They have
4858 * a configuration space, but do not contain
4859 * PCI Express Capability registers, so bus width
4860 * must be hardcoded.
4861 */
4862 if (bus->width == e1000_bus_width_unknown)
4863 bus->width = e1000_bus_width_pcie_x1;
4864
4865 return ret_val;
4866 }
4867
4868 /**
4869 * e1000_reset_hw_ich8lan - Reset the hardware
4870 * @hw: pointer to the HW structure
4871 *
4872 * Does a full reset of the hardware which includes a reset of the PHY and
4873 * MAC.
4874 **/
e1000_reset_hw_ich8lan(struct e1000_hw * hw)4875 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4876 {
4877 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4878 u16 kum_cfg;
4879 u32 ctrl, reg;
4880 s32 ret_val;
4881 u16 pci_cfg;
4882
4883 DEBUGFUNC("e1000_reset_hw_ich8lan");
4884
4885 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4886 * on the last TLP read/write transaction when MAC is reset.
4887 */
4888 ret_val = e1000_disable_pcie_master_generic(hw);
4889 if (ret_val)
4890 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4891
4892 DEBUGOUT("Masking off all interrupts\n");
4893 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4894
4895 /* Disable the Transmit and Receive units. Then delay to allow
4896 * any pending transactions to complete before we hit the MAC
4897 * with the global reset.
4898 */
4899 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4900 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4901 E1000_WRITE_FLUSH(hw);
4902
4903 msec_delay(10);
4904
4905 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4906 if (hw->mac.type == e1000_ich8lan) {
4907 /* Set Tx and Rx buffer allocation to 8k apiece. */
4908 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4909 /* Set Packet Buffer Size to 16k. */
4910 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4911 }
4912
4913 if (hw->mac.type == e1000_pchlan) {
4914 /* Save the NVM K1 bit setting*/
4915 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4916 if (ret_val)
4917 return ret_val;
4918
4919 if (kum_cfg & E1000_NVM_K1_ENABLE)
4920 dev_spec->nvm_k1_enabled = true;
4921 else
4922 dev_spec->nvm_k1_enabled = false;
4923 }
4924
4925 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4926
4927 if (!hw->phy.ops.check_reset_block(hw)) {
4928 /* Full-chip reset requires MAC and PHY reset at the same
4929 * time to make sure the interface between MAC and the
4930 * external PHY is reset.
4931 */
4932 ctrl |= E1000_CTRL_PHY_RST;
4933
4934 /* Gate automatic PHY configuration by hardware on
4935 * non-managed 82579
4936 */
4937 if ((hw->mac.type == e1000_pch2lan) &&
4938 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4939 e1000_gate_hw_phy_config_ich8lan(hw, true);
4940 }
4941 ret_val = e1000_acquire_swflag_ich8lan(hw);
4942
4943 /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan function
4944 * may occur during global reset and cause system hang.
4945 * Configuration space access creates the needed delay.
4946 * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER value
4947 * insures configuration space read is done before global reset.
4948 */
4949 e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
4950 E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
4951 DEBUGOUT("Issuing a global reset to ich8lan\n");
4952 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4953 /* cannot issue a flush here because it hangs the hardware */
4954 msec_delay(20);
4955
4956 /* Configuration space access improve HW level time sync mechanism.
4957 * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER
4958 * value to insure configuration space read is done
4959 * before any access to mac register.
4960 */
4961 e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
4962 E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
4963
4964 /* Set Phy Config Counter to 50msec */
4965 if (hw->mac.type == e1000_pch2lan) {
4966 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4967 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4968 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4969 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4970 }
4971
4972 if (!ret_val)
4973 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4974
4975 if (ctrl & E1000_CTRL_PHY_RST) {
4976 ret_val = hw->phy.ops.get_cfg_done(hw);
4977 if (ret_val)
4978 return ret_val;
4979
4980 ret_val = e1000_post_phy_reset_ich8lan(hw);
4981 if (ret_val)
4982 return ret_val;
4983 }
4984
4985 /* For PCH, this write will make sure that any noise
4986 * will be detected as a CRC error and be dropped rather than show up
4987 * as a bad packet to the DMA engine.
4988 */
4989 if (hw->mac.type == e1000_pchlan)
4990 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4991
4992 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4993 E1000_READ_REG(hw, E1000_ICR);
4994
4995 reg = E1000_READ_REG(hw, E1000_KABGTXD);
4996 reg |= E1000_KABGTXD_BGSQLBIAS;
4997 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4998
4999 return E1000_SUCCESS;
5000 }
5001
5002 /**
5003 * e1000_init_hw_ich8lan - Initialize the hardware
5004 * @hw: pointer to the HW structure
5005 *
5006 * Prepares the hardware for transmit and receive by doing the following:
5007 * - initialize hardware bits
5008 * - initialize LED identification
5009 * - setup receive address registers
5010 * - setup flow control
5011 * - setup transmit descriptors
5012 * - clear statistics
5013 **/
e1000_init_hw_ich8lan(struct e1000_hw * hw)5014 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5015 {
5016 struct e1000_mac_info *mac = &hw->mac;
5017 u32 ctrl_ext, txdctl, snoop;
5018 s32 ret_val;
5019 u16 i;
5020
5021 DEBUGFUNC("e1000_init_hw_ich8lan");
5022
5023 e1000_initialize_hw_bits_ich8lan(hw);
5024
5025 /* Initialize identification LED */
5026 ret_val = mac->ops.id_led_init(hw);
5027 /* An error is not fatal and we should not stop init due to this */
5028 if (ret_val)
5029 DEBUGOUT("Error initializing identification LED\n");
5030
5031 /* Setup the receive address. */
5032 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5033
5034 /* Zero out the Multicast HASH table */
5035 DEBUGOUT("Zeroing the MTA\n");
5036 for (i = 0; i < mac->mta_reg_count; i++)
5037 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5038
5039 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5040 * the ME. Disable wakeup by clearing the host wakeup bit.
5041 * Reset the phy after disabling host wakeup to reset the Rx buffer.
5042 */
5043 if (hw->phy.type == e1000_phy_82578) {
5044 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5045 i &= ~BM_WUC_HOST_WU_BIT;
5046 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5047 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5048 if (ret_val)
5049 return ret_val;
5050 }
5051
5052 /* Setup link and flow control */
5053 ret_val = mac->ops.setup_link(hw);
5054
5055 /* Set the transmit descriptor write-back policy for both queues */
5056 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5057 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5058 E1000_TXDCTL_FULL_TX_DESC_WB);
5059 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5060 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5061 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5062 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5063 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5064 E1000_TXDCTL_FULL_TX_DESC_WB);
5065 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5066 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5067 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5068
5069 /* ICH8 has opposite polarity of no_snoop bits.
5070 * By default, we should use snoop behavior.
5071 */
5072 if (mac->type == e1000_ich8lan)
5073 snoop = PCIE_ICH8_SNOOP_ALL;
5074 else
5075 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5076 e1000_set_pcie_no_snoop_generic(hw, snoop);
5077
5078 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5079 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5080 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5081
5082 /* Clear all of the statistics registers (clear on read). It is
5083 * important that we do this after we have tried to establish link
5084 * because the symbol error count will increment wildly if there
5085 * is no link.
5086 */
5087 e1000_clear_hw_cntrs_ich8lan(hw);
5088
5089 return ret_val;
5090 }
5091
5092 /**
5093 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5094 * @hw: pointer to the HW structure
5095 *
5096 * Sets/Clears required hardware bits necessary for correctly setting up the
5097 * hardware for transmit and receive.
5098 **/
e1000_initialize_hw_bits_ich8lan(struct e1000_hw * hw)5099 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5100 {
5101 u32 reg;
5102
5103 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5104
5105 /* Extended Device Control */
5106 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5107 reg |= (1 << 22);
5108 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5109 if (hw->mac.type >= e1000_pchlan)
5110 reg |= E1000_CTRL_EXT_PHYPDEN;
5111 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5112
5113 /* Transmit Descriptor Control 0 */
5114 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5115 reg |= (1 << 22);
5116 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5117
5118 /* Transmit Descriptor Control 1 */
5119 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5120 reg |= (1 << 22);
5121 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5122
5123 /* Transmit Arbitration Control 0 */
5124 reg = E1000_READ_REG(hw, E1000_TARC(0));
5125 if (hw->mac.type == e1000_ich8lan)
5126 reg |= (1 << 28) | (1 << 29);
5127 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5128 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5129
5130 /* Transmit Arbitration Control 1 */
5131 reg = E1000_READ_REG(hw, E1000_TARC(1));
5132 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5133 reg &= ~(1 << 28);
5134 else
5135 reg |= (1 << 28);
5136 reg |= (1 << 24) | (1 << 26) | (1 << 30);
5137 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5138
5139 /* Device Status */
5140 if (hw->mac.type == e1000_ich8lan) {
5141 reg = E1000_READ_REG(hw, E1000_STATUS);
5142 reg &= ~(1U << 31);
5143 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5144 }
5145
5146 /* work-around descriptor data corruption issue during nfs v2 udp
5147 * traffic, just disable the nfs filtering capability
5148 */
5149 reg = E1000_READ_REG(hw, E1000_RFCTL);
5150 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5151
5152 /* Disable IPv6 extension header parsing because some malformed
5153 * IPv6 headers can hang the Rx.
5154 */
5155 if (hw->mac.type == e1000_ich8lan)
5156 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5157 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5158
5159 /* Enable ECC on Lynxpoint */
5160 if (hw->mac.type >= e1000_pch_lpt) {
5161 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5162 reg |= E1000_PBECCSTS_ECC_ENABLE;
5163 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5164
5165 reg = E1000_READ_REG(hw, E1000_CTRL);
5166 reg |= E1000_CTRL_MEHE;
5167 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5168 }
5169
5170 return;
5171 }
5172
5173 /**
5174 * e1000_setup_link_ich8lan - Setup flow control and link settings
5175 * @hw: pointer to the HW structure
5176 *
5177 * Determines which flow control settings to use, then configures flow
5178 * control. Calls the appropriate media-specific link configuration
5179 * function. Assuming the adapter has a valid link partner, a valid link
5180 * should be established. Assumes the hardware has previously been reset
5181 * and the transmitter and receiver are not enabled.
5182 **/
e1000_setup_link_ich8lan(struct e1000_hw * hw)5183 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5184 {
5185 s32 ret_val;
5186
5187 DEBUGFUNC("e1000_setup_link_ich8lan");
5188
5189 /* ICH parts do not have a word in the NVM to determine
5190 * the default flow control setting, so we explicitly
5191 * set it to full.
5192 */
5193 if (hw->fc.requested_mode == e1000_fc_default)
5194 hw->fc.requested_mode = e1000_fc_full;
5195
5196 /* Save off the requested flow control mode for use later. Depending
5197 * on the link partner's capabilities, we may or may not use this mode.
5198 */
5199 hw->fc.current_mode = hw->fc.requested_mode;
5200
5201 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5202 hw->fc.current_mode);
5203
5204 if (!hw->phy.ops.check_reset_block(hw)) {
5205 /* Continue to configure the copper link. */
5206 ret_val = hw->mac.ops.setup_physical_interface(hw);
5207 if (ret_val)
5208 return ret_val;
5209 }
5210
5211 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5212 if ((hw->phy.type == e1000_phy_82578) ||
5213 (hw->phy.type == e1000_phy_82579) ||
5214 (hw->phy.type == e1000_phy_i217) ||
5215 (hw->phy.type == e1000_phy_82577)) {
5216 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5217
5218 ret_val = hw->phy.ops.write_reg(hw,
5219 PHY_REG(BM_PORT_CTRL_PAGE, 27),
5220 hw->fc.pause_time);
5221 if (ret_val)
5222 return ret_val;
5223 }
5224
5225 return e1000_set_fc_watermarks_generic(hw);
5226 }
5227
5228 /**
5229 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5230 * @hw: pointer to the HW structure
5231 *
5232 * Configures the kumeran interface to the PHY to wait the appropriate time
5233 * when polling the PHY, then call the generic setup_copper_link to finish
5234 * configuring the copper link.
5235 **/
e1000_setup_copper_link_ich8lan(struct e1000_hw * hw)5236 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5237 {
5238 u32 ctrl;
5239 s32 ret_val;
5240 u16 reg_data;
5241
5242 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5243
5244 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5245 ctrl |= E1000_CTRL_SLU;
5246 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5247 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5248
5249 /* Set the mac to wait the maximum time between each iteration
5250 * and increase the max iterations when polling the phy;
5251 * this fixes erroneous timeouts at 10Mbps.
5252 */
5253 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5254 0xFFFF);
5255 if (ret_val)
5256 return ret_val;
5257 ret_val = e1000_read_kmrn_reg_generic(hw,
5258 E1000_KMRNCTRLSTA_INBAND_PARAM,
5259 ®_data);
5260 if (ret_val)
5261 return ret_val;
5262 reg_data |= 0x3F;
5263 ret_val = e1000_write_kmrn_reg_generic(hw,
5264 E1000_KMRNCTRLSTA_INBAND_PARAM,
5265 reg_data);
5266 if (ret_val)
5267 return ret_val;
5268
5269 switch (hw->phy.type) {
5270 case e1000_phy_igp_3:
5271 ret_val = e1000_copper_link_setup_igp(hw);
5272 if (ret_val)
5273 return ret_val;
5274 break;
5275 case e1000_phy_bm:
5276 case e1000_phy_82578:
5277 ret_val = e1000_copper_link_setup_m88(hw);
5278 if (ret_val)
5279 return ret_val;
5280 break;
5281 case e1000_phy_82577:
5282 case e1000_phy_82579:
5283 ret_val = e1000_copper_link_setup_82577(hw);
5284 if (ret_val)
5285 return ret_val;
5286 break;
5287 case e1000_phy_ife:
5288 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5289 ®_data);
5290 if (ret_val)
5291 return ret_val;
5292
5293 reg_data &= ~IFE_PMC_AUTO_MDIX;
5294
5295 switch (hw->phy.mdix) {
5296 case 1:
5297 reg_data &= ~IFE_PMC_FORCE_MDIX;
5298 break;
5299 case 2:
5300 reg_data |= IFE_PMC_FORCE_MDIX;
5301 break;
5302 case 0:
5303 default:
5304 reg_data |= IFE_PMC_AUTO_MDIX;
5305 break;
5306 }
5307 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5308 reg_data);
5309 if (ret_val)
5310 return ret_val;
5311 break;
5312 default:
5313 break;
5314 }
5315
5316 return e1000_setup_copper_link_generic(hw);
5317 }
5318
5319 /**
5320 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5321 * @hw: pointer to the HW structure
5322 *
5323 * Calls the PHY specific link setup function and then calls the
5324 * generic setup_copper_link to finish configuring the link for
5325 * Lynxpoint PCH devices
5326 **/
e1000_setup_copper_link_pch_lpt(struct e1000_hw * hw)5327 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5328 {
5329 u32 ctrl;
5330 s32 ret_val;
5331
5332 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5333
5334 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5335 ctrl |= E1000_CTRL_SLU;
5336 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5337 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5338
5339 ret_val = e1000_copper_link_setup_82577(hw);
5340 if (ret_val)
5341 return ret_val;
5342
5343 return e1000_setup_copper_link_generic(hw);
5344 }
5345
5346 /**
5347 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5348 * @hw: pointer to the HW structure
5349 * @speed: pointer to store current link speed
5350 * @duplex: pointer to store the current link duplex
5351 *
5352 * Calls the generic get_speed_and_duplex to retrieve the current link
5353 * information and then calls the Kumeran lock loss workaround for links at
5354 * gigabit speeds.
5355 **/
e1000_get_link_up_info_ich8lan(struct e1000_hw * hw,u16 * speed,u16 * duplex)5356 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5357 u16 *duplex)
5358 {
5359 s32 ret_val;
5360
5361 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5362
5363 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5364 if (ret_val)
5365 return ret_val;
5366
5367 if ((hw->mac.type == e1000_ich8lan) &&
5368 (hw->phy.type == e1000_phy_igp_3) &&
5369 (*speed == SPEED_1000)) {
5370 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5371 }
5372
5373 return ret_val;
5374 }
5375
5376 /**
5377 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5378 * @hw: pointer to the HW structure
5379 *
5380 * Work-around for 82566 Kumeran PCS lock loss:
5381 * On link status change (i.e. PCI reset, speed change) and link is up and
5382 * speed is gigabit-
5383 * 0) if workaround is optionally disabled do nothing
5384 * 1) wait 1ms for Kumeran link to come up
5385 * 2) check Kumeran Diagnostic register PCS lock loss bit
5386 * 3) if not set the link is locked (all is good), otherwise...
5387 * 4) reset the PHY
5388 * 5) repeat up to 10 times
5389 * Note: this is only called for IGP3 copper when speed is 1gb.
5390 **/
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw * hw)5391 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5392 {
5393 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5394 u32 phy_ctrl;
5395 s32 ret_val;
5396 u16 i, data;
5397 bool link;
5398
5399 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5400
5401 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5402 return E1000_SUCCESS;
5403
5404 /* Make sure link is up before proceeding. If not just return.
5405 * Attempting this while link is negotiating fouled up link
5406 * stability
5407 */
5408 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5409 if (!link)
5410 return E1000_SUCCESS;
5411
5412 for (i = 0; i < 10; i++) {
5413 /* read once to clear */
5414 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5415 if (ret_val)
5416 return ret_val;
5417 /* and again to get new status */
5418 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5419 if (ret_val)
5420 return ret_val;
5421
5422 /* check for PCS lock */
5423 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5424 return E1000_SUCCESS;
5425
5426 /* Issue PHY reset */
5427 hw->phy.ops.reset(hw);
5428 msec_delay_irq(5);
5429 }
5430 /* Disable GigE link negotiation */
5431 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5432 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5433 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5434 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5435
5436 /* Call gig speed drop workaround on Gig disable before accessing
5437 * any PHY registers
5438 */
5439 e1000_gig_downshift_workaround_ich8lan(hw);
5440
5441 /* unable to acquire PCS lock */
5442 return -E1000_ERR_PHY;
5443 }
5444
5445 /**
5446 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5447 * @hw: pointer to the HW structure
5448 * @state: boolean value used to set the current Kumeran workaround state
5449 *
5450 * If ICH8, set the current Kumeran workaround state (enabled - true
5451 * /disabled - false).
5452 **/
e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw * hw,bool state)5453 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5454 bool state)
5455 {
5456 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5457
5458 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5459
5460 if (hw->mac.type != e1000_ich8lan) {
5461 DEBUGOUT("Workaround applies to ICH8 only.\n");
5462 return;
5463 }
5464
5465 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5466
5467 return;
5468 }
5469
5470 /**
5471 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5472 * @hw: pointer to the HW structure
5473 *
5474 * Workaround for 82566 power-down on D3 entry:
5475 * 1) disable gigabit link
5476 * 2) write VR power-down enable
5477 * 3) read it back
5478 * Continue if successful, else issue LCD reset and repeat
5479 **/
e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw * hw)5480 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5481 {
5482 u32 reg;
5483 u16 data;
5484 u8 retry = 0;
5485
5486 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5487
5488 if (hw->phy.type != e1000_phy_igp_3)
5489 return;
5490
5491 /* Try the workaround twice (if needed) */
5492 do {
5493 /* Disable link */
5494 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5495 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5496 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5497 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5498
5499 /* Call gig speed drop workaround on Gig disable before
5500 * accessing any PHY registers
5501 */
5502 if (hw->mac.type == e1000_ich8lan)
5503 e1000_gig_downshift_workaround_ich8lan(hw);
5504
5505 /* Write VR power-down enable */
5506 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5507 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5508 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5509 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5510
5511 /* Read it back and test */
5512 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5513 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5514 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5515 break;
5516
5517 /* Issue PHY reset and repeat at most one more time */
5518 reg = E1000_READ_REG(hw, E1000_CTRL);
5519 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5520 retry++;
5521 } while (retry);
5522 }
5523
5524 /**
5525 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5526 * @hw: pointer to the HW structure
5527 *
5528 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5529 * LPLU, Gig disable, MDIC PHY reset):
5530 * 1) Set Kumeran Near-end loopback
5531 * 2) Clear Kumeran Near-end loopback
5532 * Should only be called for ICH8[m] devices with any 1G Phy.
5533 **/
e1000_gig_downshift_workaround_ich8lan(struct e1000_hw * hw)5534 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5535 {
5536 s32 ret_val;
5537 u16 reg_data = 0;
5538
5539 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5540
5541 if ((hw->mac.type != e1000_ich8lan) ||
5542 (hw->phy.type == e1000_phy_ife))
5543 return;
5544
5545 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5546 ®_data);
5547 if (ret_val)
5548 return;
5549 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5550 ret_val = e1000_write_kmrn_reg_generic(hw,
5551 E1000_KMRNCTRLSTA_DIAG_OFFSET,
5552 reg_data);
5553 if (ret_val)
5554 return;
5555 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5556 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5557 reg_data);
5558 }
5559
5560 /**
5561 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5562 * @hw: pointer to the HW structure
5563 *
5564 * During S0 to Sx transition, it is possible the link remains at gig
5565 * instead of negotiating to a lower speed. Before going to Sx, set
5566 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5567 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5568 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5569 * needs to be written.
5570 * Parts that support (and are linked to a partner which support) EEE in
5571 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5572 * than 10Mbps w/o EEE.
5573 **/
e1000_suspend_workarounds_ich8lan(struct e1000_hw * hw)5574 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5575 {
5576 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5577 u32 phy_ctrl;
5578 s32 ret_val;
5579
5580 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5581
5582 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5583 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5584
5585 if (hw->phy.type == e1000_phy_i217) {
5586 u16 phy_reg, device_id = hw->device_id;
5587
5588 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5589 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5590 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5591 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5592 (hw->mac.type >= e1000_pch_spt)) {
5593 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5594
5595 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5596 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5597 }
5598
5599 ret_val = hw->phy.ops.acquire(hw);
5600 if (ret_val)
5601 goto out;
5602
5603 if (!dev_spec->eee_disable) {
5604 u16 eee_advert;
5605
5606 ret_val =
5607 e1000_read_emi_reg_locked(hw,
5608 I217_EEE_ADVERTISEMENT,
5609 &eee_advert);
5610 if (ret_val)
5611 goto release;
5612
5613 /* Disable LPLU if both link partners support 100BaseT
5614 * EEE and 100Full is advertised on both ends of the
5615 * link, and enable Auto Enable LPI since there will
5616 * be no driver to enable LPI while in Sx.
5617 */
5618 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5619 (dev_spec->eee_lp_ability &
5620 I82579_EEE_100_SUPPORTED) &&
5621 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5622 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5623 E1000_PHY_CTRL_NOND0A_LPLU);
5624
5625 /* Set Auto Enable LPI after link up */
5626 hw->phy.ops.read_reg_locked(hw,
5627 I217_LPI_GPIO_CTRL,
5628 &phy_reg);
5629 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5630 hw->phy.ops.write_reg_locked(hw,
5631 I217_LPI_GPIO_CTRL,
5632 phy_reg);
5633 }
5634 }
5635
5636 /* For i217 Intel Rapid Start Technology support,
5637 * when the system is going into Sx and no manageability engine
5638 * is present, the driver must configure proxy to reset only on
5639 * power good. LPI (Low Power Idle) state must also reset only
5640 * on power good, as well as the MTA (Multicast table array).
5641 * The SMBus release must also be disabled on LCD reset.
5642 */
5643 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5644 E1000_ICH_FWSM_FW_VALID)) {
5645 /* Enable proxy to reset only on power good. */
5646 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5647 &phy_reg);
5648 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5649 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5650 phy_reg);
5651
5652 /* Set bit enable LPI (EEE) to reset only on
5653 * power good.
5654 */
5655 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5656 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5657 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5658
5659 /* Disable the SMB release on LCD reset. */
5660 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5661 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5662 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5663 }
5664
5665 /* Enable MTA to reset for Intel Rapid Start Technology
5666 * Support
5667 */
5668 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5669 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5670 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5671
5672 release:
5673 hw->phy.ops.release(hw);
5674 }
5675 out:
5676 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5677
5678 if (hw->mac.type == e1000_ich8lan)
5679 e1000_gig_downshift_workaround_ich8lan(hw);
5680
5681 if (hw->mac.type >= e1000_pchlan) {
5682 e1000_oem_bits_config_ich8lan(hw, false);
5683
5684 /* Reset PHY to activate OEM bits on 82577/8 */
5685 if (hw->mac.type == e1000_pchlan)
5686 e1000_phy_hw_reset_generic(hw);
5687
5688 ret_val = hw->phy.ops.acquire(hw);
5689 if (ret_val)
5690 return;
5691 e1000_write_smbus_addr(hw);
5692 hw->phy.ops.release(hw);
5693 }
5694
5695 return;
5696 }
5697
5698 /**
5699 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5700 * @hw: pointer to the HW structure
5701 *
5702 * During Sx to S0 transitions on non-managed devices or managed devices
5703 * on which PHY resets are not blocked, if the PHY registers cannot be
5704 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5705 * the PHY.
5706 * On i217, setup Intel Rapid Start Technology.
5707 **/
e1000_resume_workarounds_pchlan(struct e1000_hw * hw)5708 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5709 {
5710 s32 ret_val;
5711
5712 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5713 if (hw->mac.type < e1000_pch2lan)
5714 return E1000_SUCCESS;
5715
5716 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5717 if (ret_val) {
5718 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5719 return ret_val;
5720 }
5721
5722 /* For i217 Intel Rapid Start Technology support when the system
5723 * is transitioning from Sx and no manageability engine is present
5724 * configure SMBus to restore on reset, disable proxy, and enable
5725 * the reset on MTA (Multicast table array).
5726 */
5727 if (hw->phy.type == e1000_phy_i217) {
5728 u16 phy_reg;
5729
5730 ret_val = hw->phy.ops.acquire(hw);
5731 if (ret_val) {
5732 DEBUGOUT("Failed to setup iRST\n");
5733 return ret_val;
5734 }
5735
5736 /* Clear Auto Enable LPI after link up */
5737 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5738 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5739 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5740
5741 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5742 E1000_ICH_FWSM_FW_VALID)) {
5743 /* Restore clear on SMB if no manageability engine
5744 * is present
5745 */
5746 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5747 &phy_reg);
5748 if (ret_val)
5749 goto release;
5750 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5751 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5752
5753 /* Disable Proxy */
5754 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5755 }
5756 /* Enable reset on MTA */
5757 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5758 &phy_reg);
5759 if (ret_val)
5760 goto release;
5761 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5762 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5763 release:
5764 if (ret_val)
5765 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5766 hw->phy.ops.release(hw);
5767 return ret_val;
5768 }
5769 return E1000_SUCCESS;
5770 }
5771
5772 /**
5773 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5774 * @hw: pointer to the HW structure
5775 *
5776 * Return the LED back to the default configuration.
5777 **/
e1000_cleanup_led_ich8lan(struct e1000_hw * hw)5778 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5779 {
5780 DEBUGFUNC("e1000_cleanup_led_ich8lan");
5781
5782 if (hw->phy.type == e1000_phy_ife)
5783 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5784 0);
5785
5786 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5787 return E1000_SUCCESS;
5788 }
5789
5790 /**
5791 * e1000_led_on_ich8lan - Turn LEDs on
5792 * @hw: pointer to the HW structure
5793 *
5794 * Turn on the LEDs.
5795 **/
e1000_led_on_ich8lan(struct e1000_hw * hw)5796 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5797 {
5798 DEBUGFUNC("e1000_led_on_ich8lan");
5799
5800 if (hw->phy.type == e1000_phy_ife)
5801 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5802 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5803
5804 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5805 return E1000_SUCCESS;
5806 }
5807
5808 /**
5809 * e1000_led_off_ich8lan - Turn LEDs off
5810 * @hw: pointer to the HW structure
5811 *
5812 * Turn off the LEDs.
5813 **/
e1000_led_off_ich8lan(struct e1000_hw * hw)5814 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5815 {
5816 DEBUGFUNC("e1000_led_off_ich8lan");
5817
5818 if (hw->phy.type == e1000_phy_ife)
5819 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5820 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5821
5822 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5823 return E1000_SUCCESS;
5824 }
5825
5826 /**
5827 * e1000_setup_led_pchlan - Configures SW controllable LED
5828 * @hw: pointer to the HW structure
5829 *
5830 * This prepares the SW controllable LED for use.
5831 **/
e1000_setup_led_pchlan(struct e1000_hw * hw)5832 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5833 {
5834 DEBUGFUNC("e1000_setup_led_pchlan");
5835
5836 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5837 (u16)hw->mac.ledctl_mode1);
5838 }
5839
5840 /**
5841 * e1000_cleanup_led_pchlan - Restore the default LED operation
5842 * @hw: pointer to the HW structure
5843 *
5844 * Return the LED back to the default configuration.
5845 **/
e1000_cleanup_led_pchlan(struct e1000_hw * hw)5846 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5847 {
5848 DEBUGFUNC("e1000_cleanup_led_pchlan");
5849
5850 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5851 (u16)hw->mac.ledctl_default);
5852 }
5853
5854 /**
5855 * e1000_led_on_pchlan - Turn LEDs on
5856 * @hw: pointer to the HW structure
5857 *
5858 * Turn on the LEDs.
5859 **/
e1000_led_on_pchlan(struct e1000_hw * hw)5860 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5861 {
5862 u16 data = (u16)hw->mac.ledctl_mode2;
5863 u32 i, led;
5864
5865 DEBUGFUNC("e1000_led_on_pchlan");
5866
5867 /* If no link, then turn LED on by setting the invert bit
5868 * for each LED that's mode is "link_up" in ledctl_mode2.
5869 */
5870 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5871 for (i = 0; i < 3; i++) {
5872 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5873 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5874 E1000_LEDCTL_MODE_LINK_UP)
5875 continue;
5876 if (led & E1000_PHY_LED0_IVRT)
5877 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5878 else
5879 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5880 }
5881 }
5882
5883 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5884 }
5885
5886 /**
5887 * e1000_led_off_pchlan - Turn LEDs off
5888 * @hw: pointer to the HW structure
5889 *
5890 * Turn off the LEDs.
5891 **/
e1000_led_off_pchlan(struct e1000_hw * hw)5892 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5893 {
5894 u16 data = (u16)hw->mac.ledctl_mode1;
5895 u32 i, led;
5896
5897 DEBUGFUNC("e1000_led_off_pchlan");
5898
5899 /* If no link, then turn LED off by clearing the invert bit
5900 * for each LED that's mode is "link_up" in ledctl_mode1.
5901 */
5902 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5903 for (i = 0; i < 3; i++) {
5904 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5905 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5906 E1000_LEDCTL_MODE_LINK_UP)
5907 continue;
5908 if (led & E1000_PHY_LED0_IVRT)
5909 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5910 else
5911 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5912 }
5913 }
5914
5915 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5916 }
5917
5918 /**
5919 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5920 * @hw: pointer to the HW structure
5921 *
5922 * Read appropriate register for the config done bit for completion status
5923 * and configure the PHY through s/w for EEPROM-less parts.
5924 *
5925 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5926 * config done bit, so only an error is logged and continues. If we were
5927 * to return with error, EEPROM-less silicon would not be able to be reset
5928 * or change link.
5929 **/
e1000_get_cfg_done_ich8lan(struct e1000_hw * hw)5930 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5931 {
5932 s32 ret_val = E1000_SUCCESS;
5933 u32 bank = 0;
5934 u32 status;
5935
5936 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5937
5938 e1000_get_cfg_done_generic(hw);
5939
5940 /* Wait for indication from h/w that it has completed basic config */
5941 if (hw->mac.type >= e1000_ich10lan) {
5942 e1000_lan_init_done_ich8lan(hw);
5943 } else {
5944 ret_val = e1000_get_auto_rd_done_generic(hw);
5945 if (ret_val) {
5946 /* When auto config read does not complete, do not
5947 * return with an error. This can happen in situations
5948 * where there is no eeprom and prevents getting link.
5949 */
5950 DEBUGOUT("Auto Read Done did not complete\n");
5951 ret_val = E1000_SUCCESS;
5952 }
5953 }
5954
5955 /* Clear PHY Reset Asserted bit */
5956 status = E1000_READ_REG(hw, E1000_STATUS);
5957 if (status & E1000_STATUS_PHYRA)
5958 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5959 else
5960 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5961
5962 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5963 if (hw->mac.type <= e1000_ich9lan) {
5964 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5965 (hw->phy.type == e1000_phy_igp_3)) {
5966 e1000_phy_init_script_igp3(hw);
5967 }
5968 } else {
5969 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5970 /* Maybe we should do a basic PHY config */
5971 DEBUGOUT("EEPROM not present\n");
5972 ret_val = -E1000_ERR_CONFIG;
5973 }
5974 }
5975
5976 return ret_val;
5977 }
5978
5979 /**
5980 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5981 * @hw: pointer to the HW structure
5982 *
5983 * In the case of a PHY power down to save power, or to turn off link during a
5984 * driver unload, or wake on lan is not enabled, remove the link.
5985 **/
e1000_power_down_phy_copper_ich8lan(struct e1000_hw * hw)5986 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5987 {
5988 /* If the management interface is not enabled, then power down */
5989 if (!(hw->mac.ops.check_mng_mode(hw) ||
5990 hw->phy.ops.check_reset_block(hw)))
5991 e1000_power_down_phy_copper(hw);
5992
5993 return;
5994 }
5995
5996 /**
5997 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5998 * @hw: pointer to the HW structure
5999 *
6000 * Clears hardware counters specific to the silicon family and calls
6001 * clear_hw_cntrs_generic to clear all general purpose counters.
6002 **/
e1000_clear_hw_cntrs_ich8lan(struct e1000_hw * hw)6003 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6004 {
6005 u16 phy_data;
6006 s32 ret_val;
6007
6008 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6009
6010 e1000_clear_hw_cntrs_base_generic(hw);
6011
6012 E1000_READ_REG(hw, E1000_ALGNERRC);
6013 E1000_READ_REG(hw, E1000_RXERRC);
6014 E1000_READ_REG(hw, E1000_TNCRS);
6015 E1000_READ_REG(hw, E1000_CEXTERR);
6016 E1000_READ_REG(hw, E1000_TSCTC);
6017 E1000_READ_REG(hw, E1000_TSCTFC);
6018
6019 E1000_READ_REG(hw, E1000_MGTPRC);
6020 E1000_READ_REG(hw, E1000_MGTPDC);
6021 E1000_READ_REG(hw, E1000_MGTPTC);
6022
6023 E1000_READ_REG(hw, E1000_IAC);
6024 E1000_READ_REG(hw, E1000_ICRXOC);
6025
6026 /* Clear PHY statistics registers */
6027 if ((hw->phy.type == e1000_phy_82578) ||
6028 (hw->phy.type == e1000_phy_82579) ||
6029 (hw->phy.type == e1000_phy_i217) ||
6030 (hw->phy.type == e1000_phy_82577)) {
6031 ret_val = hw->phy.ops.acquire(hw);
6032 if (ret_val)
6033 return;
6034 ret_val = hw->phy.ops.set_page(hw,
6035 HV_STATS_PAGE << IGP_PAGE_SHIFT);
6036 if (ret_val)
6037 goto release;
6038 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6039 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6040 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6041 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6042 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6043 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6044 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6045 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6046 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6047 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6048 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6049 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6050 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6051 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6052 release:
6053 hw->phy.ops.release(hw);
6054 }
6055 }
6056
6057 /**
6058 * e1000_configure_k0s_lpt - Configure K0s power state
6059 * @hw: pointer to the HW structure
6060 * @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
6061 * 0 corresponds to 128ns, each value over 0 doubles the duration.
6062 * @min_time: Minimum Tx idle period allowed - valid values are 0 to 4.
6063 * 0 corresponds to 128ns, each value over 0 doubles the duration.
6064 *
6065 * Configure the K1 power state based on the provided parameter.
6066 * Assumes semaphore already acquired.
6067 *
6068 * Success returns 0, Failure returns:
6069 * -E1000_ERR_PHY (-2) in case of access error
6070 * -E1000_ERR_PARAM (-4) in case of parameters error
6071 **/
e1000_configure_k0s_lpt(struct e1000_hw * hw,u8 entry_latency,u8 min_time)6072 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
6073 {
6074 s32 ret_val;
6075 u16 kmrn_reg = 0;
6076
6077 DEBUGFUNC("e1000_configure_k0s_lpt");
6078
6079 if (entry_latency > 3 || min_time > 4)
6080 return -E1000_ERR_PARAM;
6081
6082 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6083 &kmrn_reg);
6084 if (ret_val)
6085 return ret_val;
6086
6087 /* for now don't touch the latency */
6088 kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
6089 kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
6090
6091 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6092 kmrn_reg);
6093 if (ret_val)
6094 return ret_val;
6095
6096 return E1000_SUCCESS;
6097 }
6098