1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2020 Intel Corporation
3 */
4
5 #ifndef _ICE_OSDEP_H_
6 #define _ICE_OSDEP_H_
7
8 #include <string.h>
9 #include <stdint.h>
10 #include <stdio.h>
11 #include <stdarg.h>
12 #include <inttypes.h>
13 #include <sys/queue.h>
14 #include <stdbool.h>
15
16 #include <rte_common.h>
17 #include <rte_memcpy.h>
18 #include <rte_malloc.h>
19 #include <rte_memzone.h>
20 #include <rte_byteorder.h>
21 #include <rte_cycles.h>
22 #include <rte_spinlock.h>
23 #include <rte_log.h>
24 #include <rte_random.h>
25 #include <rte_io.h>
26
27 #include "ice_alloc.h"
28
29 #include "../ice_logs.h"
30
31 #ifndef __INTEL_NET_BASE_OSDEP__
32 #define __INTEL_NET_BASE_OSDEP__
33
34 #define INLINE inline
35 #define STATIC static
36
37 typedef uint8_t u8;
38 typedef int8_t s8;
39 typedef uint16_t u16;
40 typedef int16_t s16;
41 typedef uint32_t u32;
42 typedef int32_t s32;
43 typedef uint64_t u64;
44 typedef uint64_t s64;
45
46 #ifndef __le16
47 #define __le16 uint16_t
48 #endif
49 #ifndef __le32
50 #define __le32 uint32_t
51 #endif
52 #ifndef __le64
53 #define __le64 uint64_t
54 #endif
55 #ifndef __be16
56 #define __be16 uint16_t
57 #endif
58 #ifndef __be32
59 #define __be32 uint32_t
60 #endif
61 #ifndef __be64
62 #define __be64 uint64_t
63 #endif
64
65 #define min(a, b) RTE_MIN(a, b)
66 #define max(a, b) RTE_MAX(a, b)
67
68 #define FIELD_SIZEOF(t, f) RTE_SIZEOF_FIELD(t, f)
69 #define ARRAY_SIZE(arr) RTE_DIM(arr)
70
71 #define CPU_TO_LE16(o) rte_cpu_to_le_16(o)
72 #define CPU_TO_LE32(s) rte_cpu_to_le_32(s)
73 #define CPU_TO_LE64(h) rte_cpu_to_le_64(h)
74 #define LE16_TO_CPU(a) rte_le_to_cpu_16(a)
75 #define LE32_TO_CPU(c) rte_le_to_cpu_32(c)
76 #define LE64_TO_CPU(k) rte_le_to_cpu_64(k)
77
78 #define CPU_TO_BE16(o) rte_cpu_to_be_16(o)
79 #define CPU_TO_BE32(o) rte_cpu_to_be_32(o)
80 #define CPU_TO_BE64(o) rte_cpu_to_be_64(o)
81 #define BE16_TO_CPU(o) rte_be_to_cpu_16(o)
82
83 #define NTOHS(a) rte_be_to_cpu_16(a)
84 #define NTOHL(a) rte_be_to_cpu_32(a)
85 #define HTONS(a) rte_cpu_to_be_16(a)
86 #define HTONL(a) rte_cpu_to_be_32(a)
87
88 static __rte_always_inline uint32_t
readl(volatile void * addr)89 readl(volatile void *addr)
90 {
91 return rte_le_to_cpu_32(rte_read32(addr));
92 }
93
94 static __rte_always_inline void
writel(uint32_t value,volatile void * addr)95 writel(uint32_t value, volatile void *addr)
96 {
97 rte_write32(rte_cpu_to_le_32(value), addr);
98 }
99
100 static __rte_always_inline void
writel_relaxed(uint32_t value,volatile void * addr)101 writel_relaxed(uint32_t value, volatile void *addr)
102 {
103 rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
104 }
105
106 static __rte_always_inline uint64_t
readq(volatile void * addr)107 readq(volatile void *addr)
108 {
109 return rte_le_to_cpu_64(rte_read64(addr));
110 }
111
112 static __rte_always_inline void
writeq(uint64_t value,volatile void * addr)113 writeq(uint64_t value, volatile void *addr)
114 {
115 rte_write64(rte_cpu_to_le_64(value), addr);
116 }
117
118 #define wr32(a, reg, value) writel((value), (a)->hw_addr + (reg))
119 #define rd32(a, reg) readl((a)->hw_addr + (reg))
120 #define wr64(a, reg, value) writeq((value), (a)->hw_addr + (reg))
121 #define rd64(a, reg) readq((a)->hw_addr + (reg))
122
123 #endif /* __INTEL_NET_BASE_OSDEP__ */
124
125 #ifndef __always_unused
126 #define __always_unused __rte_unused
127 #endif
128 #ifndef __maybe_unused
129 #define __maybe_unused __rte_unused
130 #endif
131 #ifndef __packed
132 #define __packed __rte_packed
133 #endif
134
135 #ifndef BIT_ULL
136 #define BIT_ULL(a) (1ULL << (a))
137 #endif
138
139 #define MAKEMASK(m, s) ((m) << (s))
140
141 #define ice_debug(h, m, s, ...) \
142 do { \
143 if (((m) & (h)->debug_mask)) \
144 PMD_DRV_LOG_RAW(DEBUG, "ice %02x.%x " s, \
145 (h)->bus.device, (h)->bus.func, \
146 ##__VA_ARGS__); \
147 } while (0)
148
149 #define ice_info(hw, fmt, args...) ice_debug(hw, ICE_DBG_ALL, fmt, ##args)
150 #define ice_warn(hw, fmt, args...) ice_debug(hw, ICE_DBG_ALL, fmt, ##args)
151 #define ice_debug_array(hw, type, rowsize, groupsize, buf, len) \
152 do { \
153 struct ice_hw *hw_l = hw; \
154 u16 len_l = len; \
155 u8 *buf_l = buf; \
156 int i; \
157 for (i = 0; i < len_l; i += 8) \
158 ice_debug(hw_l, type, \
159 "0x%04X 0x%016"PRIx64"\n", \
160 i, *((u64 *)((buf_l) + i))); \
161 } while (0)
162 #define ice_snprintf snprintf
163 #ifndef SNPRINTF
164 #define SNPRINTF ice_snprintf
165 #endif
166
167 #define ICE_PCI_REG_WRITE(reg, value) writel(value, reg)
168 #define ICE_PCI_REG_WC_WRITE(reg, value) rte_write32_wc(value, reg)
169
170 #define ICE_READ_REG(hw, reg) rd32(hw, reg)
171 #define ICE_WRITE_REG(hw, reg, value) wr32(hw, reg, value)
172
173 #define ice_flush(a) ICE_READ_REG((a), GLGEN_STAT)
174 #define icevf_flush(a) ICE_READ_REG((a), VFGEN_RSTAT)
175
176 #define flush(a) ICE_READ_REG((a), GLGEN_STAT)
177 #define div64_long(n, d) ((n) / (d))
178
179 #define BITS_PER_BYTE 8
180
181 /* memory allocation tracking */
182 struct ice_dma_mem {
183 void *va;
184 u64 pa;
185 u32 size;
186 const void *zone;
187 } __rte_packed;
188
189 struct ice_virt_mem {
190 void *va;
191 u32 size;
192 } __rte_packed;
193
194 #define ice_malloc(h, s) rte_zmalloc(NULL, s, 0)
195 #define ice_calloc(h, c, s) rte_zmalloc(NULL, (c) * (s), 0)
196 #define ice_free(h, m) rte_free(m)
197
198 #define ice_memset(a, b, c, d) memset((a), (b), (c))
199 #define ice_memcpy(a, b, c, d) rte_memcpy((a), (b), (c))
200
201 /* SW spinlock */
202 struct ice_lock {
203 rte_spinlock_t spinlock;
204 };
205
206 static inline void
ice_init_lock(struct ice_lock * sp)207 ice_init_lock(struct ice_lock *sp)
208 {
209 rte_spinlock_init(&sp->spinlock);
210 }
211
212 static inline void
ice_acquire_lock(struct ice_lock * sp)213 ice_acquire_lock(struct ice_lock *sp)
214 {
215 rte_spinlock_lock(&sp->spinlock);
216 }
217
218 static inline void
ice_release_lock(struct ice_lock * sp)219 ice_release_lock(struct ice_lock *sp)
220 {
221 rte_spinlock_unlock(&sp->spinlock);
222 }
223
224 static inline void
ice_destroy_lock(__rte_unused struct ice_lock * sp)225 ice_destroy_lock(__rte_unused struct ice_lock *sp)
226 {
227 }
228
229 struct ice_hw;
230
231 static __rte_always_inline void *
ice_memdup(__rte_unused struct ice_hw * hw,const void * src,size_t size,__rte_unused enum ice_memcpy_type dir)232 ice_memdup(__rte_unused struct ice_hw *hw, const void *src, size_t size,
233 __rte_unused enum ice_memcpy_type dir)
234 {
235 void *p;
236
237 p = ice_malloc(hw, size);
238 if (p)
239 rte_memcpy(p, src, size);
240
241 return p;
242 }
243
244 static inline void *
ice_alloc_dma_mem(__rte_unused struct ice_hw * hw,struct ice_dma_mem * mem,u64 size)245 ice_alloc_dma_mem(__rte_unused struct ice_hw *hw,
246 struct ice_dma_mem *mem, u64 size)
247 {
248 const struct rte_memzone *mz = NULL;
249 char z_name[RTE_MEMZONE_NAMESIZE];
250
251 if (!mem)
252 return NULL;
253
254 snprintf(z_name, sizeof(z_name), "ice_dma_%"PRIu64, rte_rand());
255 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
256 0, RTE_PGSIZE_2M);
257 if (!mz)
258 return NULL;
259
260 mem->size = size;
261 mem->va = mz->addr;
262 mem->pa = mz->iova;
263 mem->zone = (const void *)mz;
264 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
265 "%"PRIu64, mz->name, mem->pa);
266
267 return mem->va;
268 }
269
270 static inline void
ice_free_dma_mem(__rte_unused struct ice_hw * hw,struct ice_dma_mem * mem)271 ice_free_dma_mem(__rte_unused struct ice_hw *hw,
272 struct ice_dma_mem *mem)
273 {
274 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
275 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
276 mem->pa);
277 rte_memzone_free((const struct rte_memzone *)mem->zone);
278 mem->zone = NULL;
279 mem->va = NULL;
280 mem->pa = (u64)0;
281 }
282
283 static inline u8
ice_hweight8(u32 num)284 ice_hweight8(u32 num)
285 {
286 u8 bits = 0;
287 u32 i;
288
289 for (i = 0; i < 8; i++) {
290 bits += (u8)(num & 0x1);
291 num >>= 1;
292 }
293
294 return bits;
295 }
296
297 static inline u8
ice_hweight32(u32 num)298 ice_hweight32(u32 num)
299 {
300 u8 bits = 0;
301 u32 i;
302
303 for (i = 0; i < 32; i++) {
304 bits += (u8)(num & 0x1);
305 num >>= 1;
306 }
307
308 return bits;
309 }
310
311 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
312 #define DELAY(x) rte_delay_us(x)
313 #define ice_usec_delay(x, y) rte_delay_us(x)
314 #define ice_msec_delay(x, y) rte_delay_us(1000 * (x))
315 #define udelay(x) DELAY(x)
316 #define msleep(x) DELAY(1000 * (x))
317 #define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))
318
319 struct ice_list_entry {
320 LIST_ENTRY(ice_list_entry) next;
321 };
322
323 LIST_HEAD(ice_list_head, ice_list_entry);
324
325 #define LIST_ENTRY_TYPE ice_list_entry
326 #define LIST_HEAD_TYPE ice_list_head
327 #define INIT_LIST_HEAD(list_head) LIST_INIT(list_head)
328 #define LIST_DEL(entry) LIST_REMOVE(entry, next)
329 /* LIST_EMPTY(list_head)) the same in sys/queue.h */
330
331 /*Note parameters are swapped*/
332 #define LIST_FIRST_ENTRY(head, type, field) (type *)((head)->lh_first)
333 #define LIST_NEXT_ENTRY(entry, type, field) \
334 ((type *)(entry)->field.next.le_next)
335 #define LIST_ADD(entry, list_head) LIST_INSERT_HEAD(list_head, entry, next)
336 #define LIST_ADD_AFTER(entry, list_entry) \
337 LIST_INSERT_AFTER(list_entry, entry, next)
338
list_add_tail(struct ice_list_entry * entry,struct ice_list_head * head)339 static inline void list_add_tail(struct ice_list_entry *entry,
340 struct ice_list_head *head)
341 {
342 struct ice_list_entry *tail = head->lh_first;
343
344 if (tail == NULL) {
345 LIST_INSERT_HEAD(head, entry, next);
346 return;
347 }
348 while (tail->next.le_next != NULL)
349 tail = tail->next.le_next;
350 LIST_INSERT_AFTER(tail, entry, next);
351 }
352
353 #define LIST_ADD_TAIL(entry, head) list_add_tail(entry, head)
354 #define LIST_FOR_EACH_ENTRY(pos, head, type, member) \
355 for ((pos) = (head)->lh_first ? \
356 container_of((head)->lh_first, struct type, member) : \
357 0; \
358 (pos); \
359 (pos) = (pos)->member.next.le_next ? \
360 container_of((pos)->member.next.le_next, struct type, \
361 member) : \
362 0)
363
364 #define LIST_FOR_EACH_ENTRY_SAFE(pos, tmp, head, type, member) \
365 for ((pos) = (head)->lh_first ? \
366 container_of((head)->lh_first, struct type, member) : \
367 0, \
368 (tmp) = (pos) == 0 ? 0 : ((pos)->member.next.le_next ? \
369 container_of((pos)->member.next.le_next, struct type, \
370 member) : \
371 0); \
372 (pos); \
373 (pos) = (tmp), \
374 (tmp) = (pos) == 0 ? 0 : ((tmp)->member.next.le_next ? \
375 container_of((pos)->member.next.le_next, struct type, \
376 member) : \
377 0))
378
379 #define LIST_REPLACE_INIT(list_head, head) do { \
380 (head)->lh_first = (list_head)->lh_first; \
381 INIT_LIST_HEAD(list_head); \
382 } while (0)
383
384 #define HLIST_NODE_TYPE LIST_ENTRY_TYPE
385 #define HLIST_HEAD_TYPE LIST_HEAD_TYPE
386 #define INIT_HLIST_HEAD(list_head) INIT_LIST_HEAD(list_head)
387 #define HLIST_ADD_HEAD(entry, list_head) LIST_ADD(entry, list_head)
388 #define HLIST_EMPTY(list_head) LIST_EMPTY(list_head)
389 #define HLIST_DEL(entry) LIST_DEL(entry)
390 #define HLIST_FOR_EACH_ENTRY(pos, head, type, member) \
391 LIST_FOR_EACH_ENTRY(pos, head, type, member)
392
393 #ifndef ICE_DBG_TRACE
394 #define ICE_DBG_TRACE BIT_ULL(0)
395 #endif
396
397 #ifndef DIVIDE_AND_ROUND_UP
398 #define DIVIDE_AND_ROUND_UP(a, b) (((a) + (b) - 1) / (b))
399 #endif
400
401 #ifndef ICE_INTEL_VENDOR_ID
402 #define ICE_INTEL_VENDOR_ID 0x8086
403 #endif
404
405 #ifndef IS_UNICAST_ETHER_ADDR
406 #define IS_UNICAST_ETHER_ADDR(addr) \
407 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 0))
408 #endif
409
410 #ifndef IS_MULTICAST_ETHER_ADDR
411 #define IS_MULTICAST_ETHER_ADDR(addr) \
412 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 1))
413 #endif
414
415 #ifndef IS_BROADCAST_ETHER_ADDR
416 /* Check whether an address is broadcast. */
417 #define IS_BROADCAST_ETHER_ADDR(addr) \
418 ((bool)((((u16 *)(addr))[0] == ((u16)0xffff))))
419 #endif
420
421 #ifndef IS_ZERO_ETHER_ADDR
422 #define IS_ZERO_ETHER_ADDR(addr) \
423 (((bool)((((u16 *)(addr))[0] == ((u16)0x0)))) && \
424 ((bool)((((u16 *)(addr))[1] == ((u16)0x0)))) && \
425 ((bool)((((u16 *)(addr))[2] == ((u16)0x0)))))
426 #endif
427
428 #endif /* _ICE_OSDEP_H_ */
429