| /f-stack/freebsd/contrib/device-tree/Bindings/clock/ |
| H A D | allwinner,sun4i-a10-gates-clk.yaml | 24 - const: allwinner,sun4i-a10-gates-clk
25 - const: allwinner,sun4i-a10-axi-gates-clk
26 - const: allwinner,sun4i-a10-ahb-gates-clk
27 - const: allwinner,sun5i-a10s-ahb-gates-clk
28 - const: allwinner,sun5i-a13-ahb-gates-clk
29 - const: allwinner,sun7i-a20-ahb-gates-clk
30 - const: allwinner,sun6i-a31-ahb1-gates-clk
31 - const: allwinner,sun8i-a23-ahb1-gates-clk
32 - const: allwinner,sun9i-a80-ahb0-gates-clk
33 - const: allwinner,sun9i-a80-ahb1-gates-clk
[all …]
|
| H A D | allwinner,sun8i-h3-bus-gates-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml#
23 const: allwinner,sun8i-h3-bus-gates-clk
59 compatible = "allwinner,sun8i-h3-bus-gates-clk";
|
| H A D | renesas,cpg-mstp-clocks.yaml | 13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
14 organized in groups of up to 32 gates.
|
| H A D | st,nomadik.txt | 7 PLLs and clock gates.
34 HCLK nodes: these represent the clock gates on individual
|
| H A D | ingenic,cgu.yaml | 11 typically includes a variety of PLLs, multiplexers, dividers & gates in order
|
| H A D | alphascale,acc.txt | 4 clock source, setting deviders and clock gates.
|
| H A D | imx8qxp-lpcg.yaml | 14 model to control the clock gates for the peripherals. An LPCG module
|
| H A D | pistachio-clock.txt | 103 gates for the external clocks "audio_clk_in" and "enet_clk_in".
|
| /f-stack/freebsd/arm64/rockchip/clk/ |
| H A D | rk_cru.c | 191 if (sc->gates[i].name == NULL) in rk_cru_register_gates()
194 def.clkdef.id = sc->gates[i].id; in rk_cru_register_gates()
195 def.clkdef.name = sc->gates[i].name; in rk_cru_register_gates()
196 def.clkdef.parent_names = &sc->gates[i].parent_name; in rk_cru_register_gates()
198 def.offset = sc->gates[i].offset; in rk_cru_register_gates()
199 def.shift = sc->gates[i].shift; in rk_cru_register_gates()
277 if (sc->gates) in rk_cru_attach()
|
| H A D | rk_cru.h | 240 struct rk_cru_gate *gates; member
|
| /f-stack/freebsd/arm/allwinner/clkng/ |
| H A D | aw_ccung.c | 192 if (sc->gates[i].name == NULL) in aw_ccung_register_gates()
196 def.clkdef.name = sc->gates[i].name; in aw_ccung_register_gates()
197 def.clkdef.parent_names = &sc->gates[i].parent_name; in aw_ccung_register_gates()
199 def.offset = sc->gates[i].offset; in aw_ccung_register_gates()
200 def.shift = sc->gates[i].shift; in aw_ccung_register_gates()
329 if (sc->gates) in aw_ccung_attach()
|
| H A D | ccu_de2.c | 181 sc->gates = h3_de2_ccu_gates; in ccu_de2_attach()
189 sc->gates = a64_de2_ccu_gates; in ccu_de2_attach()
|
| H A D | ccu_sun8i_r.c | 196 sc->gates = ccu_sun8i_r_gates; in ccu_sun8i_r_attach()
243 sc->gates = ccu_sun8i_r_gates; in ccu_a83t_r_attach()
|
| H A D | aw_ccung.h | 85 struct aw_ccung_gate *gates; member
|
| H A D | ccu_h6_r.c | 150 sc->gates = ccu_sun50i_h6_r_gates; in ccu_sun50i_h6_r_attach()
|
| H A D | ccu_h6.c | 479 sc->gates = h6_ccu_gates; in ccu_h6_attach()
|
| H A D | ccu_a10.c | 601 sc->gates = a10_ccu_gates; in ccu_a10_attach()
|
| /f-stack/freebsd/contrib/device-tree/Bindings/i2c/ |
| H A D | i2c-gate.txt | 4 there are no competing masters to consider for gates and therefore there is
5 no arbitration happening for gates.
|
| /f-stack/freebsd/contrib/device-tree/Bindings/mfd/ |
| H A D | allwinner,sun8i-a23-prcm.yaml | 31 - allwinner,sun8i-a23-apb0-gates-clk
73 const: allwinner,sun8i-a23-apb0-gates-clk
182 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
|
| H A D | allwinner,sun6i-a31-prcm.yaml | 31 - allwinner,sun6i-a31-apb0-gates-clk
71 const: allwinner,sun6i-a31-apb0-gates-clk
197 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
|
| /f-stack/freebsd/contrib/device-tree/Bindings/sound/ |
| H A D | nvidia,tegra-audio-rt5677.txt | 33 - nvidia,dmic-clk-en-gpios : The GPIO that gates DMIC clock signal
|
| /f-stack/freebsd/contrib/device-tree/Bindings/clock/ti/davinci/ |
| H A D | pll.txt | 4 to the PLL itself, this controller also contains bypasses, gates, dividers,
|
| H A D | da8xx-cfgchip.txt | 5 gates. This document describes the bindings for those clocks.
|
| /f-stack/freebsd/contrib/device-tree/Bindings/clock/ti/ |
| H A D | gate.txt | 42 gates the clock and clearing the bit ungates the clock.
|
| /f-stack/freebsd/contrib/device-tree/Bindings/display/ |
| H A D | allwinner,sun8i-r40-tcon-top.yaml | 17 encoder clock source and contains additional TV TCON and DSI gates.
|