1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
3 */
4
5 #ifndef __OTX2_MBOX_H__
6 #define __OTX2_MBOX_H__
7
8 #include <errno.h>
9 #include <stdbool.h>
10
11 #include <rte_ether.h>
12 #include <rte_spinlock.h>
13
14 #include <otx2_common.h>
15
16 #define SZ_64K (64ULL * 1024ULL)
17 #define SZ_1K (1ULL * 1024ULL)
18 #define MBOX_SIZE SZ_64K
19
20 /* AF/PF: PF initiated, PF/VF VF initiated */
21 #define MBOX_DOWN_RX_START 0
22 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
23 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
24 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
25 /* AF/PF: AF initiated, PF/VF PF initiated */
26 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
27 #define MBOX_UP_RX_SIZE SZ_1K
28 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
29 #define MBOX_UP_TX_SIZE SZ_1K
30
31 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
32 # error "Incorrect mailbox area sizes"
33 #endif
34
35 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
36
37 #define MBOX_RSP_TIMEOUT 3000 /* Time to wait for mbox response in ms */
38
39 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
40
41 /* Mailbox directions */
42 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
43 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
44 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
45 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
46 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
47 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
48 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
49 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
50
51 /* Device memory does not support unaligned access, instruct compiler to
52 * not optimize the memory access when working with mailbox memory.
53 */
54 #define __otx2_io volatile
55
56 struct otx2_mbox_dev {
57 void *mbase; /* This dev's mbox region */
58 rte_spinlock_t mbox_lock;
59 uint16_t msg_size; /* Total msg size to be sent */
60 uint16_t rsp_size; /* Total rsp size to be sure the reply is ok */
61 uint16_t num_msgs; /* No of msgs sent or waiting for response */
62 uint16_t msgs_acked; /* No of msgs for which response is received */
63 };
64
65 struct otx2_mbox {
66 uintptr_t hwbase; /* Mbox region advertised by HW */
67 uintptr_t reg_base;/* CSR base for this dev */
68 uint64_t trigger; /* Trigger mbox notification */
69 uint16_t tr_shift; /* Mbox trigger shift */
70 uint64_t rx_start; /* Offset of Rx region in mbox memory */
71 uint64_t tx_start; /* Offset of Tx region in mbox memory */
72 uint16_t rx_size; /* Size of Rx region */
73 uint16_t tx_size; /* Size of Tx region */
74 uint16_t ndevs; /* The number of peers */
75 struct otx2_mbox_dev *dev;
76 uint64_t intr_offset; /* Offset to interrupt register */
77 };
78
79 /* Header which precedes all mbox messages */
80 struct mbox_hdr {
81 uint64_t __otx2_io msg_size; /* Total msgs size embedded */
82 uint16_t __otx2_io num_msgs; /* No of msgs embedded */
83 };
84
85 /* Header which precedes every msg and is also part of it */
86 struct mbox_msghdr {
87 uint16_t __otx2_io pcifunc; /* Who's sending this msg */
88 uint16_t __otx2_io id; /* Mbox message ID */
89 #define OTX2_MBOX_REQ_SIG (0xdead)
90 #define OTX2_MBOX_RSP_SIG (0xbeef)
91 /* Signature, for validating corrupted msgs */
92 uint16_t __otx2_io sig;
93 #define OTX2_MBOX_VERSION (0x000a)
94 /* Version of msg's structure for this ID */
95 uint16_t __otx2_io ver;
96 /* Offset of next msg within mailbox region */
97 uint16_t __otx2_io next_msgoff;
98 int __otx2_io rc; /* Msg processed response code */
99 };
100
101 /* Mailbox message types */
102 #define MBOX_MSG_MASK 0xFFFF
103 #define MBOX_MSG_INVALID 0xFFFE
104 #define MBOX_MSG_MAX 0xFFFF
105
106 #define MBOX_MESSAGES \
107 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
108 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
109 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach_req, msg_rsp)\
110 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach_req, msg_rsp)\
111 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
112 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
113 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
114 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
115 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
116 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
117 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
118 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
119 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
120 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
121 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get,\
122 cgx_mac_addr_set_or_get) \
123 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get,\
124 cgx_mac_addr_set_or_get) \
125 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
126 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
127 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
128 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
129 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg)\
130 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
131 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
132 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
133 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
134 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
135 cgx_pause_frm_cfg) \
136 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
137 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
138 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
139 cgx_mac_addr_add_rsp) \
140 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
141 msg_rsp) \
142 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
143 cgx_max_dmac_entries_get_rsp) \
144 M(CGX_SET_LINK_STATE, 0x214, cgx_set_link_state, \
145 cgx_set_link_state_msg, msg_rsp) \
146 M(CGX_GET_PHY_MOD_TYPE, 0x215, cgx_get_phy_mod_type, msg_req, \
147 cgx_phy_mod_type) \
148 M(CGX_SET_PHY_MOD_TYPE, 0x216, cgx_set_phy_mod_type, cgx_phy_mod_type, \
149 msg_rsp) \
150 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
151 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
152 cgx_set_link_mode_rsp) \
153 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
154 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \
155 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
156 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, npa_lf_alloc_req, \
157 npa_lf_alloc_rsp) \
158 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
159 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp)\
160 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
161 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
162 M(SSO_LF_ALLOC, 0x600, sso_lf_alloc, sso_lf_alloc_req, \
163 sso_lf_alloc_rsp) \
164 M(SSO_LF_FREE, 0x601, sso_lf_free, sso_lf_free_req, msg_rsp) \
165 M(SSOW_LF_ALLOC, 0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp)\
166 M(SSOW_LF_FREE, 0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp) \
167 M(SSO_HW_SETCONFIG, 0x604, sso_hw_setconfig, sso_hw_setconfig, \
168 msg_rsp) \
169 M(SSO_GRP_SET_PRIORITY, 0x605, sso_grp_set_priority, sso_grp_priority, \
170 msg_rsp) \
171 M(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req, \
172 sso_grp_priority) \
173 M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp) \
174 M(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg, \
175 msg_rsp) \
176 M(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req, \
177 sso_grp_stats) \
178 M(SSO_HWS_GET_STATS, 0x610, sso_hws_get_stats, sso_info_req, \
179 sso_hws_stats) \
180 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
181 M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \
182 tim_lf_alloc_rsp) \
183 M(TIM_LF_FREE, 0x801, tim_lf_free, tim_ring_req, msg_rsp) \
184 M(TIM_CONFIG_RING, 0x802, tim_config_ring, tim_config_req, msg_rsp)\
185 M(TIM_ENABLE_RING, 0x803, tim_enable_ring, tim_ring_req, \
186 tim_enable_rsp) \
187 M(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \
188 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
189 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
190 cpt_lf_alloc_rsp_msg) \
191 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
192 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
193 cpt_rd_wr_reg_msg) \
194 M(CPT_SET_CRYPTO_GRP, 0xA03, cpt_set_crypto_grp, \
195 cpt_set_crypto_grp_req_msg, \
196 msg_rsp) \
197 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
198 cpt_inline_ipsec_cfg_msg, msg_rsp) \
199 M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \
200 cpt_rx_inline_lf_cfg_msg, msg_rsp) \
201 M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg) \
202 /* REE mbox IDs (range 0xE00 - 0xFFF) */ \
203 M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, \
204 msg_rsp) \
205 M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg, \
206 ree_rd_wr_reg_msg) \
207 M(REE_RULE_DB_PROG, 0xE03, ree_rule_db_prog, \
208 ree_rule_db_prog_req_msg, \
209 msg_rsp) \
210 M(REE_RULE_DB_LEN_GET, 0xE04, ree_rule_db_len_get, ree_req_msg, \
211 ree_rule_db_len_rsp_msg) \
212 M(REE_RULE_DB_GET, 0xE05, ree_rule_db_get, \
213 ree_rule_db_get_req_msg, \
214 ree_rule_db_get_rsp_msg) \
215 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
216 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, \
217 npc_mcam_alloc_entry_req, \
218 npc_mcam_alloc_entry_rsp) \
219 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
220 npc_mcam_free_entry_req, msg_rsp) \
221 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
222 npc_mcam_write_entry_req, msg_rsp) \
223 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
224 npc_mcam_ena_dis_entry_req, msg_rsp) \
225 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
226 npc_mcam_ena_dis_entry_req, msg_rsp) \
227 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, \
228 npc_mcam_shift_entry_req, \
229 npc_mcam_shift_entry_rsp) \
230 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
231 npc_mcam_alloc_counter_req, \
232 npc_mcam_alloc_counter_rsp) \
233 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
234 npc_mcam_oper_counter_req, \
235 msg_rsp) \
236 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
237 npc_mcam_unmap_counter_req, \
238 msg_rsp) \
239 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
240 npc_mcam_oper_counter_req, \
241 msg_rsp) \
242 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
243 npc_mcam_oper_counter_req, \
244 npc_mcam_oper_counter_rsp) \
245 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry,\
246 npc_mcam_alloc_and_write_entry_req, \
247 npc_mcam_alloc_and_write_entry_rsp) \
248 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, msg_req, \
249 npc_get_kex_cfg_rsp) \
250 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
251 npc_install_flow_req, \
252 npc_install_flow_rsp) \
253 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
254 npc_delete_flow_req, msg_rsp) \
255 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
256 npc_mcam_read_entry_req, \
257 npc_mcam_read_entry_rsp) \
258 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
259 npc_set_pkind, \
260 msg_rsp) \
261 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, msg_req, \
262 npc_mcam_read_base_rule_rsp) \
263 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
264 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, nix_lf_alloc_req, \
265 nix_lf_alloc_rsp) \
266 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
267 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, \
268 nix_aq_enq_rsp) \
269 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, hwctx_disable_req, \
270 msg_rsp) \
271 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, nix_txsch_alloc_req, \
272 nix_txsch_alloc_rsp) \
273 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, \
274 msg_rsp) \
275 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
276 nix_txschq_config) \
277 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
278 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
279 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
280 nix_rss_flowkey_cfg, \
281 nix_rss_flowkey_cfg_rsp) \
282 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, \
283 msg_rsp) \
284 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
285 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
286 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
287 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
288 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
289 nix_mark_format_cfg, \
290 nix_mark_format_cfg_rsp) \
291 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
292 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, nix_lso_format_cfg, \
293 nix_lso_format_cfg_rsp) \
294 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, \
295 msg_rsp) \
296 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, \
297 msg_rsp) \
298 M(NIX_SET_VLAN_TPID, 0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid, \
299 msg_rsp) \
300 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
301 nix_bp_cfg_rsp) \
302 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp)\
303 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, \
304 nix_get_mac_addr_rsp) \
305 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
306 nix_inline_ipsec_cfg, msg_rsp) \
307 M(NIX_INLINE_IPSEC_LF_CFG, \
308 0x801a, nix_inline_ipsec_lf_cfg, \
309 nix_inline_ipsec_lf_cfg, msg_rsp)
310
311 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
312 #define MBOX_UP_CGX_MESSAGES \
313 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, \
314 msg_rsp) \
315 M(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, \
316 msg_rsp)
317
318 enum {
319 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
320 MBOX_MESSAGES
321 MBOX_UP_CGX_MESSAGES
322 #undef M
323 };
324
325 /* Mailbox message formats */
326
327 #define RVU_DEFAULT_PF_FUNC 0xFFFF
328
329 /* Generic request msg used for those mbox messages which
330 * don't send any data in the request.
331 */
332 struct msg_req {
333 struct mbox_msghdr hdr;
334 };
335
336 /* Generic response msg used a ack or response for those mbox
337 * messages which doesn't have a specific rsp msg format.
338 */
339 struct msg_rsp {
340 struct mbox_msghdr hdr;
341 };
342
343 /* RVU mailbox error codes
344 * Range 256 - 300.
345 */
346 enum rvu_af_status {
347 RVU_INVALID_VF_ID = -256,
348 };
349
350 struct ready_msg_rsp {
351 struct mbox_msghdr hdr;
352 uint16_t __otx2_io sclk_feq; /* SCLK frequency */
353 uint16_t __otx2_io rclk_freq; /* RCLK frequency */
354 };
355
356 /* Struct to set pkind */
357 struct npc_set_pkind {
358 struct mbox_msghdr hdr;
359 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
360 #define OTX2_PRIV_FLAGS_EDSA BIT_ULL(1)
361 #define OTX2_PRIV_FLAGS_HIGIG BIT_ULL(2)
362 #define OTX2_PRIV_FLAGS_LEN_90B BIT_ULL(3)
363 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
364 uint64_t __otx2_io mode;
365 #define PKIND_TX BIT_ULL(0)
366 #define PKIND_RX BIT_ULL(1)
367 uint8_t __otx2_io dir;
368 uint8_t __otx2_io pkind; /* valid only in case custom flag */
369 };
370
371 /* Structure for requesting resource provisioning.
372 * 'modify' flag to be used when either requesting more
373 * or to detach partial of a certain resource type.
374 * Rest of the fields specify how many of what type to
375 * be attached.
376 * To request LFs from two blocks of same type this mailbox
377 * can be sent twice as below:
378 * struct rsrc_attach *attach;
379 * .. Allocate memory for message ..
380 * attach->cptlfs = 3; <3 LFs from CPT0>
381 * .. Send message ..
382 * .. Allocate memory for message ..
383 * attach->modify = 1;
384 * attach->cpt_blkaddr = BLKADDR_CPT1;
385 * attach->cptlfs = 2; <2 LFs from CPT1>
386 * .. Send message ..
387 */
388 struct rsrc_attach_req {
389 struct mbox_msghdr hdr;
390 uint8_t __otx2_io modify:1;
391 uint8_t __otx2_io npalf:1;
392 uint8_t __otx2_io nixlf:1;
393 uint16_t __otx2_io sso;
394 uint16_t __otx2_io ssow;
395 uint16_t __otx2_io timlfs;
396 uint16_t __otx2_io cptlfs;
397 uint16_t __otx2_io reelfs;
398 /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
399 int __otx2_io cpt_blkaddr;
400 /* BLKADDR_REE0/BLKADDR_REE1 or 0 for BLKADDR_REE0 */
401 int __otx2_io ree_blkaddr;
402 };
403
404 /* Structure for relinquishing resources.
405 * 'partial' flag to be used when relinquishing all resources
406 * but only of a certain type. If not set, all resources of all
407 * types provisioned to the RVU function will be detached.
408 */
409 struct rsrc_detach_req {
410 struct mbox_msghdr hdr;
411 uint8_t __otx2_io partial:1;
412 uint8_t __otx2_io npalf:1;
413 uint8_t __otx2_io nixlf:1;
414 uint8_t __otx2_io sso:1;
415 uint8_t __otx2_io ssow:1;
416 uint8_t __otx2_io timlfs:1;
417 uint8_t __otx2_io cptlfs:1;
418 uint8_t __otx2_io reelfs:1;
419 };
420
421 /* NIX Transmit schedulers */
422 #define NIX_TXSCH_LVL_SMQ 0x0
423 #define NIX_TXSCH_LVL_MDQ 0x0
424 #define NIX_TXSCH_LVL_TL4 0x1
425 #define NIX_TXSCH_LVL_TL3 0x2
426 #define NIX_TXSCH_LVL_TL2 0x3
427 #define NIX_TXSCH_LVL_TL1 0x4
428 #define NIX_TXSCH_LVL_CNT 0x5
429
430 /*
431 * Number of resources available to the caller.
432 * In reply to MBOX_MSG_FREE_RSRC_CNT.
433 */
434 struct free_rsrcs_rsp {
435 struct mbox_msghdr hdr;
436 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT];
437 uint16_t __otx2_io sso;
438 uint16_t __otx2_io tim;
439 uint16_t __otx2_io ssow;
440 uint16_t __otx2_io cpt;
441 uint8_t __otx2_io npa;
442 uint8_t __otx2_io nix;
443 uint16_t __otx2_io schq_nix1[NIX_TXSCH_LVL_CNT];
444 uint8_t __otx2_io nix1;
445 uint8_t __otx2_io cpt1;
446 uint8_t __otx2_io ree0;
447 uint8_t __otx2_io ree1;
448 };
449
450 #define MSIX_VECTOR_INVALID 0xFFFF
451 #define MAX_RVU_BLKLF_CNT 256
452
453 struct msix_offset_rsp {
454 struct mbox_msghdr hdr;
455 uint16_t __otx2_io npa_msixoff;
456 uint16_t __otx2_io nix_msixoff;
457 uint16_t __otx2_io sso;
458 uint16_t __otx2_io ssow;
459 uint16_t __otx2_io timlfs;
460 uint16_t __otx2_io cptlfs;
461 uint16_t __otx2_io sso_msixoff[MAX_RVU_BLKLF_CNT];
462 uint16_t __otx2_io ssow_msixoff[MAX_RVU_BLKLF_CNT];
463 uint16_t __otx2_io timlf_msixoff[MAX_RVU_BLKLF_CNT];
464 uint16_t __otx2_io cptlf_msixoff[MAX_RVU_BLKLF_CNT];
465 uint16_t __otx2_io cpt1_lfs;
466 uint16_t __otx2_io ree0_lfs;
467 uint16_t __otx2_io ree1_lfs;
468 uint16_t __otx2_io cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
469 uint16_t __otx2_io ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
470 uint16_t __otx2_io ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
471
472 };
473
474 /* CGX mbox message formats */
475
476 struct cgx_stats_rsp {
477 struct mbox_msghdr hdr;
478 #define CGX_RX_STATS_COUNT 13
479 #define CGX_TX_STATS_COUNT 18
480 uint64_t __otx2_io rx_stats[CGX_RX_STATS_COUNT];
481 uint64_t __otx2_io tx_stats[CGX_TX_STATS_COUNT];
482 };
483
484 struct cgx_fec_stats_rsp {
485 struct mbox_msghdr hdr;
486 uint64_t __otx2_io fec_corr_blks;
487 uint64_t __otx2_io fec_uncorr_blks;
488 };
489 /* Structure for requesting the operation for
490 * setting/getting mac address in the CGX interface
491 */
492 struct cgx_mac_addr_set_or_get {
493 struct mbox_msghdr hdr;
494 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
495 };
496
497 /* Structure for requesting the operation to
498 * add DMAC filter entry into CGX interface
499 */
500 struct cgx_mac_addr_add_req {
501 struct mbox_msghdr hdr;
502 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
503 };
504
505 /* Structure for response against the operation to
506 * add DMAC filter entry into CGX interface
507 */
508 struct cgx_mac_addr_add_rsp {
509 struct mbox_msghdr hdr;
510 uint8_t __otx2_io index;
511 };
512
513 /* Structure for requesting the operation to
514 * delete DMAC filter entry from CGX interface
515 */
516 struct cgx_mac_addr_del_req {
517 struct mbox_msghdr hdr;
518 uint8_t __otx2_io index;
519 };
520
521 /* Structure for response against the operation to
522 * get maximum supported DMAC filter entries
523 */
524 struct cgx_max_dmac_entries_get_rsp {
525 struct mbox_msghdr hdr;
526 uint8_t __otx2_io max_dmac_filters;
527 };
528
529 struct cgx_link_user_info {
530 uint64_t __otx2_io link_up:1;
531 uint64_t __otx2_io full_duplex:1;
532 uint64_t __otx2_io lmac_type_id:4;
533 uint64_t __otx2_io speed:20; /* speed in Mbps */
534 uint64_t __otx2_io an:1; /* AN supported or not */
535 uint64_t __otx2_io fec:2; /* FEC type if enabled else 0 */
536 uint64_t __otx2_io port:8;
537 #define LMACTYPE_STR_LEN 16
538 char lmac_type[LMACTYPE_STR_LEN];
539 };
540
541 struct cgx_link_info_msg {
542 struct mbox_msghdr hdr;
543 struct cgx_link_user_info link_info;
544 };
545
546 struct cgx_ptp_rx_info_msg {
547 struct mbox_msghdr hdr;
548 uint8_t __otx2_io ptp_en;
549 };
550
551 struct cgx_pause_frm_cfg {
552 struct mbox_msghdr hdr;
553 uint8_t __otx2_io set;
554 /* set = 1 if the request is to config pause frames */
555 /* set = 0 if the request is to fetch pause frames config */
556 uint8_t __otx2_io rx_pause;
557 uint8_t __otx2_io tx_pause;
558 };
559
560 struct sfp_eeprom_s {
561 #define SFP_EEPROM_SIZE 256
562 uint16_t __otx2_io sff_id;
563 uint8_t __otx2_io buf[SFP_EEPROM_SIZE];
564 uint64_t __otx2_io reserved;
565 };
566
567 enum fec_type {
568 OTX2_FEC_NONE,
569 OTX2_FEC_BASER,
570 OTX2_FEC_RS,
571 };
572
573 struct phy_s {
574 uint64_t __otx2_io can_change_mod_type : 1;
575 uint64_t __otx2_io mod_type : 1;
576 };
577
578 struct cgx_lmac_fwdata_s {
579 uint16_t __otx2_io rw_valid;
580 uint64_t __otx2_io supported_fec;
581 uint64_t __otx2_io supported_an;
582 uint64_t __otx2_io supported_link_modes;
583 /* Only applicable if AN is supported */
584 uint64_t __otx2_io advertised_fec;
585 uint64_t __otx2_io advertised_link_modes;
586 /* Only applicable if SFP/QSFP slot is present */
587 struct sfp_eeprom_s sfp_eeprom;
588 struct phy_s phy;
589 #define LMAC_FWDATA_RESERVED_MEM 1023
590 uint64_t __otx2_io reserved[LMAC_FWDATA_RESERVED_MEM];
591 };
592
593 struct cgx_fw_data {
594 struct mbox_msghdr hdr;
595 struct cgx_lmac_fwdata_s fwdata;
596 };
597
598 struct fec_mode {
599 struct mbox_msghdr hdr;
600 int __otx2_io fec;
601 };
602
603 struct cgx_set_link_state_msg {
604 struct mbox_msghdr hdr;
605 uint8_t __otx2_io enable;
606 };
607
608 struct cgx_phy_mod_type {
609 struct mbox_msghdr hdr;
610 int __otx2_io mod;
611 };
612
613 struct cgx_set_link_mode_args {
614 uint32_t __otx2_io speed;
615 uint8_t __otx2_io duplex;
616 uint8_t __otx2_io an;
617 uint8_t __otx2_io ports;
618 uint64_t __otx2_io mode;
619 };
620
621 struct cgx_set_link_mode_req {
622 struct mbox_msghdr hdr;
623 struct cgx_set_link_mode_args args;
624 };
625
626 struct cgx_set_link_mode_rsp {
627 struct mbox_msghdr hdr;
628 int __otx2_io status;
629 };
630 /* NPA mbox message formats */
631
632 /* NPA mailbox error codes
633 * Range 301 - 400.
634 */
635 enum npa_af_status {
636 NPA_AF_ERR_PARAM = -301,
637 NPA_AF_ERR_AQ_FULL = -302,
638 NPA_AF_ERR_AQ_ENQUEUE = -303,
639 NPA_AF_ERR_AF_LF_INVALID = -304,
640 NPA_AF_ERR_AF_LF_ALLOC = -305,
641 NPA_AF_ERR_LF_RESET = -306,
642 };
643
644 #define NPA_AURA_SZ_0 0
645 #define NPA_AURA_SZ_128 1
646 #define NPA_AURA_SZ_256 2
647 #define NPA_AURA_SZ_512 3
648 #define NPA_AURA_SZ_1K 4
649 #define NPA_AURA_SZ_2K 5
650 #define NPA_AURA_SZ_4K 6
651 #define NPA_AURA_SZ_8K 7
652 #define NPA_AURA_SZ_16K 8
653 #define NPA_AURA_SZ_32K 9
654 #define NPA_AURA_SZ_64K 10
655 #define NPA_AURA_SZ_128K 11
656 #define NPA_AURA_SZ_256K 12
657 #define NPA_AURA_SZ_512K 13
658 #define NPA_AURA_SZ_1M 14
659 #define NPA_AURA_SZ_MAX 15
660
661 /* For NPA LF context alloc and init */
662 struct npa_lf_alloc_req {
663 struct mbox_msghdr hdr;
664 int __otx2_io node;
665 int __otx2_io aura_sz; /* No of auras. See NPA_AURA_SZ_* */
666 uint32_t __otx2_io nr_pools; /* No of pools */
667 uint64_t __otx2_io way_mask;
668 };
669
670 struct npa_lf_alloc_rsp {
671 struct mbox_msghdr hdr;
672 uint32_t __otx2_io stack_pg_ptrs; /* No of ptrs per stack page */
673 uint32_t __otx2_io stack_pg_bytes; /* Size of stack page */
674 uint16_t __otx2_io qints; /* NPA_AF_CONST::QINTS */
675 };
676
677 /* NPA AQ enqueue msg */
678 struct npa_aq_enq_req {
679 struct mbox_msghdr hdr;
680 uint32_t __otx2_io aura_id;
681 uint8_t __otx2_io ctype;
682 uint8_t __otx2_io op;
683 union {
684 /* Valid when op == WRITE/INIT and ctype == AURA.
685 * LF fills the pool_id in aura.pool_addr. AF will translate
686 * the pool_id to pool context pointer.
687 */
688 __otx2_io struct npa_aura_s aura;
689 /* Valid when op == WRITE/INIT and ctype == POOL */
690 __otx2_io struct npa_pool_s pool;
691 };
692 /* Mask data when op == WRITE (1=write, 0=don't write) */
693 union {
694 /* Valid when op == WRITE and ctype == AURA */
695 __otx2_io struct npa_aura_s aura_mask;
696 /* Valid when op == WRITE and ctype == POOL */
697 __otx2_io struct npa_pool_s pool_mask;
698 };
699 };
700
701 struct npa_aq_enq_rsp {
702 struct mbox_msghdr hdr;
703 union {
704 /* Valid when op == READ and ctype == AURA */
705 __otx2_io struct npa_aura_s aura;
706 /* Valid when op == READ and ctype == POOL */
707 __otx2_io struct npa_pool_s pool;
708 };
709 };
710
711 /* Disable all contexts of type 'ctype' */
712 struct hwctx_disable_req {
713 struct mbox_msghdr hdr;
714 uint8_t __otx2_io ctype;
715 };
716
717 /* NIX mbox message formats */
718
719 /* NIX mailbox error codes
720 * Range 401 - 500.
721 */
722 enum nix_af_status {
723 NIX_AF_ERR_PARAM = -401,
724 NIX_AF_ERR_AQ_FULL = -402,
725 NIX_AF_ERR_AQ_ENQUEUE = -403,
726 NIX_AF_ERR_AF_LF_INVALID = -404,
727 NIX_AF_ERR_AF_LF_ALLOC = -405,
728 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
729 NIX_AF_ERR_TLX_INVALID = -407,
730 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
731 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
732 NIX_AF_ERR_FRS_INVALID = -410,
733 NIX_AF_ERR_RX_LINK_INVALID = -411,
734 NIX_AF_INVAL_TXSCHQ_CFG = -412,
735 NIX_AF_SMQ_FLUSH_FAILED = -413,
736 NIX_AF_ERR_LF_RESET = -414,
737 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
738 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
739 NIX_AF_ERR_MARK_CFG_FAIL = -417,
740 NIX_AF_ERR_LSO_CFG_FAIL = -418,
741 NIX_AF_INVAL_NPA_PF_FUNC = -419,
742 NIX_AF_INVAL_SSO_PF_FUNC = -420,
743 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
744 NIX_AF_ERR_RX_VTAG_INUSE = -422,
745 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
746 };
747
748 /* For NIX LF context alloc and init */
749 struct nix_lf_alloc_req {
750 struct mbox_msghdr hdr;
751 int __otx2_io node;
752 uint32_t __otx2_io rq_cnt; /* No of receive queues */
753 uint32_t __otx2_io sq_cnt; /* No of send queues */
754 uint32_t __otx2_io cq_cnt; /* No of completion queues */
755 uint8_t __otx2_io xqe_sz;
756 uint16_t __otx2_io rss_sz;
757 uint8_t __otx2_io rss_grps;
758 uint16_t __otx2_io npa_func;
759 /* RVU_DEFAULT_PF_FUNC == default pf_func associated with lf */
760 uint16_t __otx2_io sso_func;
761 uint64_t __otx2_io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
762 uint64_t __otx2_io way_mask;
763 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
764 uint64_t flags;
765 };
766
767 struct nix_lf_alloc_rsp {
768 struct mbox_msghdr hdr;
769 uint16_t __otx2_io sqb_size;
770 uint16_t __otx2_io rx_chan_base;
771 uint16_t __otx2_io tx_chan_base;
772 uint8_t __otx2_io rx_chan_cnt; /* Total number of RX channels */
773 uint8_t __otx2_io tx_chan_cnt; /* Total number of TX channels */
774 uint8_t __otx2_io lso_tsov4_idx;
775 uint8_t __otx2_io lso_tsov6_idx;
776 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
777 uint8_t __otx2_io lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
778 uint8_t __otx2_io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
779 uint16_t __otx2_io cints; /* NIX_AF_CONST2::CINTS */
780 uint16_t __otx2_io qints; /* NIX_AF_CONST2::QINTS */
781 uint8_t __otx2_io hw_rx_tstamp_en; /*set if rx timestamping enabled */
782 uint8_t __otx2_io cgx_links; /* No. of CGX links present in HW */
783 uint8_t __otx2_io lbk_links; /* No. of LBK links present in HW */
784 uint8_t __otx2_io sdp_links; /* No. of SDP links present in HW */
785 uint8_t __otx2_io tx_link; /* Transmit channel link number */
786 };
787
788 struct nix_lf_free_req {
789 struct mbox_msghdr hdr;
790 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
791 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
792 uint64_t __otx2_io flags;
793 };
794
795 /* NIX AQ enqueue msg */
796 struct nix_aq_enq_req {
797 struct mbox_msghdr hdr;
798 uint32_t __otx2_io qidx;
799 uint8_t __otx2_io ctype;
800 uint8_t __otx2_io op;
801 union {
802 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
803 __otx2_io struct nix_rq_ctx_s rq;
804 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
805 __otx2_io struct nix_sq_ctx_s sq;
806 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
807 __otx2_io struct nix_cq_ctx_s cq;
808 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
809 __otx2_io struct nix_rsse_s rss;
810 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
811 __otx2_io struct nix_rx_mce_s mce;
812 };
813 /* Mask data when op == WRITE (1=write, 0=don't write) */
814 union {
815 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
816 __otx2_io struct nix_rq_ctx_s rq_mask;
817 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
818 __otx2_io struct nix_sq_ctx_s sq_mask;
819 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
820 __otx2_io struct nix_cq_ctx_s cq_mask;
821 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
822 __otx2_io struct nix_rsse_s rss_mask;
823 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
824 __otx2_io struct nix_rx_mce_s mce_mask;
825 };
826 };
827
828 struct nix_aq_enq_rsp {
829 struct mbox_msghdr hdr;
830 union {
831 __otx2_io struct nix_rq_ctx_s rq;
832 __otx2_io struct nix_sq_ctx_s sq;
833 __otx2_io struct nix_cq_ctx_s cq;
834 __otx2_io struct nix_rsse_s rss;
835 __otx2_io struct nix_rx_mce_s mce;
836 };
837 };
838
839 /* Tx scheduler/shaper mailbox messages */
840
841 #define MAX_TXSCHQ_PER_FUNC 128
842
843 struct nix_txsch_alloc_req {
844 struct mbox_msghdr hdr;
845 /* Scheduler queue count request at each level */
846 uint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
847 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
848 };
849
850 struct nix_txsch_alloc_rsp {
851 struct mbox_msghdr hdr;
852 /* Scheduler queue count allocated at each level */
853 uint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
854 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
855 /* Scheduler queue list allocated at each level */
856 uint16_t __otx2_io
857 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
858 uint16_t __otx2_io schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
859 /* Traffic aggregation scheduler level */
860 uint8_t __otx2_io aggr_level;
861 /* Aggregation lvl's RR_PRIO config */
862 uint8_t __otx2_io aggr_lvl_rr_prio;
863 /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
864 uint8_t __otx2_io link_cfg_lvl;
865 };
866
867 struct nix_txsch_free_req {
868 struct mbox_msghdr hdr;
869 #define TXSCHQ_FREE_ALL BIT_ULL(0)
870 uint16_t __otx2_io flags;
871 /* Scheduler queue level to be freed */
872 uint16_t __otx2_io schq_lvl;
873 /* List of scheduler queues to be freed */
874 uint16_t __otx2_io schq;
875 };
876
877 struct nix_txschq_config {
878 struct mbox_msghdr hdr;
879 uint8_t __otx2_io lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
880 uint8_t __otx2_io read;
881 #define TXSCHQ_IDX_SHIFT 16
882 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
883 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
884 uint8_t __otx2_io num_regs;
885 #define MAX_REGS_PER_MBOX_MSG 20
886 uint64_t __otx2_io reg[MAX_REGS_PER_MBOX_MSG];
887 uint64_t __otx2_io regval[MAX_REGS_PER_MBOX_MSG];
888 /* All 0's => overwrite with new value */
889 uint64_t __otx2_io regval_mask[MAX_REGS_PER_MBOX_MSG];
890 };
891
892 struct nix_vtag_config {
893 struct mbox_msghdr hdr;
894 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
895 uint8_t __otx2_io vtag_size;
896 /* cfg_type is '0' for tx vlan cfg
897 * cfg_type is '1' for rx vlan cfg
898 */
899 uint8_t __otx2_io cfg_type;
900 union {
901 /* Valid when cfg_type is '0' */
902 struct {
903 uint64_t __otx2_io vtag0;
904 uint64_t __otx2_io vtag1;
905
906 /* cfg_vtag0 & cfg_vtag1 fields are valid
907 * when free_vtag0 & free_vtag1 are '0's.
908 */
909 /* cfg_vtag0 = 1 to configure vtag0 */
910 uint8_t __otx2_io cfg_vtag0 :1;
911 /* cfg_vtag1 = 1 to configure vtag1 */
912 uint8_t __otx2_io cfg_vtag1 :1;
913
914 /* vtag0_idx & vtag1_idx are only valid when
915 * both cfg_vtag0 & cfg_vtag1 are '0's,
916 * these fields are used along with free_vtag0
917 * & free_vtag1 to free the nix lf's tx_vlan
918 * configuration.
919 *
920 * Denotes the indices of tx_vtag def registers
921 * that needs to be cleared and freed.
922 */
923 int __otx2_io vtag0_idx;
924 int __otx2_io vtag1_idx;
925
926 /* Free_vtag0 & free_vtag1 fields are valid
927 * when cfg_vtag0 & cfg_vtag1 are '0's.
928 */
929 /* Free_vtag0 = 1 clears vtag0 configuration
930 * vtag0_idx denotes the index to be cleared.
931 */
932 uint8_t __otx2_io free_vtag0 :1;
933 /* Free_vtag1 = 1 clears vtag1 configuration
934 * vtag1_idx denotes the index to be cleared.
935 */
936 uint8_t __otx2_io free_vtag1 :1;
937 } tx;
938
939 /* Valid when cfg_type is '1' */
940 struct {
941 /* Rx vtag type index, valid values are in 0..7 range */
942 uint8_t __otx2_io vtag_type;
943 /* Rx vtag strip */
944 uint8_t __otx2_io strip_vtag :1;
945 /* Rx vtag capture */
946 uint8_t __otx2_io capture_vtag :1;
947 } rx;
948 };
949 };
950
951 struct nix_vtag_config_rsp {
952 struct mbox_msghdr hdr;
953 /* Indices of tx_vtag def registers used to configure
954 * tx vtag0 & vtag1 headers, these indices are valid
955 * when nix_vtag_config mbox requested for vtag0 and/
956 * or vtag1 configuration.
957 */
958 int __otx2_io vtag0_idx;
959 int __otx2_io vtag1_idx;
960 };
961
962 struct nix_rss_flowkey_cfg {
963 struct mbox_msghdr hdr;
964 int __otx2_io mcam_index; /* MCAM entry index to modify */
965 uint32_t __otx2_io flowkey_cfg; /* Flowkey types selected */
966 #define FLOW_KEY_TYPE_PORT BIT(0)
967 #define FLOW_KEY_TYPE_IPV4 BIT(1)
968 #define FLOW_KEY_TYPE_IPV6 BIT(2)
969 #define FLOW_KEY_TYPE_TCP BIT(3)
970 #define FLOW_KEY_TYPE_UDP BIT(4)
971 #define FLOW_KEY_TYPE_SCTP BIT(5)
972 #define FLOW_KEY_TYPE_NVGRE BIT(6)
973 #define FLOW_KEY_TYPE_VXLAN BIT(7)
974 #define FLOW_KEY_TYPE_GENEVE BIT(8)
975 #define FLOW_KEY_TYPE_ETH_DMAC BIT(9)
976 #define FLOW_KEY_TYPE_IPV6_EXT BIT(10)
977 #define FLOW_KEY_TYPE_GTPU BIT(11)
978 #define FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
979 #define FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
980 #define FLOW_KEY_TYPE_INNR_TCP BIT(14)
981 #define FLOW_KEY_TYPE_INNR_UDP BIT(15)
982 #define FLOW_KEY_TYPE_INNR_SCTP BIT(16)
983 #define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
984 #define FLOW_KEY_TYPE_CH_LEN_90B BIT(18)
985 #define FLOW_KEY_TYPE_CUSTOM0 BIT(19)
986 #define FLOW_KEY_TYPE_VLAN BIT(20)
987 #define FLOW_KEY_TYPE_L4_DST BIT(28)
988 #define FLOW_KEY_TYPE_L4_SRC BIT(29)
989 #define FLOW_KEY_TYPE_L3_DST BIT(30)
990 #define FLOW_KEY_TYPE_L3_SRC BIT(31)
991 uint8_t __otx2_io group; /* RSS context or group */
992 };
993
994 struct nix_rss_flowkey_cfg_rsp {
995 struct mbox_msghdr hdr;
996 uint8_t __otx2_io alg_idx; /* Selected algo index */
997 };
998
999 struct nix_set_mac_addr {
1000 struct mbox_msghdr hdr;
1001 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
1002 };
1003
1004 struct nix_get_mac_addr_rsp {
1005 struct mbox_msghdr hdr;
1006 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
1007 };
1008
1009 struct nix_mark_format_cfg {
1010 struct mbox_msghdr hdr;
1011 uint8_t __otx2_io offset;
1012 uint8_t __otx2_io y_mask;
1013 uint8_t __otx2_io y_val;
1014 uint8_t __otx2_io r_mask;
1015 uint8_t __otx2_io r_val;
1016 };
1017
1018 struct nix_mark_format_cfg_rsp {
1019 struct mbox_msghdr hdr;
1020 uint8_t __otx2_io mark_format_idx;
1021 };
1022
1023 struct nix_lso_format_cfg {
1024 struct mbox_msghdr hdr;
1025 uint64_t __otx2_io field_mask;
1026 uint64_t __otx2_io fields[NIX_LSO_FIELD_MAX];
1027 };
1028
1029 struct nix_lso_format_cfg_rsp {
1030 struct mbox_msghdr hdr;
1031 uint8_t __otx2_io lso_format_idx;
1032 };
1033
1034 struct nix_rx_mode {
1035 struct mbox_msghdr hdr;
1036 #define NIX_RX_MODE_UCAST BIT(0)
1037 #define NIX_RX_MODE_PROMISC BIT(1)
1038 #define NIX_RX_MODE_ALLMULTI BIT(2)
1039 uint16_t __otx2_io mode;
1040 };
1041
1042 struct nix_rx_cfg {
1043 struct mbox_msghdr hdr;
1044 #define NIX_RX_OL3_VERIFY BIT(0)
1045 #define NIX_RX_OL4_VERIFY BIT(1)
1046 uint8_t __otx2_io len_verify; /* Outer L3/L4 len check */
1047 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1048 uint8_t __otx2_io csum_verify; /* Outer L4 checksum verification */
1049 };
1050
1051 struct nix_frs_cfg {
1052 struct mbox_msghdr hdr;
1053 uint8_t __otx2_io update_smq; /* Update SMQ's min/max lens */
1054 uint8_t __otx2_io update_minlen; /* Set minlen also */
1055 uint8_t __otx2_io sdp_link; /* Set SDP RX link */
1056 uint16_t __otx2_io maxlen;
1057 uint16_t __otx2_io minlen;
1058 };
1059
1060 struct nix_set_vlan_tpid {
1061 struct mbox_msghdr hdr;
1062 #define NIX_VLAN_TYPE_INNER 0
1063 #define NIX_VLAN_TYPE_OUTER 1
1064 uint8_t __otx2_io vlan_type;
1065 uint16_t __otx2_io tpid;
1066 };
1067
1068 struct nix_bp_cfg_req {
1069 struct mbox_msghdr hdr;
1070 uint16_t __otx2_io chan_base; /* Starting channel number */
1071 uint8_t __otx2_io chan_cnt; /* Number of channels */
1072 uint8_t __otx2_io bpid_per_chan;
1073 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1074 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1075 };
1076
1077 /* PF can be mapped to either CGX or LBK interface,
1078 * so maximum 64 channels are possible.
1079 */
1080 #define NIX_MAX_CHAN 64
1081 struct nix_bp_cfg_rsp {
1082 struct mbox_msghdr hdr;
1083 /* Channel and bpid mapping */
1084 uint16_t __otx2_io chan_bpid[NIX_MAX_CHAN];
1085 /* Number of channel for which bpids are assigned */
1086 uint8_t __otx2_io chan_cnt;
1087 };
1088
1089 /* Global NIX inline IPSec configuration */
1090 struct nix_inline_ipsec_cfg {
1091 struct mbox_msghdr hdr;
1092 uint32_t __otx2_io cpt_credit;
1093 struct {
1094 uint8_t __otx2_io egrp;
1095 uint8_t __otx2_io opcode;
1096 } gen_cfg;
1097 struct {
1098 uint16_t __otx2_io cpt_pf_func;
1099 uint8_t __otx2_io cpt_slot;
1100 } inst_qsel;
1101 uint8_t __otx2_io enable;
1102 };
1103
1104 /* Per NIX LF inline IPSec configuration */
1105 struct nix_inline_ipsec_lf_cfg {
1106 struct mbox_msghdr hdr;
1107 uint64_t __otx2_io sa_base_addr;
1108 struct {
1109 uint32_t __otx2_io tag_const;
1110 uint16_t __otx2_io lenm1_max;
1111 uint8_t __otx2_io sa_pow2_size;
1112 uint8_t __otx2_io tt;
1113 } ipsec_cfg0;
1114 struct {
1115 uint32_t __otx2_io sa_idx_max;
1116 uint8_t __otx2_io sa_idx_w;
1117 } ipsec_cfg1;
1118 uint8_t __otx2_io enable;
1119 };
1120
1121 /* SSO mailbox error codes
1122 * Range 501 - 600.
1123 */
1124 enum sso_af_status {
1125 SSO_AF_ERR_PARAM = -501,
1126 SSO_AF_ERR_LF_INVALID = -502,
1127 SSO_AF_ERR_AF_LF_ALLOC = -503,
1128 SSO_AF_ERR_GRP_EBUSY = -504,
1129 SSO_AF_INVAL_NPA_PF_FUNC = -505,
1130 };
1131
1132 struct sso_lf_alloc_req {
1133 struct mbox_msghdr hdr;
1134 int __otx2_io node;
1135 uint16_t __otx2_io hwgrps;
1136 };
1137
1138 struct sso_lf_alloc_rsp {
1139 struct mbox_msghdr hdr;
1140 uint32_t __otx2_io xaq_buf_size;
1141 uint32_t __otx2_io xaq_wq_entries;
1142 uint32_t __otx2_io in_unit_entries;
1143 uint16_t __otx2_io hwgrps;
1144 };
1145
1146 struct sso_lf_free_req {
1147 struct mbox_msghdr hdr;
1148 int __otx2_io node;
1149 uint16_t __otx2_io hwgrps;
1150 };
1151
1152 /* SSOW mailbox error codes
1153 * Range 601 - 700.
1154 */
1155 enum ssow_af_status {
1156 SSOW_AF_ERR_PARAM = -601,
1157 SSOW_AF_ERR_LF_INVALID = -602,
1158 SSOW_AF_ERR_AF_LF_ALLOC = -603,
1159 };
1160
1161 struct ssow_lf_alloc_req {
1162 struct mbox_msghdr hdr;
1163 int __otx2_io node;
1164 uint16_t __otx2_io hws;
1165 };
1166
1167 struct ssow_lf_free_req {
1168 struct mbox_msghdr hdr;
1169 int __otx2_io node;
1170 uint16_t __otx2_io hws;
1171 };
1172
1173 struct sso_hw_setconfig {
1174 struct mbox_msghdr hdr;
1175 uint32_t __otx2_io npa_aura_id;
1176 uint16_t __otx2_io npa_pf_func;
1177 uint16_t __otx2_io hwgrps;
1178 };
1179
1180 struct sso_info_req {
1181 struct mbox_msghdr hdr;
1182 union {
1183 uint16_t __otx2_io grp;
1184 uint16_t __otx2_io hws;
1185 };
1186 };
1187
1188 struct sso_grp_priority {
1189 struct mbox_msghdr hdr;
1190 uint16_t __otx2_io grp;
1191 uint8_t __otx2_io priority;
1192 uint8_t __otx2_io affinity;
1193 uint8_t __otx2_io weight;
1194 };
1195
1196 struct sso_grp_qos_cfg {
1197 struct mbox_msghdr hdr;
1198 uint16_t __otx2_io grp;
1199 uint32_t __otx2_io xaq_limit;
1200 uint16_t __otx2_io taq_thr;
1201 uint16_t __otx2_io iaq_thr;
1202 };
1203
1204 struct sso_grp_stats {
1205 struct mbox_msghdr hdr;
1206 uint16_t __otx2_io grp;
1207 uint64_t __otx2_io ws_pc;
1208 uint64_t __otx2_io ext_pc;
1209 uint64_t __otx2_io wa_pc;
1210 uint64_t __otx2_io ts_pc;
1211 uint64_t __otx2_io ds_pc;
1212 uint64_t __otx2_io dq_pc;
1213 uint64_t __otx2_io aw_status;
1214 uint64_t __otx2_io page_cnt;
1215 };
1216
1217 struct sso_hws_stats {
1218 struct mbox_msghdr hdr;
1219 uint16_t __otx2_io hws;
1220 uint64_t __otx2_io arbitration;
1221 };
1222
1223 /* CPT mailbox error codes
1224 * Range 901 - 1000.
1225 */
1226 enum cpt_af_status {
1227 CPT_AF_ERR_PARAM = -901,
1228 CPT_AF_ERR_GRP_INVALID = -902,
1229 CPT_AF_ERR_LF_INVALID = -903,
1230 CPT_AF_ERR_ACCESS_DENIED = -904,
1231 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1232 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1233 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1234 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1235 };
1236
1237 /* CPT mbox message formats */
1238
1239 struct cpt_rd_wr_reg_msg {
1240 struct mbox_msghdr hdr;
1241 uint64_t __otx2_io reg_offset;
1242 uint64_t __otx2_io *ret_val;
1243 uint64_t __otx2_io val;
1244 uint8_t __otx2_io is_write;
1245 /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
1246 uint8_t __otx2_io blkaddr;
1247 };
1248
1249 struct cpt_set_crypto_grp_req_msg {
1250 struct mbox_msghdr hdr;
1251 uint8_t __otx2_io crypto_eng_grp;
1252 };
1253
1254 struct cpt_lf_alloc_req_msg {
1255 struct mbox_msghdr hdr;
1256 uint16_t __otx2_io nix_pf_func;
1257 uint16_t __otx2_io sso_pf_func;
1258 uint16_t __otx2_io eng_grpmask;
1259 /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
1260 uint8_t __otx2_io blkaddr;
1261 };
1262
1263 struct cpt_lf_alloc_rsp_msg {
1264 struct mbox_msghdr hdr;
1265 uint16_t __otx2_io eng_grpmsk;
1266 };
1267
1268 #define CPT_INLINE_INBOUND 0
1269 #define CPT_INLINE_OUTBOUND 1
1270
1271 struct cpt_inline_ipsec_cfg_msg {
1272 struct mbox_msghdr hdr;
1273 uint8_t __otx2_io enable;
1274 uint8_t __otx2_io slot;
1275 uint8_t __otx2_io dir;
1276 uint16_t __otx2_io sso_pf_func; /* Inbound path SSO_PF_FUNC */
1277 uint16_t __otx2_io nix_pf_func; /* Outbound path NIX_PF_FUNC */
1278 };
1279
1280 struct cpt_rx_inline_lf_cfg_msg {
1281 struct mbox_msghdr hdr;
1282 uint16_t __otx2_io sso_pf_func;
1283 };
1284
1285 enum cpt_eng_type {
1286 CPT_ENG_TYPE_AE = 1,
1287 CPT_ENG_TYPE_SE = 2,
1288 CPT_ENG_TYPE_IE = 3,
1289 CPT_MAX_ENG_TYPES,
1290 };
1291
1292 /* CPT HW capabilities */
1293 union cpt_eng_caps {
1294 uint64_t __otx2_io u;
1295 struct {
1296 uint64_t __otx2_io reserved_0_4:5;
1297 uint64_t __otx2_io mul:1;
1298 uint64_t __otx2_io sha1_sha2:1;
1299 uint64_t __otx2_io chacha20:1;
1300 uint64_t __otx2_io zuc_snow3g:1;
1301 uint64_t __otx2_io sha3:1;
1302 uint64_t __otx2_io aes:1;
1303 uint64_t __otx2_io kasumi:1;
1304 uint64_t __otx2_io des:1;
1305 uint64_t __otx2_io crc:1;
1306 uint64_t __otx2_io reserved_14_63:50;
1307 };
1308 };
1309
1310 struct cpt_caps_rsp_msg {
1311 struct mbox_msghdr hdr;
1312 uint16_t __otx2_io cpt_pf_drv_version;
1313 uint8_t __otx2_io cpt_revision;
1314 union cpt_eng_caps eng_caps[CPT_MAX_ENG_TYPES];
1315 };
1316
1317 /* NPC mbox message structs */
1318
1319 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1320 #define NPC_MCAM_INVALID_MAP 0xFFFF
1321
1322 /* NPC mailbox error codes
1323 * Range 701 - 800.
1324 */
1325 enum npc_af_status {
1326 NPC_MCAM_INVALID_REQ = -701,
1327 NPC_MCAM_ALLOC_DENIED = -702,
1328 NPC_MCAM_ALLOC_FAILED = -703,
1329 NPC_MCAM_PERM_DENIED = -704,
1330 NPC_AF_ERR_HIGIG_CONFIG_FAIL = -705,
1331 };
1332
1333 struct npc_mcam_alloc_entry_req {
1334 struct mbox_msghdr hdr;
1335 #define NPC_MAX_NONCONTIG_ENTRIES 256
1336 uint8_t __otx2_io contig; /* Contiguous entries ? */
1337 #define NPC_MCAM_ANY_PRIO 0
1338 #define NPC_MCAM_LOWER_PRIO 1
1339 #define NPC_MCAM_HIGHER_PRIO 2
1340 uint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */
1341 uint16_t __otx2_io ref_entry;
1342 uint16_t __otx2_io count; /* Number of entries requested */
1343 };
1344
1345 struct npc_mcam_alloc_entry_rsp {
1346 struct mbox_msghdr hdr;
1347 /* Entry alloc'ed or start index if contiguous.
1348 * Invalid in case of non-contiguous.
1349 */
1350 uint16_t __otx2_io entry;
1351 uint16_t __otx2_io count; /* Number of entries allocated */
1352 uint16_t __otx2_io free_count; /* Number of entries available */
1353 uint16_t __otx2_io entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1354 };
1355
1356 struct npc_mcam_free_entry_req {
1357 struct mbox_msghdr hdr;
1358 uint16_t __otx2_io entry; /* Entry index to be freed */
1359 uint8_t __otx2_io all; /* Free all entries alloc'ed to this PFVF */
1360 };
1361
1362 struct mcam_entry {
1363 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max key width */
1364 uint64_t __otx2_io kw[NPC_MAX_KWS_IN_KEY];
1365 uint64_t __otx2_io kw_mask[NPC_MAX_KWS_IN_KEY];
1366 uint64_t __otx2_io action;
1367 uint64_t __otx2_io vtag_action;
1368 };
1369
1370 struct npc_mcam_write_entry_req {
1371 struct mbox_msghdr hdr;
1372 struct mcam_entry entry_data;
1373 uint16_t __otx2_io entry; /* MCAM entry to write this match key */
1374 uint16_t __otx2_io cntr; /* Counter for this MCAM entry */
1375 uint8_t __otx2_io intf; /* Rx or Tx interface */
1376 uint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */
1377 uint8_t __otx2_io set_cntr; /* Set counter for this entry ? */
1378 };
1379
1380 /* Enable/Disable a given entry */
1381 struct npc_mcam_ena_dis_entry_req {
1382 struct mbox_msghdr hdr;
1383 uint16_t __otx2_io entry;
1384 };
1385
1386 struct npc_mcam_shift_entry_req {
1387 struct mbox_msghdr hdr;
1388 #define NPC_MCAM_MAX_SHIFTS 64
1389 uint16_t __otx2_io curr_entry[NPC_MCAM_MAX_SHIFTS];
1390 uint16_t __otx2_io new_entry[NPC_MCAM_MAX_SHIFTS];
1391 uint16_t __otx2_io shift_count; /* Number of entries to shift */
1392 };
1393
1394 struct npc_mcam_shift_entry_rsp {
1395 struct mbox_msghdr hdr;
1396 /* Index in 'curr_entry', not entry itself */
1397 uint16_t __otx2_io failed_entry_idx;
1398 };
1399
1400 struct npc_mcam_alloc_counter_req {
1401 struct mbox_msghdr hdr;
1402 uint8_t __otx2_io contig; /* Contiguous counters ? */
1403 #define NPC_MAX_NONCONTIG_COUNTERS 64
1404 uint16_t __otx2_io count; /* Number of counters requested */
1405 };
1406
1407 struct npc_mcam_alloc_counter_rsp {
1408 struct mbox_msghdr hdr;
1409 /* Counter alloc'ed or start idx if contiguous.
1410 * Invalid incase of non-contiguous.
1411 */
1412 uint16_t __otx2_io cntr;
1413 uint16_t __otx2_io count; /* Number of counters allocated */
1414 uint16_t __otx2_io cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1415 };
1416
1417 struct npc_mcam_oper_counter_req {
1418 struct mbox_msghdr hdr;
1419 uint16_t __otx2_io cntr; /* Free a counter or clear/fetch it's stats */
1420 };
1421
1422 struct npc_mcam_oper_counter_rsp {
1423 struct mbox_msghdr hdr;
1424 /* valid only while fetching counter's stats */
1425 uint64_t __otx2_io stat;
1426 };
1427
1428 struct npc_mcam_unmap_counter_req {
1429 struct mbox_msghdr hdr;
1430 uint16_t __otx2_io cntr;
1431 uint16_t __otx2_io entry; /* Entry and counter to be unmapped */
1432 uint8_t __otx2_io all; /* Unmap all entries using this counter ? */
1433 };
1434
1435 struct npc_mcam_alloc_and_write_entry_req {
1436 struct mbox_msghdr hdr;
1437 struct mcam_entry entry_data;
1438 uint16_t __otx2_io ref_entry;
1439 uint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */
1440 uint8_t __otx2_io intf; /* Rx or Tx interface */
1441 uint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */
1442 uint8_t __otx2_io alloc_cntr; /* Allocate counter and map ? */
1443 };
1444
1445 struct npc_mcam_alloc_and_write_entry_rsp {
1446 struct mbox_msghdr hdr;
1447 uint16_t __otx2_io entry;
1448 uint16_t __otx2_io cntr;
1449 };
1450
1451 struct npc_get_kex_cfg_rsp {
1452 struct mbox_msghdr hdr;
1453 uint64_t __otx2_io rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1454 uint64_t __otx2_io tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1455 #define NPC_MAX_INTF 2
1456 #define NPC_MAX_LID 8
1457 #define NPC_MAX_LT 16
1458 #define NPC_MAX_LD 2
1459 #define NPC_MAX_LFL 16
1460 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1461 uint64_t __otx2_io kex_ld_flags[NPC_MAX_LD];
1462 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1463 uint64_t __otx2_io
1464 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1465 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1466 uint64_t __otx2_io
1467 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1468 #define MKEX_NAME_LEN 128
1469 uint8_t __otx2_io mkex_pfl_name[MKEX_NAME_LEN];
1470 };
1471
1472 enum header_fields {
1473 NPC_DMAC,
1474 NPC_SMAC,
1475 NPC_ETYPE,
1476 NPC_OUTER_VID,
1477 NPC_TOS,
1478 NPC_SIP_IPV4,
1479 NPC_DIP_IPV4,
1480 NPC_SIP_IPV6,
1481 NPC_DIP_IPV6,
1482 NPC_SPORT_TCP,
1483 NPC_DPORT_TCP,
1484 NPC_SPORT_UDP,
1485 NPC_DPORT_UDP,
1486 NPC_FDSA_VAL,
1487 NPC_HEADER_FIELDS_MAX,
1488 };
1489
1490 struct flow_msg {
1491 unsigned char __otx2_io dmac[6];
1492 unsigned char __otx2_io smac[6];
1493 uint16_t __otx2_io etype;
1494 uint16_t __otx2_io vlan_etype;
1495 uint16_t __otx2_io vlan_tci;
1496 union {
1497 uint32_t __otx2_io ip4src;
1498 uint32_t __otx2_io ip6src[4];
1499 };
1500 union {
1501 uint32_t __otx2_io ip4dst;
1502 uint32_t __otx2_io ip6dst[4];
1503 };
1504 uint8_t __otx2_io tos;
1505 uint8_t __otx2_io ip_ver;
1506 uint8_t __otx2_io ip_proto;
1507 uint8_t __otx2_io tc;
1508 uint16_t __otx2_io sport;
1509 uint16_t __otx2_io dport;
1510 };
1511
1512 struct npc_install_flow_req {
1513 struct mbox_msghdr hdr;
1514 struct flow_msg packet;
1515 struct flow_msg mask;
1516 uint64_t __otx2_io features;
1517 uint16_t __otx2_io entry;
1518 uint16_t __otx2_io channel;
1519 uint8_t __otx2_io intf;
1520 uint8_t __otx2_io set_cntr;
1521 uint8_t __otx2_io default_rule;
1522 /* Overwrite(0) or append(1) flow to default rule? */
1523 uint8_t __otx2_io append;
1524 uint16_t __otx2_io vf;
1525 /* action */
1526 uint32_t __otx2_io index;
1527 uint16_t __otx2_io match_id;
1528 uint8_t __otx2_io flow_key_alg;
1529 uint8_t __otx2_io op;
1530 /* vtag action */
1531 uint8_t __otx2_io vtag0_type;
1532 uint8_t __otx2_io vtag0_valid;
1533 uint8_t __otx2_io vtag1_type;
1534 uint8_t __otx2_io vtag1_valid;
1535
1536 /* vtag tx action */
1537 uint16_t __otx2_io vtag0_def;
1538 uint8_t __otx2_io vtag0_op;
1539 uint16_t __otx2_io vtag1_def;
1540 uint8_t __otx2_io vtag1_op;
1541 };
1542
1543 struct npc_install_flow_rsp {
1544 struct mbox_msghdr hdr;
1545 /* Negative if no counter else counter number */
1546 int __otx2_io counter;
1547 };
1548
1549 struct npc_delete_flow_req {
1550 struct mbox_msghdr hdr;
1551 uint16_t __otx2_io entry;
1552 uint16_t __otx2_io start;/*Disable range of entries */
1553 uint16_t __otx2_io end;
1554 uint8_t __otx2_io all; /* PF + VFs */
1555 };
1556
1557 struct npc_mcam_read_entry_req {
1558 struct mbox_msghdr hdr;
1559 /* MCAM entry to read */
1560 uint16_t __otx2_io entry;
1561 };
1562
1563 struct npc_mcam_read_entry_rsp {
1564 struct mbox_msghdr hdr;
1565 struct mcam_entry entry_data;
1566 uint8_t __otx2_io intf;
1567 uint8_t __otx2_io enable;
1568 };
1569
1570 struct npc_mcam_read_base_rule_rsp {
1571 struct mbox_msghdr hdr;
1572 struct mcam_entry entry_data;
1573 };
1574
1575 /* TIM mailbox error codes
1576 * Range 801 - 900.
1577 */
1578 enum tim_af_status {
1579 TIM_AF_NO_RINGS_LEFT = -801,
1580 TIM_AF_INVALID_NPA_PF_FUNC = -802,
1581 TIM_AF_INVALID_SSO_PF_FUNC = -803,
1582 TIM_AF_RING_STILL_RUNNING = -804,
1583 TIM_AF_LF_INVALID = -805,
1584 TIM_AF_CSIZE_NOT_ALIGNED = -806,
1585 TIM_AF_CSIZE_TOO_SMALL = -807,
1586 TIM_AF_CSIZE_TOO_BIG = -808,
1587 TIM_AF_INTERVAL_TOO_SMALL = -809,
1588 TIM_AF_INVALID_BIG_ENDIAN_VALUE = -810,
1589 TIM_AF_INVALID_CLOCK_SOURCE = -811,
1590 TIM_AF_GPIO_CLK_SRC_NOT_ENABLED = -812,
1591 TIM_AF_INVALID_BSIZE = -813,
1592 TIM_AF_INVALID_ENABLE_PERIODIC = -814,
1593 TIM_AF_INVALID_ENABLE_DONTFREE = -815,
1594 TIM_AF_ENA_DONTFRE_NSET_PERIODIC = -816,
1595 TIM_AF_RING_ALREADY_DISABLED = -817,
1596 };
1597
1598 enum tim_clk_srcs {
1599 TIM_CLK_SRCS_TENNS = 0,
1600 TIM_CLK_SRCS_GPIO = 1,
1601 TIM_CLK_SRCS_GTI = 2,
1602 TIM_CLK_SRCS_PTP = 3,
1603 TIM_CLK_SRSC_INVALID,
1604 };
1605
1606 enum tim_gpio_edge {
1607 TIM_GPIO_NO_EDGE = 0,
1608 TIM_GPIO_LTOH_TRANS = 1,
1609 TIM_GPIO_HTOL_TRANS = 2,
1610 TIM_GPIO_BOTH_TRANS = 3,
1611 TIM_GPIO_INVALID,
1612 };
1613
1614 enum ptp_op {
1615 PTP_OP_ADJFINE = 0, /* adjfine(req.scaled_ppm); */
1616 PTP_OP_GET_CLOCK = 1, /* rsp.clk = get_clock() */
1617 };
1618
1619 struct ptp_req {
1620 struct mbox_msghdr hdr;
1621 uint8_t __otx2_io op;
1622 int64_t __otx2_io scaled_ppm;
1623 uint8_t __otx2_io is_pmu;
1624 };
1625
1626 struct ptp_rsp {
1627 struct mbox_msghdr hdr;
1628 uint64_t __otx2_io clk;
1629 uint64_t __otx2_io tsc;
1630 };
1631
1632 struct get_hw_cap_rsp {
1633 struct mbox_msghdr hdr;
1634 /* Schq mapping fixed or flexible */
1635 uint8_t __otx2_io nix_fixed_txschq_mapping;
1636 uint8_t __otx2_io nix_shaping; /* Is shaping and coloring supported */
1637 };
1638
1639 struct ndc_sync_op {
1640 struct mbox_msghdr hdr;
1641 uint8_t __otx2_io nix_lf_tx_sync;
1642 uint8_t __otx2_io nix_lf_rx_sync;
1643 uint8_t __otx2_io npa_lf_sync;
1644 };
1645
1646 struct tim_lf_alloc_req {
1647 struct mbox_msghdr hdr;
1648 uint16_t __otx2_io ring;
1649 uint16_t __otx2_io npa_pf_func;
1650 uint16_t __otx2_io sso_pf_func;
1651 };
1652
1653 struct tim_ring_req {
1654 struct mbox_msghdr hdr;
1655 uint16_t __otx2_io ring;
1656 };
1657
1658 struct tim_config_req {
1659 struct mbox_msghdr hdr;
1660 uint16_t __otx2_io ring;
1661 uint8_t __otx2_io bigendian;
1662 uint8_t __otx2_io clocksource;
1663 uint8_t __otx2_io enableperiodic;
1664 uint8_t __otx2_io enabledontfreebuffer;
1665 uint32_t __otx2_io bucketsize;
1666 uint32_t __otx2_io chunksize;
1667 uint32_t __otx2_io interval;
1668 };
1669
1670 struct tim_lf_alloc_rsp {
1671 struct mbox_msghdr hdr;
1672 uint64_t __otx2_io tenns_clk;
1673 };
1674
1675 struct tim_enable_rsp {
1676 struct mbox_msghdr hdr;
1677 uint64_t __otx2_io timestarted;
1678 uint32_t __otx2_io currentbucket;
1679 };
1680
1681 /* REE mailbox error codes
1682 * Range 1001 - 1100.
1683 */
1684 enum ree_af_status {
1685 REE_AF_ERR_RULE_UNKNOWN_VALUE = -1001,
1686 REE_AF_ERR_LF_NO_MORE_RESOURCES = -1002,
1687 REE_AF_ERR_LF_INVALID = -1003,
1688 REE_AF_ERR_ACCESS_DENIED = -1004,
1689 REE_AF_ERR_RULE_DB_PARTIAL = -1005,
1690 REE_AF_ERR_RULE_DB_EQ_BAD_VALUE = -1006,
1691 REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED = -1007,
1692 REE_AF_ERR_BLOCK_NOT_IMPLEMENTED = -1008,
1693 REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG = -1009,
1694 REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG = -1010,
1695 REE_AF_ERR_Q_IS_GRACEFUL_DIS = -1011,
1696 REE_AF_ERR_Q_NOT_GRACEFUL_DIS = -1012,
1697 REE_AF_ERR_RULE_DB_ALLOC_FAILED = -1013,
1698 REE_AF_ERR_RULE_DB_TOO_BIG = -1014,
1699 REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE = -1015,
1700 REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE = -1016,
1701 REE_AF_ERR_RULE_DB_WRONG_LENGTH = -1017,
1702 REE_AF_ERR_RULE_DB_WRONG_OFFSET = -1018,
1703 REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG = -1019,
1704 REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST = -1020,
1705 REE_AF_ERR_RULE_DBI_ALLOC_FAILED = -1021,
1706 REE_AF_ERR_LF_WRONG_PRIORITY = -1022,
1707 REE_AF_ERR_LF_SIZE_TOO_BIG = -1023,
1708 };
1709
1710 /* REE mbox message formats */
1711
1712 struct ree_req_msg {
1713 struct mbox_msghdr hdr;
1714 uint32_t __otx2_io blkaddr;
1715 };
1716
1717 struct ree_lf_req_msg {
1718 struct mbox_msghdr hdr;
1719 uint32_t __otx2_io blkaddr;
1720 uint32_t __otx2_io size;
1721 uint8_t __otx2_io lf;
1722 uint8_t __otx2_io pri;
1723 };
1724
1725 struct ree_rule_db_prog_req_msg {
1726 struct mbox_msghdr hdr;
1727 #define REE_RULE_DB_REQ_BLOCK_SIZE (MBOX_SIZE >> 1)
1728 uint8_t __otx2_io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];
1729 uint32_t __otx2_io blkaddr; /* REE0 or REE1 */
1730 uint32_t __otx2_io total_len; /* total len of rule db */
1731 uint32_t __otx2_io offset; /* offset of current rule db block */
1732 uint16_t __otx2_io len; /* length of rule db block */
1733 uint8_t __otx2_io is_last; /* is this the last block */
1734 uint8_t __otx2_io is_incremental; /* is incremental flow */
1735 uint8_t __otx2_io is_dbi; /* is rule db incremental */
1736 };
1737
1738 struct ree_rule_db_get_req_msg {
1739 struct mbox_msghdr hdr;
1740 uint32_t __otx2_io blkaddr;
1741 uint32_t __otx2_io offset; /* retrieve db from this offset */
1742 uint8_t __otx2_io is_dbi; /* is request for rule db incremental */
1743 };
1744
1745 struct ree_rd_wr_reg_msg {
1746 struct mbox_msghdr hdr;
1747 uint64_t __otx2_io reg_offset;
1748 uint64_t __otx2_io *ret_val;
1749 uint64_t __otx2_io val;
1750 uint32_t __otx2_io blkaddr;
1751 uint8_t __otx2_io is_write;
1752 };
1753
1754 struct ree_rule_db_len_rsp_msg {
1755 struct mbox_msghdr hdr;
1756 uint32_t __otx2_io blkaddr;
1757 uint32_t __otx2_io len;
1758 uint32_t __otx2_io inc_len;
1759 };
1760
1761 struct ree_rule_db_get_rsp_msg {
1762 struct mbox_msghdr hdr;
1763 #define REE_RULE_DB_RSP_BLOCK_SIZE (MBOX_DOWN_TX_SIZE - SZ_1K)
1764 uint8_t __otx2_io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];
1765 uint32_t __otx2_io total_len; /* total len of rule db */
1766 uint32_t __otx2_io offset; /* offset of current rule db block */
1767 uint16_t __otx2_io len; /* length of rule db block */
1768 uint8_t __otx2_io is_last; /* is this the last block */
1769 };
1770
1771 __rte_internal
1772 const char *otx2_mbox_id2name(uint16_t id);
1773 int otx2_mbox_id2size(uint16_t id);
1774 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
1775 int otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase, uintptr_t reg_base,
1776 int direction, int ndevsi, uint64_t intr_offset);
1777 void otx2_mbox_fini(struct otx2_mbox *mbox);
1778 __rte_internal
1779 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
1780 __rte_internal
1781 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
1782 int otx2_mbox_wait_for_rsp_tmo(struct otx2_mbox *mbox, int devid, uint32_t tmo);
1783 __rte_internal
1784 int otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, void **msg);
1785 __rte_internal
1786 int otx2_mbox_get_rsp_tmo(struct otx2_mbox *mbox, int devid, void **msg,
1787 uint32_t tmo);
1788 int otx2_mbox_get_availmem(struct otx2_mbox *mbox, int devid);
1789 __rte_internal
1790 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
1791 int size, int size_rsp);
1792
1793 static inline struct mbox_msghdr *
otx2_mbox_alloc_msg(struct otx2_mbox * mbox,int devid,int size)1794 otx2_mbox_alloc_msg(struct otx2_mbox *mbox, int devid, int size)
1795 {
1796 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
1797 }
1798
1799 static inline void
otx2_mbox_req_init(uint16_t mbox_id,void * msghdr)1800 otx2_mbox_req_init(uint16_t mbox_id, void *msghdr)
1801 {
1802 struct mbox_msghdr *hdr = msghdr;
1803
1804 hdr->sig = OTX2_MBOX_REQ_SIG;
1805 hdr->ver = OTX2_MBOX_VERSION;
1806 hdr->id = mbox_id;
1807 hdr->pcifunc = 0;
1808 }
1809
1810 static inline void
otx2_mbox_rsp_init(uint16_t mbox_id,void * msghdr)1811 otx2_mbox_rsp_init(uint16_t mbox_id, void *msghdr)
1812 {
1813 struct mbox_msghdr *hdr = msghdr;
1814
1815 hdr->sig = OTX2_MBOX_RSP_SIG;
1816 hdr->rc = -ETIMEDOUT;
1817 hdr->id = mbox_id;
1818 }
1819
1820 static inline bool
otx2_mbox_nonempty(struct otx2_mbox * mbox,int devid)1821 otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid)
1822 {
1823 struct otx2_mbox_dev *mdev = &mbox->dev[devid];
1824 bool ret;
1825
1826 rte_spinlock_lock(&mdev->mbox_lock);
1827 ret = mdev->num_msgs != 0;
1828 rte_spinlock_unlock(&mdev->mbox_lock);
1829
1830 return ret;
1831 }
1832
1833 static inline int
otx2_mbox_process(struct otx2_mbox * mbox)1834 otx2_mbox_process(struct otx2_mbox *mbox)
1835 {
1836 otx2_mbox_msg_send(mbox, 0);
1837 return otx2_mbox_get_rsp(mbox, 0, NULL);
1838 }
1839
1840 static inline int
otx2_mbox_process_msg(struct otx2_mbox * mbox,void ** msg)1841 otx2_mbox_process_msg(struct otx2_mbox *mbox, void **msg)
1842 {
1843 otx2_mbox_msg_send(mbox, 0);
1844 return otx2_mbox_get_rsp(mbox, 0, msg);
1845 }
1846
1847 static inline int
otx2_mbox_process_tmo(struct otx2_mbox * mbox,uint32_t tmo)1848 otx2_mbox_process_tmo(struct otx2_mbox *mbox, uint32_t tmo)
1849 {
1850 otx2_mbox_msg_send(mbox, 0);
1851 return otx2_mbox_get_rsp_tmo(mbox, 0, NULL, tmo);
1852 }
1853
1854 static inline int
otx2_mbox_process_msg_tmo(struct otx2_mbox * mbox,void ** msg,uint32_t tmo)1855 otx2_mbox_process_msg_tmo(struct otx2_mbox *mbox, void **msg, uint32_t tmo)
1856 {
1857 otx2_mbox_msg_send(mbox, 0);
1858 return otx2_mbox_get_rsp_tmo(mbox, 0, msg, tmo);
1859 }
1860
1861 int otx2_send_ready_msg(struct otx2_mbox *mbox, uint16_t *pf_func /* out */);
1862 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, uint16_t pf_func,
1863 uint16_t id);
1864
1865 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
1866 static inline struct _req_type \
1867 *otx2_mbox_alloc_msg_ ## _fn_name(struct otx2_mbox *mbox) \
1868 { \
1869 struct _req_type *req; \
1870 \
1871 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
1872 mbox, 0, sizeof(struct _req_type), \
1873 sizeof(struct _rsp_type)); \
1874 if (!req) \
1875 return NULL; \
1876 \
1877 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
1878 req->hdr.id = _id; \
1879 otx2_mbox_dbg("id=0x%x (%s)", \
1880 req->hdr.id, otx2_mbox_id2name(req->hdr.id)); \
1881 return req; \
1882 }
1883
1884 MBOX_MESSAGES
1885 #undef M
1886
1887 /* This is required for copy operations from device memory which do not work on
1888 * addresses which are unaligned to 16B. This is because of specific
1889 * optimizations to libc memcpy.
1890 */
1891 static inline volatile void *
otx2_mbox_memcpy(volatile void * d,const volatile void * s,size_t l)1892 otx2_mbox_memcpy(volatile void *d, const volatile void *s, size_t l)
1893 {
1894 const volatile uint8_t *sb;
1895 volatile uint8_t *db;
1896 size_t i;
1897
1898 if (!d || !s)
1899 return NULL;
1900 db = (volatile uint8_t *)d;
1901 sb = (const volatile uint8_t *)s;
1902 for (i = 0; i < l; i++)
1903 db[i] = sb[i];
1904 return d;
1905 }
1906
1907 /* This is required for memory operations from device memory which do not
1908 * work on addresses which are unaligned to 16B. This is because of specific
1909 * optimizations to libc memset.
1910 */
1911 static inline void
otx2_mbox_memset(volatile void * d,uint8_t val,size_t l)1912 otx2_mbox_memset(volatile void *d, uint8_t val, size_t l)
1913 {
1914 volatile uint8_t *db;
1915 size_t i = 0;
1916
1917 if (!d || !l)
1918 return;
1919 db = (volatile uint8_t *)d;
1920 for (i = 0; i < l; i++)
1921 db[i] = val;
1922 }
1923
1924 #endif /* __OTX2_MBOX_H__ */
1925