1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 3 */ 4 5 #ifndef _TXGBE_MNG_H_ 6 #define _TXGBE_MNG_H_ 7 8 #include "txgbe_type.h" 9 10 11 #define TXGBE_PMMBX_QSIZE 64 /* Num of dwords in range */ 12 #define TXGBE_PMMBX_BSIZE (TXGBE_PMMBX_QSIZE * 4) 13 #define TXGBE_PMMBX_DATA_SIZE (TXGBE_PMMBX_BSIZE - FW_NVM_DATA_OFFSET * 4) 14 #define TXGBE_HI_COMMAND_TIMEOUT 5000 /* Process HI command limit */ 15 #define TXGBE_HI_FLASH_ERASE_TIMEOUT 5000 /* Process Erase command limit */ 16 #define TXGBE_HI_FLASH_UPDATE_TIMEOUT 5000 /* Process Update command limit */ 17 #define TXGBE_HI_FLASH_VERIFY_TIMEOUT 60000 /* Process Apply command limit */ 18 #define TXGBE_HI_PHY_MGMT_REQ_TIMEOUT 2000 /* Wait up to 2 seconds */ 19 20 /* CEM Support */ 21 #define FW_CEM_HDR_LEN 0x4 22 #define FW_CEM_CMD_DRIVER_INFO 0xDD 23 #define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 24 #define FW_CEM_CMD_RESERVED 0X0 25 #define FW_CEM_UNUSED_VER 0x0 26 #define FW_CEM_MAX_RETRIES 3 27 #define FW_CEM_RESP_STATUS_SUCCESS 0x1 28 #define FW_READ_SHADOW_RAM_CMD 0x31 29 #define FW_READ_SHADOW_RAM_LEN 0x6 30 #define FW_WRITE_SHADOW_RAM_CMD 0x33 31 #define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */ 32 #define FW_SHADOW_RAM_DUMP_CMD 0x36 33 #define FW_SHADOW_RAM_DUMP_LEN 0 34 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 35 #define FW_NVM_DATA_OFFSET 3 36 #define FW_MAX_READ_BUFFER_SIZE 244 37 #define FW_DISABLE_RXEN_CMD 0xDE 38 #define FW_DISABLE_RXEN_LEN 0x1 39 #define FW_PHY_MGMT_REQ_CMD 0x20 40 #define FW_RESET_CMD 0xDF 41 #define FW_RESET_LEN 0x2 42 #define FW_SETUP_MAC_LINK_CMD 0xE0 43 #define FW_SETUP_MAC_LINK_LEN 0x2 44 #define FW_FLASH_UPGRADE_START_CMD 0xE3 45 #define FW_FLASH_UPGRADE_START_LEN 0x1 46 #define FW_FLASH_UPGRADE_WRITE_CMD 0xE4 47 #define FW_FLASH_UPGRADE_VERIFY_CMD 0xE5 48 #define FW_FLASH_UPGRADE_VERIFY_LEN 0x4 49 #define FW_PHY_ACT_DATA_COUNT 4 50 #define FW_PHY_TOKEN_DELAY 5 /* milliseconds */ 51 #define FW_PHY_TOKEN_WAIT 5 /* seconds */ 52 #define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY) 53 54 /* Host Interface Command Structures */ 55 struct txgbe_hic_hdr { 56 u8 cmd; 57 u8 buf_len; 58 union { 59 u8 cmd_resv; 60 u8 ret_status; 61 } cmd_or_resp; 62 u8 checksum; 63 }; 64 65 struct txgbe_hic_hdr2_req { 66 u8 cmd; 67 u8 buf_lenh; 68 u8 buf_lenl; 69 u8 checksum; 70 }; 71 72 struct txgbe_hic_hdr2_rsp { 73 u8 cmd; 74 u8 buf_lenl; 75 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */ 76 u8 checksum; 77 }; 78 79 union txgbe_hic_hdr2 { 80 struct txgbe_hic_hdr2_req req; 81 struct txgbe_hic_hdr2_rsp rsp; 82 }; 83 84 struct txgbe_hic_drv_info { 85 struct txgbe_hic_hdr hdr; 86 u8 port_num; 87 u8 ver_sub; 88 u8 ver_build; 89 u8 ver_min; 90 u8 ver_maj; 91 u8 pad; /* end spacing to ensure length is mult. of dword */ 92 u16 pad2; /* end spacing to ensure length is mult. of dword2 */ 93 }; 94 95 /* These need to be dword aligned */ 96 struct txgbe_hic_read_shadow_ram { 97 union txgbe_hic_hdr2 hdr; 98 u32 address; 99 u16 length; 100 u16 pad2; 101 u16 data; 102 u16 pad3; 103 }; 104 105 struct txgbe_hic_write_shadow_ram { 106 union txgbe_hic_hdr2 hdr; 107 u32 address; 108 u16 length; 109 u16 pad2; 110 u16 data; 111 u16 pad3; 112 }; 113 114 struct txgbe_hic_disable_rxen { 115 struct txgbe_hic_hdr hdr; 116 u8 port_number; 117 u8 pad2; 118 u16 pad3; 119 }; 120 121 struct txgbe_hic_reset { 122 struct txgbe_hic_hdr hdr; 123 u16 lan_id; 124 u16 reset_type; 125 }; 126 127 struct txgbe_hic_phy_cfg { 128 struct txgbe_hic_hdr hdr; 129 u8 lan_id; 130 u8 phy_mode; 131 u16 phy_speed; 132 }; 133 134 enum txgbe_module_id { 135 TXGBE_MODULE_EEPROM = 0, 136 TXGBE_MODULE_FIRMWARE, 137 TXGBE_MODULE_HARDWARE, 138 TXGBE_MODULE_PCIE 139 }; 140 141 struct txgbe_hic_upg_start { 142 struct txgbe_hic_hdr hdr; 143 u8 module_id; 144 u8 pad2; 145 u16 pad3; 146 }; 147 148 struct txgbe_hic_upg_write { 149 struct txgbe_hic_hdr hdr; 150 u8 data_len; 151 u8 eof_flag; 152 u16 check_sum; 153 u32 data[62]; 154 }; 155 156 enum txgbe_upg_flag { 157 TXGBE_RESET_NONE = 0, 158 TXGBE_RESET_FIRMWARE, 159 TXGBE_RELOAD_EEPROM, 160 TXGBE_RESET_LAN 161 }; 162 163 struct txgbe_hic_upg_verify { 164 struct txgbe_hic_hdr hdr; 165 u32 action_flag; 166 }; 167 168 s32 txgbe_hic_sr_read(struct txgbe_hw *hw, u32 addr, u8 *buf, int len); 169 s32 txgbe_hic_sr_write(struct txgbe_hw *hw, u32 addr, u8 *buf, int len); 170 171 s32 txgbe_hic_set_drv_ver(struct txgbe_hw *hw, u8 maj, u8 min, u8 build, 172 u8 ver, u16 len, const char *str); 173 s32 txgbe_hic_reset(struct txgbe_hw *hw); 174 bool txgbe_mng_present(struct txgbe_hw *hw); 175 bool txgbe_mng_enabled(struct txgbe_hw *hw); 176 #endif /* _TXGBE_MNG_H_ */ 177