1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _E1000_PHY_H_ 6 #define _E1000_PHY_H_ 7 8 void e1000_init_phy_ops_generic(struct e1000_hw *hw); 9 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data); 10 void e1000_null_phy_generic(struct e1000_hw *hw); 11 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active); 12 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data); 13 s32 e1000_null_set_page(struct e1000_hw *hw, u16 data); 14 s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset, 15 u8 dev_addr, u8 *data); 16 s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset, 17 u8 dev_addr, u8 data); 18 s32 e1000_check_downshift_generic(struct e1000_hw *hw); 19 s32 e1000_check_polarity_m88(struct e1000_hw *hw); 20 s32 e1000_check_polarity_igp(struct e1000_hw *hw); 21 s32 e1000_check_polarity_ife(struct e1000_hw *hw); 22 s32 e1000_check_reset_block_generic(struct e1000_hw *hw); 23 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); 24 s32 e1000_copper_link_autoneg(struct e1000_hw *hw); 25 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw); 26 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw); 27 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw); 28 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw); 29 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw); 30 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); 31 s32 e1000_get_cable_length_m88(struct e1000_hw *hw); 32 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw); 33 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw); 34 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw); 35 s32 e1000_get_phy_id(struct e1000_hw *hw); 36 s32 e1000_get_phy_info_igp(struct e1000_hw *hw); 37 s32 e1000_get_phy_info_m88(struct e1000_hw *hw); 38 s32 e1000_get_phy_info_ife(struct e1000_hw *hw); 39 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw); 40 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); 41 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw); 42 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw); 43 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data); 44 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data); 45 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page); 46 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 47 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data); 48 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); 49 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active); 50 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw); 51 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data); 52 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data); 53 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 54 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data); 55 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); 56 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 57 u32 usec_interval, bool *success); 58 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw); 59 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id); 60 s32 e1000_determine_phy_address(struct e1000_hw *hw); 61 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); 62 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); 63 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); 64 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); 65 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); 66 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); 67 void e1000_power_up_phy_copper(struct e1000_hw *hw); 68 void e1000_power_down_phy_copper(struct e1000_hw *hw); 69 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); 70 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); 71 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data); 72 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data); 73 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data); 74 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data); 75 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); 76 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data); 77 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data); 78 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); 79 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data); 80 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data); 81 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); 82 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); 83 s32 e1000_check_polarity_82577(struct e1000_hw *hw); 84 s32 e1000_get_phy_info_82577(struct e1000_hw *hw); 85 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); 86 s32 e1000_get_cable_length_82577(struct e1000_hw *hw); 87 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data); 88 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); 89 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data); 90 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data, 91 bool line_override); 92 bool e1000_is_mphy_ready(struct e1000_hw *hw); 93 94 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, 95 u16 *data); 96 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, 97 u16 data); 98 99 #define E1000_MAX_PHY_ADDR 8 100 101 /* IGP01E1000 Specific Registers */ 102 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 103 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 104 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 105 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 106 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ 107 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 108 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 109 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ 110 #define IGP_PAGE_SHIFT 5 111 #define PHY_REG_MASK 0x1F 112 113 /* GS40G - I210 PHY defines */ 114 #define GS40G_PAGE_SELECT 0x16 115 #define GS40G_PAGE_SHIFT 16 116 #define GS40G_OFFSET_MASK 0xFFFF 117 #define GS40G_PAGE_2 0x20000 118 #define GS40G_MAC_REG2 0x15 119 #define GS40G_MAC_LB 0x4140 120 #define GS40G_MAC_SPEED_1G 0X0006 121 #define GS40G_COPPER_SPEC 0x0010 122 123 /* BM/HV Specific Registers */ 124 #define BM_PORT_CTRL_PAGE 769 125 #define BM_WUC_PAGE 800 126 #define BM_WUC_ADDRESS_OPCODE 0x11 127 #define BM_WUC_DATA_OPCODE 0x12 128 #define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE 129 #define BM_WUC_ENABLE_REG 17 130 #define BM_WUC_ENABLE_BIT (1 << 2) 131 #define BM_WUC_HOST_WU_BIT (1 << 4) 132 #define BM_WUC_ME_WU_BIT (1 << 5) 133 134 #define PHY_UPPER_SHIFT 21 135 #define BM_PHY_REG(page, reg) \ 136 (((reg) & MAX_PHY_REG_ADDRESS) |\ 137 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ 138 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) 139 #define BM_PHY_REG_PAGE(offset) \ 140 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) 141 #define BM_PHY_REG_NUM(offset) \ 142 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ 143 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ 144 ~MAX_PHY_REG_ADDRESS))) 145 146 #define HV_INTC_FC_PAGE_START 768 147 #define I82578_ADDR_REG 29 148 #define I82577_ADDR_REG 16 149 #define I82577_CFG_REG 22 150 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) 151 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift */ 152 #define I82577_CTRL_REG 23 153 154 /* 82577 specific PHY registers */ 155 #define I82577_PHY_CTRL_2 18 156 #define I82577_PHY_LBK_CTRL 19 157 #define I82577_PHY_STATUS_2 26 158 #define I82577_PHY_DIAG_STATUS 31 159 160 /* I82577 PHY Status 2 */ 161 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 162 #define I82577_PHY_STATUS2_MDIX 0x0800 163 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 164 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 165 166 /* I82577 PHY Control 2 */ 167 #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200 168 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400 169 #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600 170 171 /* I82577 PHY Diagnostics Status */ 172 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC 173 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 174 175 /* 82580 PHY Power Management */ 176 #define E1000_82580_PHY_POWER_MGMT 0xE14 177 #define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */ 178 #define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */ 179 #define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */ 180 #define E1000_82580_PM_GO_LINKD 0x0020 /* Go Link Disconnect */ 181 182 #define E1000_MPHY_DIS_ACCESS 0x80000000 /* disable_access bit */ 183 #define E1000_MPHY_ENA_ACCESS 0x40000000 /* enable_access bit */ 184 #define E1000_MPHY_BUSY 0x00010000 /* busy bit */ 185 #define E1000_MPHY_ADDRESS_FNC_OVERRIDE 0x20000000 /* fnc_override bit */ 186 #define E1000_MPHY_ADDRESS_MASK 0x0000FFFF /* address mask */ 187 188 /* BM PHY Copper Specific Control 1 */ 189 #define BM_CS_CTRL1 16 190 191 /* BM PHY Copper Specific Status */ 192 #define BM_CS_STATUS 17 193 #define BM_CS_STATUS_LINK_UP 0x0400 194 #define BM_CS_STATUS_RESOLVED 0x0800 195 #define BM_CS_STATUS_SPEED_MASK 0xC000 196 #define BM_CS_STATUS_SPEED_1000 0x8000 197 198 /* 82577 Mobile Phy Status Register */ 199 #define HV_M_STATUS 26 200 #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 201 #define HV_M_STATUS_SPEED_MASK 0x0300 202 #define HV_M_STATUS_SPEED_1000 0x0200 203 #define HV_M_STATUS_SPEED_100 0x0100 204 #define HV_M_STATUS_LINK_UP 0x0040 205 206 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 207 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 208 209 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 210 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 211 212 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 213 214 /* Enable flexible speed on link-up */ 215 #define IGP01E1000_GMII_FLEX_SPD 0x0010 216 #define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */ 217 218 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 219 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ 220 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ 221 222 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 223 224 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 225 #define IGP01E1000_PSSR_MDIX 0x0800 226 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 227 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 228 229 #define IGP02E1000_PHY_CHANNEL_NUM 4 230 #define IGP02E1000_PHY_AGC_A 0x11B1 231 #define IGP02E1000_PHY_AGC_B 0x12B1 232 #define IGP02E1000_PHY_AGC_C 0x14B1 233 #define IGP02E1000_PHY_AGC_D 0x18B1 234 235 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */ 236 #define IGP02E1000_AGC_LENGTH_MASK 0x7F 237 #define IGP02E1000_AGC_RANGE 15 238 239 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF 240 241 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 242 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 243 #define E1000_KMRNCTRLSTA_REN 0x00200000 244 #define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */ 245 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ 246 #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ 247 #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ 248 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ 249 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ 250 #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 251 #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */ 252 #define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */ 253 #define E1000_KMRNCTRLSTA_K0S_CTRL 0x1E /* Kumeran K0s Control */ 254 #define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT 0 255 #define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT 4 256 #define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_MASK \ 257 (3 << E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT) 258 #define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK \ 259 (7 << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT) 260 #define E1000_KMRNCTRLSTA_OP_MODES 0x1F /* Kumeran Modes of Operation */ 261 #define E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC 0x0002 /* change LSC to CSC */ 262 263 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 264 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */ 265 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */ 266 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ 267 268 /* IFE PHY Extended Status Control */ 269 #define IFE_PESC_POLARITY_REVERSED 0x0100 270 271 /* IFE PHY Special Control */ 272 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 273 #define IFE_PSC_FORCE_POLARITY 0x0020 274 275 /* IFE PHY Special Control and LED Control */ 276 #define IFE_PSCL_PROBE_MODE 0x0020 277 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 278 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 279 280 /* IFE PHY MDIX Control */ 281 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 282 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ 283 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */ 284 285 /* SFP modules ID memory locations */ 286 #define E1000_SFF_IDENTIFIER_OFFSET 0x00 287 #define E1000_SFF_IDENTIFIER_SFF 0x02 288 #define E1000_SFF_IDENTIFIER_SFP 0x03 289 290 #define E1000_SFF_ETH_FLAGS_OFFSET 0x06 291 /* Flags for SFP modules compatible with ETH up to 1Gb */ 292 struct sfp_e1000_flags { 293 u8 e1000_base_sx:1; 294 u8 e1000_base_lx:1; 295 u8 e1000_base_cx:1; 296 u8 e1000_base_t:1; 297 u8 e100_base_lx:1; 298 u8 e100_base_fx:1; 299 u8 e10_base_bx10:1; 300 u8 e10_base_px:1; 301 }; 302 303 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ 304 #define E1000_SFF_VENDOR_OUI_TYCO 0x00407600 305 #define E1000_SFF_VENDOR_OUI_FTL 0x00906500 306 #define E1000_SFF_VENDOR_OUI_AVAGO 0x00176A00 307 #define E1000_SFF_VENDOR_OUI_INTEL 0x001B2100 308 309 /* EEPROM byte offsets */ 310 #define IGB_SFF_8472_SWAP 0x5C 311 #define IGB_SFF_8472_COMP 0x5E 312 313 /* Bitmasks */ 314 #define IGB_SFF_ADDRESSING_MODE 0x4 315 #define IGB_SFF_8472_UNSUP 0x00 316 317 #endif 318