1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2016-2020 Intel Corporation 3 */ 4 5 #ifndef __DLB_USER_H 6 #define __DLB_USER_H 7 8 #include <linux/types.h> 9 10 #define DLB_MAX_NAME_LEN 64 11 12 enum dlb_error { 13 DLB_ST_SUCCESS = 0, 14 DLB_ST_NAME_EXISTS, 15 DLB_ST_DOMAIN_UNAVAILABLE, 16 DLB_ST_LDB_PORTS_UNAVAILABLE, 17 DLB_ST_DIR_PORTS_UNAVAILABLE, 18 DLB_ST_LDB_QUEUES_UNAVAILABLE, 19 DLB_ST_LDB_CREDITS_UNAVAILABLE, 20 DLB_ST_DIR_CREDITS_UNAVAILABLE, 21 DLB_ST_LDB_CREDIT_POOLS_UNAVAILABLE, 22 DLB_ST_DIR_CREDIT_POOLS_UNAVAILABLE, 23 DLB_ST_SEQUENCE_NUMBERS_UNAVAILABLE, 24 DLB_ST_INVALID_DOMAIN_ID, 25 DLB_ST_INVALID_QID_INFLIGHT_ALLOCATION, 26 DLB_ST_ATOMIC_INFLIGHTS_UNAVAILABLE, 27 DLB_ST_HIST_LIST_ENTRIES_UNAVAILABLE, 28 DLB_ST_INVALID_LDB_CREDIT_POOL_ID, 29 DLB_ST_INVALID_DIR_CREDIT_POOL_ID, 30 DLB_ST_INVALID_POP_COUNT_VIRT_ADDR, 31 DLB_ST_INVALID_LDB_QUEUE_ID, 32 DLB_ST_INVALID_CQ_DEPTH, 33 DLB_ST_INVALID_CQ_VIRT_ADDR, 34 DLB_ST_INVALID_PORT_ID, 35 DLB_ST_INVALID_QID, 36 DLB_ST_INVALID_PRIORITY, 37 DLB_ST_NO_QID_SLOTS_AVAILABLE, 38 DLB_ST_QED_FREELIST_ENTRIES_UNAVAILABLE, 39 DLB_ST_DQED_FREELIST_ENTRIES_UNAVAILABLE, 40 DLB_ST_INVALID_DIR_QUEUE_ID, 41 DLB_ST_DIR_QUEUES_UNAVAILABLE, 42 DLB_ST_INVALID_LDB_CREDIT_LOW_WATERMARK, 43 DLB_ST_INVALID_LDB_CREDIT_QUANTUM, 44 DLB_ST_INVALID_DIR_CREDIT_LOW_WATERMARK, 45 DLB_ST_INVALID_DIR_CREDIT_QUANTUM, 46 DLB_ST_DOMAIN_NOT_CONFIGURED, 47 DLB_ST_PID_ALREADY_ATTACHED, 48 DLB_ST_PID_NOT_ATTACHED, 49 DLB_ST_INTERNAL_ERROR, 50 DLB_ST_DOMAIN_IN_USE, 51 DLB_ST_IOMMU_MAPPING_ERROR, 52 DLB_ST_FAIL_TO_PIN_MEMORY_PAGE, 53 DLB_ST_UNABLE_TO_PIN_POPCOUNT_PAGES, 54 DLB_ST_UNABLE_TO_PIN_CQ_PAGES, 55 DLB_ST_DISCONTIGUOUS_CQ_MEMORY, 56 DLB_ST_DISCONTIGUOUS_POP_COUNT_MEMORY, 57 DLB_ST_DOMAIN_STARTED, 58 DLB_ST_LARGE_POOL_NOT_SPECIFIED, 59 DLB_ST_SMALL_POOL_NOT_SPECIFIED, 60 DLB_ST_NEITHER_POOL_SPECIFIED, 61 DLB_ST_DOMAIN_NOT_STARTED, 62 DLB_ST_INVALID_MEASUREMENT_DURATION, 63 DLB_ST_INVALID_PERF_METRIC_GROUP_ID, 64 DLB_ST_LDB_PORT_REQUIRED_FOR_LDB_QUEUES, 65 DLB_ST_DOMAIN_RESET_FAILED, 66 DLB_ST_MBOX_ERROR, 67 DLB_ST_INVALID_HIST_LIST_DEPTH, 68 DLB_ST_NO_MEMORY, 69 }; 70 71 static const char dlb_error_strings[][128] = { 72 "DLB_ST_SUCCESS", 73 "DLB_ST_NAME_EXISTS", 74 "DLB_ST_DOMAIN_UNAVAILABLE", 75 "DLB_ST_LDB_PORTS_UNAVAILABLE", 76 "DLB_ST_DIR_PORTS_UNAVAILABLE", 77 "DLB_ST_LDB_QUEUES_UNAVAILABLE", 78 "DLB_ST_LDB_CREDITS_UNAVAILABLE", 79 "DLB_ST_DIR_CREDITS_UNAVAILABLE", 80 "DLB_ST_LDB_CREDIT_POOLS_UNAVAILABLE", 81 "DLB_ST_DIR_CREDIT_POOLS_UNAVAILABLE", 82 "DLB_ST_SEQUENCE_NUMBERS_UNAVAILABLE", 83 "DLB_ST_INVALID_DOMAIN_ID", 84 "DLB_ST_INVALID_QID_INFLIGHT_ALLOCATION", 85 "DLB_ST_ATOMIC_INFLIGHTS_UNAVAILABLE", 86 "DLB_ST_HIST_LIST_ENTRIES_UNAVAILABLE", 87 "DLB_ST_INVALID_LDB_CREDIT_POOL_ID", 88 "DLB_ST_INVALID_DIR_CREDIT_POOL_ID", 89 "DLB_ST_INVALID_POP_COUNT_VIRT_ADDR", 90 "DLB_ST_INVALID_LDB_QUEUE_ID", 91 "DLB_ST_INVALID_CQ_DEPTH", 92 "DLB_ST_INVALID_CQ_VIRT_ADDR", 93 "DLB_ST_INVALID_PORT_ID", 94 "DLB_ST_INVALID_QID", 95 "DLB_ST_INVALID_PRIORITY", 96 "DLB_ST_NO_QID_SLOTS_AVAILABLE", 97 "DLB_ST_QED_FREELIST_ENTRIES_UNAVAILABLE", 98 "DLB_ST_DQED_FREELIST_ENTRIES_UNAVAILABLE", 99 "DLB_ST_INVALID_DIR_QUEUE_ID", 100 "DLB_ST_DIR_QUEUES_UNAVAILABLE", 101 "DLB_ST_INVALID_LDB_CREDIT_LOW_WATERMARK", 102 "DLB_ST_INVALID_LDB_CREDIT_QUANTUM", 103 "DLB_ST_INVALID_DIR_CREDIT_LOW_WATERMARK", 104 "DLB_ST_INVALID_DIR_CREDIT_QUANTUM", 105 "DLB_ST_DOMAIN_NOT_CONFIGURED", 106 "DLB_ST_PID_ALREADY_ATTACHED", 107 "DLB_ST_PID_NOT_ATTACHED", 108 "DLB_ST_INTERNAL_ERROR", 109 "DLB_ST_DOMAIN_IN_USE", 110 "DLB_ST_IOMMU_MAPPING_ERROR", 111 "DLB_ST_FAIL_TO_PIN_MEMORY_PAGE", 112 "DLB_ST_UNABLE_TO_PIN_POPCOUNT_PAGES", 113 "DLB_ST_UNABLE_TO_PIN_CQ_PAGES", 114 "DLB_ST_DISCONTIGUOUS_CQ_MEMORY", 115 "DLB_ST_DISCONTIGUOUS_POP_COUNT_MEMORY", 116 "DLB_ST_DOMAIN_STARTED", 117 "DLB_ST_LARGE_POOL_NOT_SPECIFIED", 118 "DLB_ST_SMALL_POOL_NOT_SPECIFIED", 119 "DLB_ST_NEITHER_POOL_SPECIFIED", 120 "DLB_ST_DOMAIN_NOT_STARTED", 121 "DLB_ST_INVALID_MEASUREMENT_DURATION", 122 "DLB_ST_INVALID_PERF_METRIC_GROUP_ID", 123 "DLB_ST_LDB_PORT_REQUIRED_FOR_LDB_QUEUES", 124 "DLB_ST_DOMAIN_RESET_FAILED", 125 "DLB_ST_MBOX_ERROR", 126 "DLB_ST_INVALID_HIST_LIST_DEPTH", 127 "DLB_ST_NO_MEMORY", 128 }; 129 130 struct dlb_cmd_response { 131 __u32 status; /* Interpret using enum dlb_error */ 132 __u32 id; 133 }; 134 135 /******************************/ 136 /* 'dlb' commands */ 137 /******************************/ 138 139 #define DLB_DEVICE_VERSION(x) (((x) >> 8) & 0xFF) 140 #define DLB_DEVICE_REVISION(x) ((x) & 0xFF) 141 142 enum dlb_revisions { 143 DLB_REV_A0 = 0, 144 DLB_REV_A1 = 1, 145 DLB_REV_A2 = 2, 146 DLB_REV_A3 = 3, 147 DLB_REV_B0 = 4, 148 }; 149 150 /* 151 * DLB_CMD_CREATE_SCHED_DOMAIN: Create a DLB scheduling domain and reserve the 152 * resources (queues, ports, etc.) that it contains. 153 * 154 * Input parameters: 155 * - num_ldb_queues: Number of load-balanced queues. 156 * - num_ldb_ports: Number of load-balanced ports. 157 * - num_dir_ports: Number of directed ports. A directed port has one directed 158 * queue, so no num_dir_queues argument is necessary. 159 * - num_atomic_inflights: This specifies the amount of temporary atomic QE 160 * storage for the domain. This storage is divided among the domain's 161 * load-balanced queues that are configured for atomic scheduling. 162 * - num_hist_list_entries: Amount of history list storage. This is divided 163 * among the domain's CQs. 164 * - num_ldb_credits: Amount of load-balanced QE storage (QED). QEs occupy this 165 * space until they are scheduled to a load-balanced CQ. One credit 166 * represents the storage for one QE. 167 * - num_dir_credits: Amount of directed QE storage (DQED). QEs occupy this 168 * space until they are scheduled to a directed CQ. One credit represents 169 * the storage for one QE. 170 * - num_ldb_credit_pools: Number of pools into which the load-balanced credits 171 * are placed. 172 * - num_dir_credit_pools: Number of pools into which the directed credits are 173 * placed. 174 * - padding0: Reserved for future use. 175 * 176 * Output parameters: 177 * - response: pointer to a struct dlb_cmd_response. 178 * response.status: Detailed error code. In certain cases, such as if the 179 * response pointer is invalid, the driver won't set status. 180 * response.id: domain ID. 181 */ 182 struct dlb_create_sched_domain_args { 183 /* Output parameters */ 184 __u64 response; 185 /* Input parameters */ 186 __u32 num_ldb_queues; 187 __u32 num_ldb_ports; 188 __u32 num_dir_ports; 189 __u32 num_atomic_inflights; 190 __u32 num_hist_list_entries; 191 __u32 num_ldb_credits; 192 __u32 num_dir_credits; 193 __u32 num_ldb_credit_pools; 194 __u32 num_dir_credit_pools; 195 }; 196 197 /* 198 * DLB_CMD_GET_NUM_RESOURCES: Return the number of available resources 199 * (queues, ports, etc.) that this device owns. 200 * 201 * Output parameters: 202 * - num_domains: Number of available scheduling domains. 203 * - num_ldb_queues: Number of available load-balanced queues. 204 * - num_ldb_ports: Number of available load-balanced ports. 205 * - num_dir_ports: Number of available directed ports. There is one directed 206 * queue for every directed port. 207 * - num_atomic_inflights: Amount of available temporary atomic QE storage. 208 * - max_contiguous_atomic_inflights: When a domain is created, the temporary 209 * atomic QE storage is allocated in a contiguous chunk. This return value 210 * is the longest available contiguous range of atomic QE storage. 211 * - num_hist_list_entries: Amount of history list storage. 212 * - max_contiguous_hist_list_entries: History list storage is allocated in 213 * a contiguous chunk, and this return value is the longest available 214 * contiguous range of history list entries. 215 * - num_ldb_credits: Amount of available load-balanced QE storage. 216 * - max_contiguous_ldb_credits: QED storage is allocated in a contiguous 217 * chunk, and this return value is the longest available contiguous range 218 * of load-balanced credit storage. 219 * - num_dir_credits: Amount of available directed QE storage. 220 * - max_contiguous_dir_credits: DQED storage is allocated in a contiguous 221 * chunk, and this return value is the longest available contiguous range 222 * of directed credit storage. 223 * - num_ldb_credit_pools: Number of available load-balanced credit pools. 224 * - num_dir_credit_pools: Number of available directed credit pools. 225 * - padding0: Reserved for future use. 226 */ 227 struct dlb_get_num_resources_args { 228 /* Output parameters */ 229 __u32 num_sched_domains; 230 __u32 num_ldb_queues; 231 __u32 num_ldb_ports; 232 __u32 num_dir_ports; 233 __u32 num_atomic_inflights; 234 __u32 max_contiguous_atomic_inflights; 235 __u32 num_hist_list_entries; 236 __u32 max_contiguous_hist_list_entries; 237 __u32 num_ldb_credits; 238 __u32 max_contiguous_ldb_credits; 239 __u32 num_dir_credits; 240 __u32 max_contiguous_dir_credits; 241 __u32 num_ldb_credit_pools; 242 __u32 num_dir_credit_pools; 243 __u32 padding0; 244 }; 245 246 /* 247 * DLB_CMD_SET_SN_ALLOCATION: Configure a sequence number group 248 * 249 * Input parameters: 250 * - group: Sequence number group ID. 251 * - num: Number of sequence numbers per queue. 252 * 253 * Output parameters: 254 * - response: pointer to a struct dlb_cmd_response. 255 * response.status: Detailed error code. In certain cases, such as if the 256 * response pointer is invalid, the driver won't set status. 257 */ 258 struct dlb_set_sn_allocation_args { 259 /* Output parameters */ 260 __u64 response; 261 /* Input parameters */ 262 __u32 group; 263 __u32 num; 264 }; 265 266 /* 267 * DLB_CMD_GET_SN_ALLOCATION: Get a sequence number group's configuration 268 * 269 * Input parameters: 270 * - group: Sequence number group ID. 271 * - padding0: Reserved for future use. 272 * 273 * Output parameters: 274 * - response: pointer to a struct dlb_cmd_response. 275 * response.status: Detailed error code. In certain cases, such as if the 276 * response pointer is invalid, the driver won't set status. 277 * response.id: Specified group's number of sequence numbers per queue. 278 */ 279 struct dlb_get_sn_allocation_args { 280 /* Output parameters */ 281 __u64 response; 282 /* Input parameters */ 283 __u32 group; 284 __u32 padding0; 285 }; 286 287 enum dlb_cq_poll_modes { 288 DLB_CQ_POLL_MODE_STD, 289 DLB_CQ_POLL_MODE_SPARSE, 290 291 /* NUM_DLB_CQ_POLL_MODE must be last */ 292 NUM_DLB_CQ_POLL_MODE, 293 }; 294 295 /* 296 * DLB_CMD_QUERY_CQ_POLL_MODE: Query the CQ poll mode the kernel driver is using 297 * 298 * Output parameters: 299 * - response: pointer to a struct dlb_cmd_response. 300 * response.status: Detailed error code. In certain cases, such as if the 301 * response pointer is invalid, the driver won't set status. 302 * response.id: CQ poll mode (see enum dlb_cq_poll_modes). 303 */ 304 struct dlb_query_cq_poll_mode_args { 305 /* Output parameters */ 306 __u64 response; 307 }; 308 309 /* 310 * DLB_CMD_GET_SN_OCCUPANCY: Get a sequence number group's occupancy 311 * 312 * Each sequence number group has one or more slots, depending on its 313 * configuration. I.e.: 314 * - If configured for 1024 sequence numbers per queue, the group has 1 slot 315 * - If configured for 512 sequence numbers per queue, the group has 2 slots 316 * ... 317 * - If configured for 32 sequence numbers per queue, the group has 32 slots 318 * 319 * This ioctl returns the group's number of in-use slots. If its occupancy is 320 * 0, the group's sequence number allocation can be reconfigured. 321 * 322 * Input parameters: 323 * - group: Sequence number group ID. 324 * - padding0: Reserved for future use. 325 * 326 * Output parameters: 327 * - response: pointer to a struct dlb_cmd_response. 328 * response.status: Detailed error code. In certain cases, such as if the 329 * response pointer is invalid, the driver won't set status. 330 * response.id: Specified group's number of used slots. 331 */ 332 struct dlb_get_sn_occupancy_args { 333 /* Output parameters */ 334 __u64 response; 335 /* Input parameters */ 336 __u32 group; 337 __u32 padding0; 338 }; 339 340 /*********************************/ 341 /* 'scheduling domain' commands */ 342 /*********************************/ 343 344 /* 345 * DLB_DOMAIN_CMD_CREATE_LDB_POOL: Configure a load-balanced credit pool. 346 * Input parameters: 347 * - num_ldb_credits: Number of load-balanced credits (QED space) for this 348 * pool. 349 * - padding0: Reserved for future use. 350 * 351 * Output parameters: 352 * - response: pointer to a struct dlb_cmd_response. 353 * response.status: Detailed error code. In certain cases, such as if the 354 * response pointer is invalid, the driver won't set status. 355 * response.id: pool ID. 356 */ 357 struct dlb_create_ldb_pool_args { 358 /* Output parameters */ 359 __u64 response; 360 /* Input parameters */ 361 __u32 num_ldb_credits; 362 __u32 padding0; 363 }; 364 365 /* 366 * DLB_DOMAIN_CMD_CREATE_DIR_POOL: Configure a directed credit pool. 367 * Input parameters: 368 * - num_dir_credits: Number of directed credits (DQED space) for this pool. 369 * - padding0: Reserved for future use. 370 * 371 * Output parameters: 372 * - response: pointer to a struct dlb_cmd_response. 373 * response.status: Detailed error code. In certain cases, such as if the 374 * response pointer is invalid, the driver won't set status. 375 * response.id: Pool ID. 376 */ 377 struct dlb_create_dir_pool_args { 378 /* Output parameters */ 379 __u64 response; 380 /* Input parameters */ 381 __u32 num_dir_credits; 382 __u32 padding0; 383 }; 384 385 /* 386 * DLB_DOMAIN_CMD_CREATE_LDB_QUEUE: Configure a load-balanced queue. 387 * Input parameters: 388 * - num_atomic_inflights: This specifies the amount of temporary atomic QE 389 * storage for this queue. If zero, the queue will not support atomic 390 * scheduling. 391 * - num_sequence_numbers: This specifies the number of sequence numbers used 392 * by this queue. If zero, the queue will not support ordered scheduling. 393 * If non-zero, the queue will not support unordered scheduling. 394 * - num_qid_inflights: The maximum number of QEs that can be inflight 395 * (scheduled to a CQ but not completed) at any time. If 396 * num_sequence_numbers is non-zero, num_qid_inflights must be set equal 397 * to num_sequence_numbers. 398 * - padding0: Reserved for future use. 399 * 400 * Output parameters: 401 * - response: pointer to a struct dlb_cmd_response. 402 * response.status: Detailed error code. In certain cases, such as if the 403 * response pointer is invalid, the driver won't set status. 404 * response.id: Queue ID. 405 */ 406 struct dlb_create_ldb_queue_args { 407 /* Output parameters */ 408 __u64 response; 409 /* Input parameters */ 410 __u32 num_sequence_numbers; 411 __u32 num_qid_inflights; 412 __u32 num_atomic_inflights; 413 __u32 padding0; 414 }; 415 416 /* 417 * DLB_DOMAIN_CMD_CREATE_DIR_QUEUE: Configure a directed queue. 418 * Input parameters: 419 * - port_id: Port ID. If the corresponding directed port is already created, 420 * specify its ID here. Else this argument must be 0xFFFFFFFF to indicate 421 * that the queue is being created before the port. 422 * - padding0: Reserved for future use. 423 * 424 * Output parameters: 425 * - response: pointer to a struct dlb_cmd_response. 426 * response.status: Detailed error code. In certain cases, such as if the 427 * response pointer is invalid, the driver won't set status. 428 * response.id: Queue ID. 429 */ 430 struct dlb_create_dir_queue_args { 431 /* Output parameters */ 432 __u64 response; 433 /* Input parameters */ 434 __s32 port_id; 435 __u32 padding0; 436 }; 437 438 /* 439 * DLB_DOMAIN_CMD_CREATE_LDB_PORT: Configure a load-balanced port. 440 * Input parameters: 441 * - ldb_credit_pool_id: Load-balanced credit pool this port will belong to. 442 * - dir_credit_pool_id: Directed credit pool this port will belong to. 443 * - ldb_credit_high_watermark: Number of load-balanced credits from the pool 444 * that this port will own. 445 * 446 * If this port's scheduling domain does not have any load-balanced queues, 447 * this argument is ignored and the port is given no load-balanced 448 * credits. 449 * - dir_credit_high_watermark: Number of directed credits from the pool that 450 * this port will own. 451 * 452 * If this port's scheduling domain does not have any directed queues, 453 * this argument is ignored and the port is given no directed credits. 454 * - ldb_credit_low_watermark: Load-balanced credit low watermark. When the 455 * port's credits reach this watermark, they become eligible to be 456 * refilled by the DLB as credits until the high watermark 457 * (num_ldb_credits) is reached. 458 * 459 * If this port's scheduling domain does not have any load-balanced queues, 460 * this argument is ignored and the port is given no load-balanced 461 * credits. 462 * - dir_credit_low_watermark: Directed credit low watermark. When the port's 463 * credits reach this watermark, they become eligible to be refilled by 464 * the DLB as credits until the high watermark (num_dir_credits) is 465 * reached. 466 * 467 * If this port's scheduling domain does not have any directed queues, 468 * this argument is ignored and the port is given no directed credits. 469 * - ldb_credit_quantum: Number of load-balanced credits for the DLB to refill 470 * per refill operation. 471 * 472 * If this port's scheduling domain does not have any load-balanced queues, 473 * this argument is ignored and the port is given no load-balanced 474 * credits. 475 * - dir_credit_quantum: Number of directed credits for the DLB to refill per 476 * refill operation. 477 * 478 * If this port's scheduling domain does not have any directed queues, 479 * this argument is ignored and the port is given no directed credits. 480 * - padding0: Reserved for future use. 481 * - cq_depth: Depth of the port's CQ. Must be a power-of-two between 8 and 482 * 1024, inclusive. 483 * - cq_depth_threshold: CQ depth interrupt threshold. A value of N means that 484 * the CQ interrupt won't fire until there are N or more outstanding CQ 485 * tokens. 486 * - cq_history_list_size: Number of history list entries. This must be greater 487 * than or equal to cq_depth. 488 * - padding1: Reserved for future use. 489 * - padding2: Reserved for future use. 490 * 491 * Output parameters: 492 * - response: pointer to a struct dlb_cmd_response. 493 * response.status: Detailed error code. In certain cases, such as if the 494 * response pointer is invalid, the driver won't set status. 495 * response.id: port ID. 496 */ 497 struct dlb_create_ldb_port_args { 498 /* Output parameters */ 499 __u64 response; 500 /* Input parameters */ 501 __u32 ldb_credit_pool_id; 502 __u32 dir_credit_pool_id; 503 __u16 ldb_credit_high_watermark; 504 __u16 ldb_credit_low_watermark; 505 __u16 ldb_credit_quantum; 506 __u16 dir_credit_high_watermark; 507 __u16 dir_credit_low_watermark; 508 __u16 dir_credit_quantum; 509 __u16 padding0; 510 __u16 cq_depth; 511 __u16 cq_depth_threshold; 512 __u16 cq_history_list_size; 513 __u32 padding1; 514 }; 515 516 /* 517 * DLB_DOMAIN_CMD_CREATE_DIR_PORT: Configure a directed port. 518 * Input parameters: 519 * - ldb_credit_pool_id: Load-balanced credit pool this port will belong to. 520 * - dir_credit_pool_id: Directed credit pool this port will belong to. 521 * - ldb_credit_high_watermark: Number of load-balanced credits from the pool 522 * that this port will own. 523 * 524 * If this port's scheduling domain does not have any load-balanced queues, 525 * this argument is ignored and the port is given no load-balanced 526 * credits. 527 * - dir_credit_high_watermark: Number of directed credits from the pool that 528 * this port will own. 529 * - ldb_credit_low_watermark: Load-balanced credit low watermark. When the 530 * port's credits reach this watermark, they become eligible to be 531 * refilled by the DLB as credits until the high watermark 532 * (num_ldb_credits) is reached. 533 * 534 * If this port's scheduling domain does not have any load-balanced queues, 535 * this argument is ignored and the port is given no load-balanced 536 * credits. 537 * - dir_credit_low_watermark: Directed credit low watermark. When the port's 538 * credits reach this watermark, they become eligible to be refilled by 539 * the DLB as credits until the high watermark (num_dir_credits) is 540 * reached. 541 * - ldb_credit_quantum: Number of load-balanced credits for the DLB to refill 542 * per refill operation. 543 * 544 * If this port's scheduling domain does not have any load-balanced queues, 545 * this argument is ignored and the port is given no load-balanced 546 * credits. 547 * - dir_credit_quantum: Number of directed credits for the DLB to refill per 548 * refill operation. 549 * - cq_depth: Depth of the port's CQ. Must be a power-of-two between 8 and 550 * 1024, inclusive. 551 * - cq_depth_threshold: CQ depth interrupt threshold. A value of N means that 552 * the CQ interrupt won't fire until there are N or more outstanding CQ 553 * tokens. 554 * - qid: Queue ID. If the corresponding directed queue is already created, 555 * specify its ID here. Else this argument must be 0xFFFFFFFF to indicate 556 * that the port is being created before the queue. 557 * - padding1: Reserved for future use. 558 * 559 * Output parameters: 560 * - response: pointer to a struct dlb_cmd_response. 561 * response.status: Detailed error code. In certain cases, such as if the 562 * response pointer is invalid, the driver won't set status. 563 * response.id: Port ID. 564 */ 565 struct dlb_create_dir_port_args { 566 /* Output parameters */ 567 __u64 response; 568 /* Input parameters */ 569 __u32 ldb_credit_pool_id; 570 __u32 dir_credit_pool_id; 571 __u16 ldb_credit_high_watermark; 572 __u16 ldb_credit_low_watermark; 573 __u16 ldb_credit_quantum; 574 __u16 dir_credit_high_watermark; 575 __u16 dir_credit_low_watermark; 576 __u16 dir_credit_quantum; 577 __u16 cq_depth; 578 __u16 cq_depth_threshold; 579 __s32 queue_id; 580 __u32 padding1; 581 }; 582 583 /* 584 * DLB_DOMAIN_CMD_START_DOMAIN: Mark the end of the domain configuration. This 585 * must be called before passing QEs into the device, and no configuration 586 * ioctls can be issued once the domain has started. Sending QEs into the 587 * device before calling this ioctl will result in undefined behavior. 588 * Input parameters: 589 * - (None) 590 * 591 * Output parameters: 592 * - response: pointer to a struct dlb_cmd_response. 593 * response.status: Detailed error code. In certain cases, such as if the 594 * response pointer is invalid, the driver won't set status. 595 */ 596 struct dlb_start_domain_args { 597 /* Output parameters */ 598 __u64 response; 599 /* Input parameters */ 600 }; 601 602 /* 603 * DLB_DOMAIN_CMD_MAP_QID: Map a load-balanced queue to a load-balanced port. 604 * Input parameters: 605 * - port_id: Load-balanced port ID. 606 * - qid: Load-balanced queue ID. 607 * - priority: Queue->port service priority. 608 * - padding0: Reserved for future use. 609 * 610 * Output parameters: 611 * - response: pointer to a struct dlb_cmd_response. 612 * response.status: Detailed error code. In certain cases, such as if the 613 * response pointer is invalid, the driver won't set status. 614 */ 615 struct dlb_map_qid_args { 616 /* Output parameters */ 617 __u64 response; 618 /* Input parameters */ 619 __u32 port_id; 620 __u32 qid; 621 __u32 priority; 622 __u32 padding0; 623 }; 624 625 /* 626 * DLB_DOMAIN_CMD_UNMAP_QID: Unmap a load-balanced queue to a load-balanced 627 * port. 628 * Input parameters: 629 * - port_id: Load-balanced port ID. 630 * - qid: Load-balanced queue ID. 631 * 632 * Output parameters: 633 * - response: pointer to a struct dlb_cmd_response. 634 * response.status: Detailed error code. In certain cases, such as if the 635 * response pointer is invalid, the driver won't set status. 636 */ 637 struct dlb_unmap_qid_args { 638 /* Output parameters */ 639 __u64 response; 640 /* Input parameters */ 641 __u32 port_id; 642 __u32 qid; 643 }; 644 645 /* 646 * DLB_DOMAIN_CMD_ENABLE_LDB_PORT: Enable scheduling to a load-balanced port. 647 * Input parameters: 648 * - port_id: Load-balanced port ID. 649 * - padding0: Reserved for future use. 650 * 651 * Output parameters: 652 * - response: pointer to a struct dlb_cmd_response. 653 * response.status: Detailed error code. In certain cases, such as if the 654 * response pointer is invalid, the driver won't set status. 655 */ 656 struct dlb_enable_ldb_port_args { 657 /* Output parameters */ 658 __u64 response; 659 /* Input parameters */ 660 __u32 port_id; 661 __u32 padding0; 662 }; 663 664 /* 665 * DLB_DOMAIN_CMD_ENABLE_DIR_PORT: Enable scheduling to a directed port. 666 * Input parameters: 667 * - port_id: Directed port ID. 668 * - padding0: Reserved for future use. 669 * 670 * Output parameters: 671 * - response: pointer to a struct dlb_cmd_response. 672 * response.status: Detailed error code. In certain cases, such as if the 673 * response pointer is invalid, the driver won't set status. 674 */ 675 struct dlb_enable_dir_port_args { 676 /* Output parameters */ 677 __u64 response; 678 /* Input parameters */ 679 __u32 port_id; 680 }; 681 682 /* 683 * DLB_DOMAIN_CMD_DISABLE_LDB_PORT: Disable scheduling to a load-balanced port. 684 * Input parameters: 685 * - port_id: Load-balanced port ID. 686 * - padding0: Reserved for future use. 687 * 688 * Output parameters: 689 * - response: pointer to a struct dlb_cmd_response. 690 * response.status: Detailed error code. In certain cases, such as if the 691 * response pointer is invalid, the driver won't set status. 692 */ 693 struct dlb_disable_ldb_port_args { 694 /* Output parameters */ 695 __u64 response; 696 /* Input parameters */ 697 __u32 port_id; 698 __u32 padding0; 699 }; 700 701 /* 702 * DLB_DOMAIN_CMD_DISABLE_DIR_PORT: Disable scheduling to a directed port. 703 * Input parameters: 704 * - port_id: Directed port ID. 705 * - padding0: Reserved for future use. 706 * 707 * Output parameters: 708 * - response: pointer to a struct dlb_cmd_response. 709 * response.status: Detailed error code. In certain cases, such as if the 710 * response pointer is invalid, the driver won't set status. 711 */ 712 struct dlb_disable_dir_port_args { 713 /* Output parameters */ 714 __u64 response; 715 /* Input parameters */ 716 __u32 port_id; 717 __u32 padding0; 718 }; 719 720 /* 721 * DLB_DOMAIN_CMD_GET_LDB_QUEUE_DEPTH: Get a load-balanced queue's depth. 722 * Input parameters: 723 * - queue_id: The load-balanced queue ID. 724 * - padding0: Reserved for future use. 725 * 726 * Output parameters: 727 * - response: pointer to a struct dlb_cmd_response. 728 * response.status: Detailed error code. In certain cases, such as if the 729 * response pointer is invalid, the driver won't set status. 730 * response.id: queue depth. 731 */ 732 struct dlb_get_ldb_queue_depth_args { 733 /* Output parameters */ 734 __u64 response; 735 /* Input parameters */ 736 __u32 queue_id; 737 __u32 padding0; 738 }; 739 740 /* 741 * DLB_DOMAIN_CMD_GET_DIR_QUEUE_DEPTH: Get a directed queue's depth. 742 * Input parameters: 743 * - queue_id: The directed queue ID. 744 * - padding0: Reserved for future use. 745 * 746 * Output parameters: 747 * - response: pointer to a struct dlb_cmd_response. 748 * response.status: Detailed error code. In certain cases, such as if the 749 * response pointer is invalid, the driver won't set status. 750 * response.id: queue depth. 751 */ 752 struct dlb_get_dir_queue_depth_args { 753 /* Output parameters */ 754 __u64 response; 755 /* Input parameters */ 756 __u32 queue_id; 757 __u32 padding0; 758 }; 759 760 /* 761 * DLB_DOMAIN_CMD_PENDING_PORT_UNMAPS: Get number of queue unmap operations in 762 * progress for a load-balanced port. 763 * 764 * Note: This is a snapshot; the number of unmap operations in progress 765 * is subject to change at any time. 766 * 767 * Input parameters: 768 * - port_id: Load-balanced port ID. 769 * 770 * Output parameters: 771 * - response: pointer to a struct dlb_cmd_response. 772 * response.status: Detailed error code. In certain cases, such as if the 773 * response pointer is invalid, the driver won't set status. 774 * response.id: number of unmaps in progress. 775 */ 776 struct dlb_pending_port_unmaps_args { 777 /* Output parameters */ 778 __u64 response; 779 /* Input parameters */ 780 __u32 port_id; 781 __u32 padding0; 782 }; 783 784 /* 785 * Base addresses for memory mapping the consumer queue (CQ) and popcount (PC) 786 * memory space, and producer port (PP) MMIO space. The CQ, PC, and PP 787 * addresses are per-port. Every address is page-separated (e.g. LDB PP 0 is at 788 * 0x2100000 and LDB PP 1 is at 0x2101000). 789 */ 790 #define DLB_LDB_CQ_BASE 0x3000000 791 #define DLB_LDB_CQ_MAX_SIZE 65536 792 #define DLB_LDB_CQ_OFFS(id) (DLB_LDB_CQ_BASE + (id) * DLB_LDB_CQ_MAX_SIZE) 793 794 #define DLB_DIR_CQ_BASE 0x3800000 795 #define DLB_DIR_CQ_MAX_SIZE 65536 796 #define DLB_DIR_CQ_OFFS(id) (DLB_DIR_CQ_BASE + (id) * DLB_DIR_CQ_MAX_SIZE) 797 798 #define DLB_LDB_PC_BASE 0x2300000 799 #define DLB_LDB_PC_MAX_SIZE 4096 800 #define DLB_LDB_PC_OFFS(id) (DLB_LDB_PC_BASE + (id) * DLB_LDB_PC_MAX_SIZE) 801 802 #define DLB_DIR_PC_BASE 0x2200000 803 #define DLB_DIR_PC_MAX_SIZE 4096 804 #define DLB_DIR_PC_OFFS(id) (DLB_DIR_PC_BASE + (id) * DLB_DIR_PC_MAX_SIZE) 805 806 #define DLB_LDB_PP_BASE 0x2100000 807 #define DLB_LDB_PP_MAX_SIZE 4096 808 #define DLB_LDB_PP_OFFS(id) (DLB_LDB_PP_BASE + (id) * DLB_LDB_PP_MAX_SIZE) 809 810 #define DLB_DIR_PP_BASE 0x2000000 811 #define DLB_DIR_PP_MAX_SIZE 4096 812 #define DLB_DIR_PP_OFFS(id) (DLB_DIR_PP_BASE + (id) * DLB_DIR_PP_MAX_SIZE) 813 814 #endif /* __DLB_USER_H */ 815