xref: /f-stack/dpdk/drivers/event/dlb2/pf/base/dlb2_mbox.h (revision 2d9fd380)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2016-2020 Intel Corporation
3  */
4 
5 #ifndef __DLB2_BASE_DLB2_MBOX_H
6 #define __DLB2_BASE_DLB2_MBOX_H
7 
8 #include "dlb2_osdep_types.h"
9 #include "dlb2_regs.h"
10 
11 #define DLB2_MBOX_INTERFACE_VERSION 1
12 
13 /*
14  * The PF uses its PF->VF mailbox to send responses to VF requests, as well as
15  * to send requests of its own (e.g. notifying a VF of an impending FLR).
16  * To avoid communication race conditions, e.g. the PF sends a response and then
17  * sends a request before the VF reads the response, the PF->VF mailbox is
18  * divided into two sections:
19  * - Bytes 0-47: PF responses
20  * - Bytes 48-63: PF requests
21  *
22  * Partitioning the PF->VF mailbox allows responses and requests to occupy the
23  * mailbox simultaneously.
24  */
25 #define DLB2_PF2VF_RESP_BYTES	  48
26 #define DLB2_PF2VF_RESP_BASE	  0
27 #define DLB2_PF2VF_RESP_BASE_WORD (DLB2_PF2VF_RESP_BASE / 4)
28 
29 #define DLB2_PF2VF_REQ_BYTES	  16
30 #define DLB2_PF2VF_REQ_BASE	  (DLB2_PF2VF_RESP_BASE + DLB2_PF2VF_RESP_BYTES)
31 #define DLB2_PF2VF_REQ_BASE_WORD  (DLB2_PF2VF_REQ_BASE / 4)
32 
33 /*
34  * Similarly, the VF->PF mailbox is divided into two sections:
35  * - Bytes 0-239: VF requests
36  * -- (Bytes 0-3 are unused due to a hardware errata)
37  * - Bytes 240-255: VF responses
38  */
39 #define DLB2_VF2PF_REQ_BYTES	 236
40 #define DLB2_VF2PF_REQ_BASE	 4
41 #define DLB2_VF2PF_REQ_BASE_WORD (DLB2_VF2PF_REQ_BASE / 4)
42 
43 #define DLB2_VF2PF_RESP_BYTES	  16
44 #define DLB2_VF2PF_RESP_BASE	  (DLB2_VF2PF_REQ_BASE + DLB2_VF2PF_REQ_BYTES)
45 #define DLB2_VF2PF_RESP_BASE_WORD (DLB2_VF2PF_RESP_BASE / 4)
46 
47 /* VF-initiated commands */
48 enum dlb2_mbox_cmd_type {
49 	DLB2_MBOX_CMD_REGISTER,
50 	DLB2_MBOX_CMD_UNREGISTER,
51 	DLB2_MBOX_CMD_GET_NUM_RESOURCES,
52 	DLB2_MBOX_CMD_CREATE_SCHED_DOMAIN,
53 	DLB2_MBOX_CMD_RESET_SCHED_DOMAIN,
54 	DLB2_MBOX_CMD_CREATE_LDB_QUEUE,
55 	DLB2_MBOX_CMD_CREATE_DIR_QUEUE,
56 	DLB2_MBOX_CMD_CREATE_LDB_PORT,
57 	DLB2_MBOX_CMD_CREATE_DIR_PORT,
58 	DLB2_MBOX_CMD_ENABLE_LDB_PORT,
59 	DLB2_MBOX_CMD_DISABLE_LDB_PORT,
60 	DLB2_MBOX_CMD_ENABLE_DIR_PORT,
61 	DLB2_MBOX_CMD_DISABLE_DIR_PORT,
62 	DLB2_MBOX_CMD_LDB_PORT_OWNED_BY_DOMAIN,
63 	DLB2_MBOX_CMD_DIR_PORT_OWNED_BY_DOMAIN,
64 	DLB2_MBOX_CMD_MAP_QID,
65 	DLB2_MBOX_CMD_UNMAP_QID,
66 	DLB2_MBOX_CMD_START_DOMAIN,
67 	DLB2_MBOX_CMD_ENABLE_LDB_PORT_INTR,
68 	DLB2_MBOX_CMD_ENABLE_DIR_PORT_INTR,
69 	DLB2_MBOX_CMD_ARM_CQ_INTR,
70 	DLB2_MBOX_CMD_GET_NUM_USED_RESOURCES,
71 	DLB2_MBOX_CMD_GET_SN_ALLOCATION,
72 	DLB2_MBOX_CMD_GET_LDB_QUEUE_DEPTH,
73 	DLB2_MBOX_CMD_GET_DIR_QUEUE_DEPTH,
74 	DLB2_MBOX_CMD_PENDING_PORT_UNMAPS,
75 	DLB2_MBOX_CMD_GET_COS_BW,
76 	DLB2_MBOX_CMD_GET_SN_OCCUPANCY,
77 	DLB2_MBOX_CMD_QUERY_CQ_POLL_MODE,
78 
79 	/* NUM_QE_CMD_TYPES must be last */
80 	NUM_DLB2_MBOX_CMD_TYPES,
81 };
82 
83 static const char dlb2_mbox_cmd_type_strings[][128] = {
84 	"DLB2_MBOX_CMD_REGISTER",
85 	"DLB2_MBOX_CMD_UNREGISTER",
86 	"DLB2_MBOX_CMD_GET_NUM_RESOURCES",
87 	"DLB2_MBOX_CMD_CREATE_SCHED_DOMAIN",
88 	"DLB2_MBOX_CMD_RESET_SCHED_DOMAIN",
89 	"DLB2_MBOX_CMD_CREATE_LDB_QUEUE",
90 	"DLB2_MBOX_CMD_CREATE_DIR_QUEUE",
91 	"DLB2_MBOX_CMD_CREATE_LDB_PORT",
92 	"DLB2_MBOX_CMD_CREATE_DIR_PORT",
93 	"DLB2_MBOX_CMD_ENABLE_LDB_PORT",
94 	"DLB2_MBOX_CMD_DISABLE_LDB_PORT",
95 	"DLB2_MBOX_CMD_ENABLE_DIR_PORT",
96 	"DLB2_MBOX_CMD_DISABLE_DIR_PORT",
97 	"DLB2_MBOX_CMD_LDB_PORT_OWNED_BY_DOMAIN",
98 	"DLB2_MBOX_CMD_DIR_PORT_OWNED_BY_DOMAIN",
99 	"DLB2_MBOX_CMD_MAP_QID",
100 	"DLB2_MBOX_CMD_UNMAP_QID",
101 	"DLB2_MBOX_CMD_START_DOMAIN",
102 	"DLB2_MBOX_CMD_ENABLE_LDB_PORT_INTR",
103 	"DLB2_MBOX_CMD_ENABLE_DIR_PORT_INTR",
104 	"DLB2_MBOX_CMD_ARM_CQ_INTR",
105 	"DLB2_MBOX_CMD_GET_NUM_USED_RESOURCES",
106 	"DLB2_MBOX_CMD_GET_SN_ALLOCATION",
107 	"DLB2_MBOX_CMD_GET_LDB_QUEUE_DEPTH",
108 	"DLB2_MBOX_CMD_GET_DIR_QUEUE_DEPTH",
109 	"DLB2_MBOX_CMD_PENDING_PORT_UNMAPS",
110 	"DLB2_MBOX_CMD_GET_COS_BW",
111 	"DLB2_MBOX_CMD_GET_SN_OCCUPANCY",
112 	"DLB2_MBOX_CMD_QUERY_CQ_POLL_MODE",
113 };
114 
115 /* PF-initiated commands */
116 enum dlb2_mbox_vf_cmd_type {
117 	DLB2_MBOX_VF_CMD_DOMAIN_ALERT,
118 	DLB2_MBOX_VF_CMD_NOTIFICATION,
119 	DLB2_MBOX_VF_CMD_IN_USE,
120 
121 	/* NUM_DLB2_MBOX_VF_CMD_TYPES must be last */
122 	NUM_DLB2_MBOX_VF_CMD_TYPES,
123 };
124 
125 static const char dlb2_mbox_vf_cmd_type_strings[][128] = {
126 	"DLB2_MBOX_VF_CMD_DOMAIN_ALERT",
127 	"DLB2_MBOX_VF_CMD_NOTIFICATION",
128 	"DLB2_MBOX_VF_CMD_IN_USE",
129 };
130 
131 #define DLB2_MBOX_CMD_TYPE(hdr) \
132 	(((struct dlb2_mbox_req_hdr *)hdr)->type)
133 #define DLB2_MBOX_CMD_STRING(hdr) \
134 	dlb2_mbox_cmd_type_strings[DLB2_MBOX_CMD_TYPE(hdr)]
135 
136 enum dlb2_mbox_status_type {
137 	DLB2_MBOX_ST_SUCCESS,
138 	DLB2_MBOX_ST_INVALID_CMD_TYPE,
139 	DLB2_MBOX_ST_VERSION_MISMATCH,
140 	DLB2_MBOX_ST_INVALID_OWNER_VF,
141 };
142 
143 static const char dlb2_mbox_status_type_strings[][128] = {
144 	"DLB2_MBOX_ST_SUCCESS",
145 	"DLB2_MBOX_ST_INVALID_CMD_TYPE",
146 	"DLB2_MBOX_ST_VERSION_MISMATCH",
147 	"DLB2_MBOX_ST_INVALID_OWNER_VF",
148 };
149 
150 #define DLB2_MBOX_ST_TYPE(hdr) \
151 	(((struct dlb2_mbox_resp_hdr *)hdr)->status)
152 #define DLB2_MBOX_ST_STRING(hdr) \
153 	dlb2_mbox_status_type_strings[DLB2_MBOX_ST_TYPE(hdr)]
154 
155 /* This structure is always the first field in a request structure */
156 struct dlb2_mbox_req_hdr {
157 	u32 type;
158 };
159 
160 /* This structure is always the first field in a response structure */
161 struct dlb2_mbox_resp_hdr {
162 	u32 status;
163 };
164 
165 struct dlb2_mbox_register_cmd_req {
166 	struct dlb2_mbox_req_hdr hdr;
167 	u16 min_interface_version;
168 	u16 max_interface_version;
169 };
170 
171 struct dlb2_mbox_register_cmd_resp {
172 	struct dlb2_mbox_resp_hdr hdr;
173 	u32 interface_version;
174 	u8 pf_id;
175 	u8 vf_id;
176 	u8 is_auxiliary_vf;
177 	u8 primary_vf_id;
178 	u32 padding;
179 };
180 
181 struct dlb2_mbox_unregister_cmd_req {
182 	struct dlb2_mbox_req_hdr hdr;
183 	u32 padding;
184 };
185 
186 struct dlb2_mbox_unregister_cmd_resp {
187 	struct dlb2_mbox_resp_hdr hdr;
188 	u32 padding;
189 };
190 
191 struct dlb2_mbox_get_num_resources_cmd_req {
192 	struct dlb2_mbox_req_hdr hdr;
193 	u32 padding;
194 };
195 
196 struct dlb2_mbox_get_num_resources_cmd_resp {
197 	struct dlb2_mbox_resp_hdr hdr;
198 	u32 error_code;
199 	u16 num_sched_domains;
200 	u16 num_ldb_queues;
201 	u16 num_ldb_ports;
202 	u16 num_cos_ldb_ports[4];
203 	u16 num_dir_ports;
204 	u32 num_atomic_inflights;
205 	u32 num_hist_list_entries;
206 	u32 max_contiguous_hist_list_entries;
207 	u16 num_ldb_credits;
208 	u16 num_dir_credits;
209 };
210 
211 struct dlb2_mbox_create_sched_domain_cmd_req {
212 	struct dlb2_mbox_req_hdr hdr;
213 	u32 num_ldb_queues;
214 	u32 num_ldb_ports;
215 	u32 num_cos_ldb_ports[4];
216 	u32 num_dir_ports;
217 	u32 num_atomic_inflights;
218 	u32 num_hist_list_entries;
219 	u32 num_ldb_credits;
220 	u32 num_dir_credits;
221 	u8 cos_strict;
222 	u8 padding0[3];
223 	u32 padding1;
224 };
225 
226 struct dlb2_mbox_create_sched_domain_cmd_resp {
227 	struct dlb2_mbox_resp_hdr hdr;
228 	u32 error_code;
229 	u32 status;
230 	u32 id;
231 };
232 
233 struct dlb2_mbox_reset_sched_domain_cmd_req {
234 	struct dlb2_mbox_req_hdr hdr;
235 	u32 id;
236 };
237 
238 struct dlb2_mbox_reset_sched_domain_cmd_resp {
239 	struct dlb2_mbox_resp_hdr hdr;
240 	u32 error_code;
241 };
242 
243 struct dlb2_mbox_create_ldb_queue_cmd_req {
244 	struct dlb2_mbox_req_hdr hdr;
245 	u32 domain_id;
246 	u32 num_sequence_numbers;
247 	u32 num_qid_inflights;
248 	u32 num_atomic_inflights;
249 	u32 lock_id_comp_level;
250 	u32 depth_threshold;
251 	u32 padding;
252 };
253 
254 struct dlb2_mbox_create_ldb_queue_cmd_resp {
255 	struct dlb2_mbox_resp_hdr hdr;
256 	u32 error_code;
257 	u32 status;
258 	u32 id;
259 };
260 
261 struct dlb2_mbox_create_dir_queue_cmd_req {
262 	struct dlb2_mbox_req_hdr hdr;
263 	u32 domain_id;
264 	u32 port_id;
265 	u32 depth_threshold;
266 };
267 
268 struct dlb2_mbox_create_dir_queue_cmd_resp {
269 	struct dlb2_mbox_resp_hdr hdr;
270 	u32 error_code;
271 	u32 status;
272 	u32 id;
273 };
274 
275 struct dlb2_mbox_create_ldb_port_cmd_req {
276 	struct dlb2_mbox_req_hdr hdr;
277 	u32 domain_id;
278 	u16 cq_depth;
279 	u16 cq_history_list_size;
280 	u8 cos_id;
281 	u8 cos_strict;
282 	u16 padding1;
283 	u64 cq_base_address;
284 };
285 
286 struct dlb2_mbox_create_ldb_port_cmd_resp {
287 	struct dlb2_mbox_resp_hdr hdr;
288 	u32 error_code;
289 	u32 status;
290 	u32 id;
291 };
292 
293 struct dlb2_mbox_create_dir_port_cmd_req {
294 	struct dlb2_mbox_req_hdr hdr;
295 	u32 domain_id;
296 	u64 cq_base_address;
297 	u16 cq_depth;
298 	u16 padding0;
299 	s32 queue_id;
300 };
301 
302 struct dlb2_mbox_create_dir_port_cmd_resp {
303 	struct dlb2_mbox_resp_hdr hdr;
304 	u32 error_code;
305 	u32 status;
306 	u32 id;
307 };
308 
309 struct dlb2_mbox_enable_ldb_port_cmd_req {
310 	struct dlb2_mbox_req_hdr hdr;
311 	u32 domain_id;
312 	u32 port_id;
313 	u32 padding;
314 };
315 
316 struct dlb2_mbox_enable_ldb_port_cmd_resp {
317 	struct dlb2_mbox_resp_hdr hdr;
318 	u32 error_code;
319 	u32 status;
320 	u32 padding;
321 };
322 
323 struct dlb2_mbox_disable_ldb_port_cmd_req {
324 	struct dlb2_mbox_req_hdr hdr;
325 	u32 domain_id;
326 	u32 port_id;
327 	u32 padding;
328 };
329 
330 struct dlb2_mbox_disable_ldb_port_cmd_resp {
331 	struct dlb2_mbox_resp_hdr hdr;
332 	u32 error_code;
333 	u32 status;
334 	u32 padding;
335 };
336 
337 struct dlb2_mbox_enable_dir_port_cmd_req {
338 	struct dlb2_mbox_req_hdr hdr;
339 	u32 domain_id;
340 	u32 port_id;
341 	u32 padding;
342 };
343 
344 struct dlb2_mbox_enable_dir_port_cmd_resp {
345 	struct dlb2_mbox_resp_hdr hdr;
346 	u32 error_code;
347 	u32 status;
348 	u32 padding;
349 };
350 
351 struct dlb2_mbox_disable_dir_port_cmd_req {
352 	struct dlb2_mbox_req_hdr hdr;
353 	u32 domain_id;
354 	u32 port_id;
355 	u32 padding;
356 };
357 
358 struct dlb2_mbox_disable_dir_port_cmd_resp {
359 	struct dlb2_mbox_resp_hdr hdr;
360 	u32 error_code;
361 	u32 status;
362 	u32 padding;
363 };
364 
365 struct dlb2_mbox_ldb_port_owned_by_domain_cmd_req {
366 	struct dlb2_mbox_req_hdr hdr;
367 	u32 domain_id;
368 	u32 port_id;
369 	u32 padding;
370 };
371 
372 struct dlb2_mbox_ldb_port_owned_by_domain_cmd_resp {
373 	struct dlb2_mbox_resp_hdr hdr;
374 	s32 owned;
375 };
376 
377 struct dlb2_mbox_dir_port_owned_by_domain_cmd_req {
378 	struct dlb2_mbox_req_hdr hdr;
379 	u32 domain_id;
380 	u32 port_id;
381 	u32 padding;
382 };
383 
384 struct dlb2_mbox_dir_port_owned_by_domain_cmd_resp {
385 	struct dlb2_mbox_resp_hdr hdr;
386 	s32 owned;
387 };
388 
389 struct dlb2_mbox_map_qid_cmd_req {
390 	struct dlb2_mbox_req_hdr hdr;
391 	u32 domain_id;
392 	u32 port_id;
393 	u32 qid;
394 	u32 priority;
395 	u32 padding0;
396 };
397 
398 struct dlb2_mbox_map_qid_cmd_resp {
399 	struct dlb2_mbox_resp_hdr hdr;
400 	u32 error_code;
401 	u32 status;
402 	u32 id;
403 };
404 
405 struct dlb2_mbox_unmap_qid_cmd_req {
406 	struct dlb2_mbox_req_hdr hdr;
407 	u32 domain_id;
408 	u32 port_id;
409 	u32 qid;
410 };
411 
412 struct dlb2_mbox_unmap_qid_cmd_resp {
413 	struct dlb2_mbox_resp_hdr hdr;
414 	u32 error_code;
415 	u32 status;
416 	u32 padding;
417 };
418 
419 struct dlb2_mbox_start_domain_cmd_req {
420 	struct dlb2_mbox_req_hdr hdr;
421 	u32 domain_id;
422 };
423 
424 struct dlb2_mbox_start_domain_cmd_resp {
425 	struct dlb2_mbox_resp_hdr hdr;
426 	u32 error_code;
427 	u32 status;
428 	u32 padding;
429 };
430 
431 struct dlb2_mbox_enable_ldb_port_intr_cmd_req {
432 	struct dlb2_mbox_req_hdr hdr;
433 	u16 port_id;
434 	u16 thresh;
435 	u16 vector;
436 	u16 owner_vf;
437 	u16 reserved[2];
438 };
439 
440 struct dlb2_mbox_enable_ldb_port_intr_cmd_resp {
441 	struct dlb2_mbox_resp_hdr hdr;
442 	u32 error_code;
443 	u32 status;
444 	u32 padding;
445 };
446 
447 struct dlb2_mbox_enable_dir_port_intr_cmd_req {
448 	struct dlb2_mbox_req_hdr hdr;
449 	u16 port_id;
450 	u16 thresh;
451 	u16 vector;
452 	u16 owner_vf;
453 	u16 reserved[2];
454 };
455 
456 struct dlb2_mbox_enable_dir_port_intr_cmd_resp {
457 	struct dlb2_mbox_resp_hdr hdr;
458 	u32 error_code;
459 	u32 status;
460 	u32 padding;
461 };
462 
463 struct dlb2_mbox_arm_cq_intr_cmd_req {
464 	struct dlb2_mbox_req_hdr hdr;
465 	u32 domain_id;
466 	u32 port_id;
467 	u32 is_ldb;
468 };
469 
470 struct dlb2_mbox_arm_cq_intr_cmd_resp {
471 	struct dlb2_mbox_resp_hdr hdr;
472 	u32 error_code;
473 	u32 status;
474 	u32 padding0;
475 };
476 
477 /*
478  * The alert_id and aux_alert_data follows the format of the alerts defined in
479  * dlb2_types.h. The alert id contains an enum dlb2_domain_alert_id value, and
480  * the aux_alert_data value varies depending on the alert.
481  */
482 struct dlb2_mbox_vf_alert_cmd_req {
483 	struct dlb2_mbox_req_hdr hdr;
484 	u32 domain_id;
485 	u32 alert_id;
486 	u32 aux_alert_data;
487 };
488 
489 enum dlb2_mbox_vf_notification_type {
490 	DLB2_MBOX_VF_NOTIFICATION_PRE_RESET,
491 	DLB2_MBOX_VF_NOTIFICATION_POST_RESET,
492 
493 	/* NUM_DLB2_MBOX_VF_NOTIFICATION_TYPES must be last */
494 	NUM_DLB2_MBOX_VF_NOTIFICATION_TYPES,
495 };
496 
497 struct dlb2_mbox_vf_notification_cmd_req {
498 	struct dlb2_mbox_req_hdr hdr;
499 	u32 notification;
500 };
501 
502 struct dlb2_mbox_vf_in_use_cmd_req {
503 	struct dlb2_mbox_req_hdr hdr;
504 	u32 padding;
505 };
506 
507 struct dlb2_mbox_vf_in_use_cmd_resp {
508 	struct dlb2_mbox_resp_hdr hdr;
509 	u32 in_use;
510 };
511 
512 struct dlb2_mbox_get_sn_allocation_cmd_req {
513 	struct dlb2_mbox_req_hdr hdr;
514 	u32 group_id;
515 };
516 
517 struct dlb2_mbox_get_sn_allocation_cmd_resp {
518 	struct dlb2_mbox_resp_hdr hdr;
519 	u32 num;
520 };
521 
522 struct dlb2_mbox_get_ldb_queue_depth_cmd_req {
523 	struct dlb2_mbox_req_hdr hdr;
524 	u32 domain_id;
525 	u32 queue_id;
526 	u32 padding;
527 };
528 
529 struct dlb2_mbox_get_ldb_queue_depth_cmd_resp {
530 	struct dlb2_mbox_resp_hdr hdr;
531 	u32 error_code;
532 	u32 status;
533 	u32 depth;
534 };
535 
536 struct dlb2_mbox_get_dir_queue_depth_cmd_req {
537 	struct dlb2_mbox_req_hdr hdr;
538 	u32 domain_id;
539 	u32 queue_id;
540 	u32 padding;
541 };
542 
543 struct dlb2_mbox_get_dir_queue_depth_cmd_resp {
544 	struct dlb2_mbox_resp_hdr hdr;
545 	u32 error_code;
546 	u32 status;
547 	u32 depth;
548 };
549 
550 struct dlb2_mbox_pending_port_unmaps_cmd_req {
551 	struct dlb2_mbox_req_hdr hdr;
552 	u32 domain_id;
553 	u32 port_id;
554 	u32 padding;
555 };
556 
557 struct dlb2_mbox_pending_port_unmaps_cmd_resp {
558 	struct dlb2_mbox_resp_hdr hdr;
559 	u32 error_code;
560 	u32 status;
561 	u32 num;
562 };
563 
564 struct dlb2_mbox_get_cos_bw_cmd_req {
565 	struct dlb2_mbox_req_hdr hdr;
566 	u32 cos_id;
567 };
568 
569 struct dlb2_mbox_get_cos_bw_cmd_resp {
570 	struct dlb2_mbox_resp_hdr hdr;
571 	u32 num;
572 };
573 
574 struct dlb2_mbox_get_sn_occupancy_cmd_req {
575 	struct dlb2_mbox_req_hdr hdr;
576 	u32 group_id;
577 };
578 
579 struct dlb2_mbox_get_sn_occupancy_cmd_resp {
580 	struct dlb2_mbox_resp_hdr hdr;
581 	u32 num;
582 };
583 
584 struct dlb2_mbox_query_cq_poll_mode_cmd_req {
585 	struct dlb2_mbox_req_hdr hdr;
586 	u32 padding;
587 };
588 
589 struct dlb2_mbox_query_cq_poll_mode_cmd_resp {
590 	struct dlb2_mbox_resp_hdr hdr;
591 	u32 error_code;
592 	u32 status;
593 	u32 mode;
594 };
595 
596 #endif /* __DLB2_BASE_DLB2_MBOX_H */
597