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/f-stack/freebsd/contrib/device-tree/Bindings/iio/afe/
H A Dvoltage-divider.txt1 Voltage divider
4 When an io-channel measures the midpoint of a voltage divider, the
6 of the divider. This binding describes the voltage divider in such
24 - compatible : "voltage-divider"
28 - full-ohms : Resistance R + Rout for the full divider. The io-channel
33 voltage divider (R = 200 Ohms, Rout = 22 Ohms) and fed to an ADC.
36 compatible = "voltage-divider";
/f-stack/freebsd/contrib/device-tree/Bindings/clock/ti/
H A Ddivider.txt1 Binding for TI divider clock
6 register-mapped adjustable clock rate divider that does not gate and has
44 The binding must also provide the register to control the divider and
45 unless the divider array is provided, min and max dividers. Optionally
56 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
59 - reg : offset for register controlling adjustable divider
64 - ti,bit-shift : number of bits to shift the divider value, defaults to 0
85 compatible = "ti,divider-clock";
94 compatible = "ti,divider-clock";
103 compatible = "ti,composite-divider-clock";
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/clock/
H A Dxgene.txt37 reset and/or the divider. Either may be omitted, but at least
55 - divider-offset : Offset to the divider CSR register from the divider base.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
107 divider-offset = <0x238>;
108 divider-width = <0x9>;
109 divider-shift = <0x0>;
125 divider-offset = <0x10>;
126 divider-width = <0x2>;
127 divider-shift = <0x0>;
H A Dnspire-clock.txt5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
H A Dkeystone-pll.txt4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
29 reg-names = "control", "multiplier", "post-divider";
66 - compatible : shall be "ti,keystone,pll-divider-clock"
70 - bit-mask : arbitrary bitmask for programming the divider
78 compatible = "ti,keystone,pll-divider-clock";
H A Ddove-divider-clock.txt1 PLL divider based Dove clocks
17 - compatible : shall be "marvell,dove-divider-clock"
25 compatible = "marvell,dove-divider-clock";
H A Dsilabs,si5351.txt43 - silabs,clock-source: source clock of the output divider stage N, shall be
50 divider.
89 * - multisynth0 as clock source of output divider
106 * - multisynth1 as clock source of output divider
119 * - xtal as clock source of output divider
/f-stack/freebsd/contrib/device-tree/Bindings/regulator/
H A Dltc3676.txt17 - lltc,fb-voltage-divider: An array of two integers containing the resistor
18 values R1 and R2 of the feedback voltage divider in ohms.
39 lltc,fb-voltage-divider = <127000 200000>;
48 lltc,fb-voltage-divider = <301000 200000>;
57 lltc,fb-voltage-divider = <127000 200000>;
66 lltc,fb-voltage-divider = <221000 200000>;
75 lltc,fb-voltage-divider = <487000 200000>;
89 lltc,fb-voltage-divider = <634000 200000>;
H A Dltc3589.txt17 - lltc,fb-voltage-divider: An array of two integers containing the resistor
18 values R1 and R2 of the feedback voltage divider in ohms.
39 lltc,fb-voltage-divider = <100000 158000>;
48 lltc,fb-voltage-divider = <180000 191000>;
57 lltc,fb-voltage-divider = <270000 100000>;
66 lltc,fb-voltage-divider = <511000 158000>;
74 lltc,fb-voltage-divider = <100000 158000>;
82 lltc,fb-voltage-divider = <180000 191000>;
H A Dmp886x.txt9 - mps,fb-voltage-divider: An array of two integers containing the resistor
10 values R1 and R2 of the feedback voltage divider in kilo ohms.
25 mps,fb-voltage-divider = <80 240>;
/f-stack/freebsd/mips/ingenic/
H A Djz4780_clk_gen.c156 uint32_t divider, div_reg, div_msk, reg, div_l, div_h; in jz4780_clk_gen_set_freq() local
164 divider = abs((int64_t)*fout - (fin / div_l)) < in jz4780_clk_gen_set_freq()
168 div_reg = divider >> sc->clk_descr->clk_div.div_lg; in jz4780_clk_gen_set_freq()
169 divider = div_reg << sc->clk_descr->clk_div.div_lg; in jz4780_clk_gen_set_freq()
170 if (divider == 0) in jz4780_clk_gen_set_freq()
171 divider = 1; in jz4780_clk_gen_set_freq()
173 _fout = fin / divider; in jz4780_clk_gen_set_freq()
191 divider = (div_reg << sc->clk_descr->clk_div.div_lg); in jz4780_clk_gen_set_freq()
195 if (*stop != 0 && *fout != fin / divider && in jz4780_clk_gen_set_freq()
198 *fout = fin / divider; in jz4780_clk_gen_set_freq()
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/f-stack/freebsd/contrib/device-tree/src/arm/
H A Ddra7xx-clocks.dtsi211 compatible = "ti,divider-clock";
222 compatible = "ti,divider-clock";
231 compatible = "ti,divider-clock";
242 compatible = "ti,divider-clock";
274 compatible = "ti,divider-clock";
300 compatible = "ti,divider-clock";
344 compatible = "ti,divider-clock";
382 compatible = "ti,divider-clock";
420 compatible = "ti,divider-clock";
433 compatible = "ti,divider-clock";
[all …]
H A Domap54xx-clocks.dtsi117 compatible = "ti,divider-clock";
134 compatible = "ti,divider-clock";
143 compatible = "ti,divider-clock";
160 compatible = "ti,divider-clock";
190 compatible = "ti,divider-clock";
215 compatible = "ti,divider-clock";
224 compatible = "ti,divider-clock";
233 compatible = "ti,divider-clock";
242 compatible = "ti,divider-clock";
251 compatible = "ti,divider-clock";
[all …]
H A Ddm816x-clocks.dtsi95 compatible = "ti,divider-clock";
113 compatible = "ti,divider-clock";
121 compatible = "ti,divider-clock";
129 compatible = "ti,divider-clock";
137 compatible = "ti,divider-clock";
145 compatible = "ti,divider-clock";
153 compatible = "ti,divider-clock";
161 compatible = "ti,divider-clock";
169 compatible = "ti,divider-clock";
185 compatible = "ti,divider-clock";
H A Domap44xx-clocks.dtsi148 compatible = "ti,divider-clock";
167 compatible = "ti,divider-clock";
177 compatible = "ti,divider-clock";
209 compatible = "ti,divider-clock";
220 compatible = "ti,divider-clock";
239 compatible = "ti,divider-clock";
250 compatible = "ti,divider-clock";
258 compatible = "ti,divider-clock";
267 compatible = "ti,divider-clock";
276 compatible = "ti,divider-clock";
[all …]
H A Dam43xx-clocks.dtsi218 compatible = "ti,divider-clock";
229 compatible = "ti,divider-clock";
240 compatible = "ti,divider-clock";
258 compatible = "ti,divider-clock";
284 compatible = "ti,divider-clock";
302 compatible = "ti,divider-clock";
321 compatible = "ti,divider-clock";
504 compatible = "ti,divider-clock";
542 compatible = "ti,divider-clock";
565 compatible = "ti,divider-clock";
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H A Dimx53-usbarmory.dts153 lltc,fb-voltage-divider = <100000 158000>;
162 lltc,fb-voltage-divider = <180000 191000>;
171 lltc,fb-voltage-divider = <270000 100000>;
180 lltc,fb-voltage-divider = <511000 158000>;
188 lltc,fb-voltage-divider = <100000 158000>;
196 lltc,fb-voltage-divider = <180000 191000>;
/f-stack/freebsd/contrib/device-tree/Bindings/spi/
H A Dspi_oc_tiny.txt8 - baud-width: width, in bits, of the programmable divider used to scale
11 The clock-frequency and baud-width properties are needed only if the divider
12 is programmable. They are not needed if the divider is fixed.
/f-stack/freebsd/contrib/device-tree/Bindings/net/can/
H A Dmpc5xxx-mscan.txt21 also specify which clock source and divider shall be used for the controller:
32 - fsl,mscan-clock-divider: for the reference and system clock, an additional
33 clock divider can be specified. By default, a
52 fsl,mscan-clock-divider = <3>;
/f-stack/freebsd/arm/allwinner/clkng/
H A Dccu_a31.c436 { .value = 0, .divider = 1, },
437 { .value = 1, .divider = 2, },
438 { .value = 2, .divider = 3, },
439 { .value = 3, .divider = 4, },
440 { .value = 4, .divider = 4, },
441 { .value = 5, .divider = 4, },
442 { .value = 6, .divider = 4, },
443 { .value = 7, .divider = 4, },
472 { .value = 0, .divider = 2, },
473 { .value = 1, .divider = 2, },
[all …]
H A Dccu_h3.c425 { .value = 0, .divider = 2, },
426 { .value = 1, .divider = 2, },
427 { .value = 2, .divider = 4, },
428 { .value = 3, .divider = 8, },
461 { .value = 0, .divider = 1, },
462 { .value = 1, .divider = 2, },
463 { .value = 2, .divider = 4, },
464 { .value = 3, .divider = 6, },
/f-stack/freebsd/arm/nvidia/tegra124/
H A Dtegra124_clk_per.c533 uint32_t divider; member
570 sc->divider = 1; in periph_init()
573 sc->divider = 2; in periph_init()
642 uint64_t tmp, divider; in periph_set_freq() local
651 divider = tmp / *fout; in periph_set_freq()
653 divider++; in periph_set_freq()
655 if (divider < (1 << sc->div_f_width)) in periph_set_freq()
656 divider = 1 << (sc->div_f_width - 1); in periph_set_freq()
660 (*fout != (tmp / divider))) in periph_set_freq()
667 sc->divider = divider; in periph_set_freq()
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/f-stack/freebsd/contrib/device-tree/Bindings/mfd/
H A Dgateworks-gsc.yaml68 (i.e. voltage rail with a pre-scaling resistor divider).
83 2 - scaled voltage based on an optional resistor divider
89 gw,voltage-divider-ohms:
90 description: Values of resistors for divider on raw ADC input
179 gw,voltage-divider-ohms = <22100 1000>;
/f-stack/freebsd/contrib/device-tree/Bindings/iio/frequency/
H A Dadf4350.txt21 - adi,reference-div2-enable: Enables reference divider.
48 - adi,12bit-clk-divider: Clock divider value used when
50 - adi,clk-divider-mode:
52 0: Clock divider off (default)
/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_clk_per.c646 uint32_t divider; member
683 sc->divider = 1; in periph_init()
686 sc->divider = 2; in periph_init()
756 uint64_t tmp, divider; in periph_set_freq() local
765 divider = tmp / *fout; in periph_set_freq()
767 divider++; in periph_set_freq()
769 if (divider < (1 << sc->div_f_width)) in periph_set_freq()
770 divider = 1 << (sc->div_f_width - 1); in periph_set_freq()
774 (*fout != (tmp / divider))) in periph_set_freq()
781 sc->divider = divider; in periph_set_freq()
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