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Searched refs:div_mask (Results 1 – 5 of 5) sorted by relevance

/f-stack/freebsd/arm/freescale/vybrid/
H A Dvf_ccm.c159 uint32_t div_mask; member
171 .div_mask = IPG_CLK_DIV_MASK,
207 .div_mask = SAI3_DIV_MASK,
219 .div_mask = CKO1_DIV_MASK,
231 .div_mask = ESDHC0_DIV_M,
243 .div_mask = ESDHC1_DIV_M,
255 .div_mask = 0,
267 .div_mask = 0x7,
279 .div_mask = 0,
291 .div_mask = 0,
[all …]
/f-stack/freebsd/arm64/rockchip/clk/
H A Drk_clk_composite.c53 uint32_t div_mask; member
213 div = ((reg & sc->div_mask) >> sc->div_shift); in rk_clk_composite_recalc()
236 for (div_reg = 0; div_reg <= ((sc->div_mask >> sc->div_shift) + 1); in rk_clk_composite_find_best()
310 dprintf(" div_mask: 0x%X, div_shift: %d\n", sc->div_mask, in rk_clk_composite_set_freq()
315 val |= sc->div_mask << RK_CLK_COMPOSITE_MASK_SHIFT; in rk_clk_composite_set_freq()
360 sc->div_mask = ((1 << clkdef->div_width) - 1) << sc->div_shift; in rk_clk_composite_register()
H A Drk_clk_armclk.c51 uint32_t div_mask; member
137 div = ((reg & sc->div_mask) >> sc->div_shift) + 1; in rk_clk_armclk_recalc()
199 val |= sc->div_mask << RK_ARMCLK_WRITE_MASK_SHIFT; in rk_clk_armclk_set_freq()
244 sc->div_mask = ((1 << clkdef->div_width) - 1) << sc->div_shift; in rk_clk_armclk_register()
/f-stack/freebsd/arm/nvidia/tegra124/
H A Dtegra124_clk_per.c66 uint32_t div_mask; member
528 uint32_t div_mask; member
568 sc->divider = (reg & sc->div_mask) + 2; in periph_init()
664 MD4(sc, sc->base_reg, sc->div_mask, in periph_set_freq()
688 sc->div_mask = (1 <<clkdef->div_width) - 1; in periph_register()
/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_clk_per.c61 uint32_t div_mask; member
641 uint32_t div_mask; member
681 sc->divider = (reg & sc->div_mask) + 2; in periph_init()
778 MD4(sc, sc->base_reg, sc->div_mask, in periph_set_freq()
802 sc->div_mask = (1 <<clkdef->div_width) - 1; in periph_register()