Searched refs:div1 (Results 1 – 2 of 2) sorted by relevance
218 int div0, div1; in cgem_set_ref_clk() local226 for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) { in cgem_set_ref_clk()228 div1 / frequency; in cgem_set_ref_clk()319 int div0, div1; in zy7_pl_fclk_set_freq() local348 for (div1 = 1; div1 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX; div1++) { in zy7_pl_fclk_set_freq()350 div1 / frequency; in zy7_pl_fclk_set_freq()378 return (base_frequency / div0 / div1); in zy7_pl_fclk_set_freq()385 int div0, div1; in zy7_pl_fclk_get_freq() local426 if (div1 == 0) in zy7_pl_fclk_get_freq()427 div1 = 1; in zy7_pl_fclk_get_freq()[all …]
43 "mult-div1" - contains the multiplier / divider register base address