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/f-stack/freebsd/contrib/device-tree/Bindings/net/
H A Dhisilicon-femac.txt19 - hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
40 hisilicon,phy-reset-delays-us = <10000 20000 20000>;
H A Dhisilicon-hix5hd2-gmac.txt28 - hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
55 hisilicon,phy-reset-delays-us = <10000 10000 30000>;
H A Dti,dp83867.yaml81 delays will be left at their default values, as set by the PHY's pin
85 should use "rgmii-id" if internal delays are desired as this may be
86 changed in future to cause "rgmii" mode to disable delays.
H A Dethernet-controller.yaml72 # RX and TX delays are added by the MAC when required
75 # RGMII with internal RX and TX delays provided by the PHY,
76 # the MAC should not add the RX or TX delays in this case
H A Dethernet-phy.yaml168 PHY's that have configurable RX internal delays. If this property is
174 PHY's that have configurable TX internal delays. If this property is
H A Dmicrel-ksz90x1.txt4 to clock delays. You can specify clock delay values in the PHY OF
98 step is 100ps. Unlike KSZ9031, the values represent picoseccond delays.
/f-stack/freebsd/contrib/device-tree/Bindings/fsi/
H A Dfsi-master-gpio.txt14 - no-gpio-delays; : Don't add extra delays between GPIO
/f-stack/freebsd/contrib/device-tree/Bindings/net/dsa/
H A Dsja1105.txt19 of support for RGMII internal delays (supported on P/Q/R/S, but not on
36 delays:
40 is the PHY. The SJA1105 MAC does not apply any internal delays.
42 of the above, the designated entity to apply the internal delays
/f-stack/freebsd/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxbb-p201.dts24 snps,reset-delays-us = <0>, <10000>, <1000000>;
/f-stack/freebsd/net/altq/
H A Daltq_cbq.h88 u_int delays; /* # times invoked delay actions */ member
H A Daltq_rmclass.h133 u_int delays; /* # times invoked delay actions */ member
H A Daltq_cbq.c181 statsp->delays = cl->stats_.delays; in get_class_stats()
/f-stack/freebsd/contrib/device-tree/Bindings/mmc/
H A Dsdhci-sprd.txt26 PHY DLL delays are used to delay the data valid window, and align the window
27 to sampling clock. PHY DLL delays can be configured by following properties,
H A Dcdns,sdhci.yaml32 # PHY DLL input delays:
82 # PHY DLL clock delays:
/f-stack/freebsd/contrib/device-tree/Bindings/input/touchscreen/
H A Dti-tsc-adc.txt54 ti,chan-step-opendelay: List of open delays for each channel of
61 ti,chan-step-sampledelay: List of sample delays for each channel
/f-stack/freebsd/contrib/device-tree/src/arm64/qcom/
H A Dqcs404-evb-4000.dts20 snps,reset-delays-us = <0 10000 10000>;
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Drockchip-radxa-dalang-carrier.dtsi63 snps,reset-delays-us = <0 10000 50000>;
/f-stack/freebsd/contrib/device-tree/Bindings/mtd/
H A Dfsl-upm-nand.txt17 - fsl,upm-wait-flags : add chip-dependent short delays after running the
/f-stack/freebsd/arm/versatile/
H A Dpl050.c550 static const int delays[] = {250, 500, 750, 1000}; in kmi_set_typematic() local
559 kbd->kb_delay1 = delays[(code >> 5) & 3]; in kmi_set_typematic()
/f-stack/freebsd/contrib/device-tree/src/mips/ingenic/
H A Dcu1000-neo.dts126 snps,reset-delays-us = <0 10000 30000>;
H A Dcu1830-neo.dts126 snps,reset-delays-us = <0 10000 30000>;
/f-stack/freebsd/contrib/openzfs/tests/zfs-tests/tests/perf/
H A Dperf.shlib296 # In case there's been some "leaked" zinject delays, or if the
297 # performance test injected some delays itself, we clear all
298 # delays before attempting to destroy the pool. Each delay
300 # are any outstanding delays.
/f-stack/freebsd/contrib/device-tree/Bindings/mfd/
H A Dmax77620.txt34 and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can be programmed
50 power sequencer, the power up and power down delays can be specified in
/f-stack/freebsd/contrib/device-tree/src/arm64/rockchip/
H A Drk3399-ficus.dts85 snps,reset-delays-us = <0 10000 50000>;
/f-stack/freebsd/contrib/device-tree/src/arm64/hisilicon/
H A Dhi3798cv200-poplar.dts99 hisilicon,phy-reset-delays-us = <10000 10000 30000>;

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