1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #ifndef _ICE_ADMINQ_CMD_H_ 6 #define _ICE_ADMINQ_CMD_H_ 7 8 /* This header file defines the Admin Queue commands, error codes and 9 * descriptor format. It is shared between Firmware and Software. 10 */ 11 12 #define ICE_MAX_VSI 768 13 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 14 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 15 16 struct ice_aqc_generic { 17 __le32 param0; 18 __le32 param1; 19 __le32 addr_high; 20 __le32 addr_low; 21 }; 22 23 /* Get version (direct 0x0001) */ 24 struct ice_aqc_get_ver { 25 __le32 rom_ver; 26 __le32 fw_build; 27 u8 fw_branch; 28 u8 fw_major; 29 u8 fw_minor; 30 u8 fw_patch; 31 u8 api_branch; 32 u8 api_major; 33 u8 api_minor; 34 u8 api_patch; 35 }; 36 37 /* Send driver version (indirect 0x0002) */ 38 struct ice_aqc_driver_ver { 39 u8 major_ver; 40 u8 minor_ver; 41 u8 build_ver; 42 u8 subbuild_ver; 43 u8 reserved[4]; 44 __le32 addr_high; 45 __le32 addr_low; 46 }; 47 48 /* Queue Shutdown (direct 0x0003) */ 49 struct ice_aqc_q_shutdown { 50 u8 driver_unloading; 51 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 52 u8 reserved[15]; 53 }; 54 55 /* Request resource ownership (direct 0x0008) 56 * Release resource ownership (direct 0x0009) 57 */ 58 struct ice_aqc_req_res { 59 __le16 res_id; 60 #define ICE_AQC_RES_ID_NVM 1 61 #define ICE_AQC_RES_ID_SDP 2 62 #define ICE_AQC_RES_ID_CHNG_LOCK 3 63 #define ICE_AQC_RES_ID_GLBL_LOCK 4 64 __le16 access_type; 65 #define ICE_AQC_RES_ACCESS_READ 1 66 #define ICE_AQC_RES_ACCESS_WRITE 2 67 68 /* Upon successful completion, FW writes this value and driver is 69 * expected to release resource before timeout. This value is provided 70 * in milliseconds. 71 */ 72 __le32 timeout; 73 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 74 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 75 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 76 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 77 /* For SDP: pin ID of the SDP */ 78 __le32 res_number; 79 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 80 __le16 status; 81 #define ICE_AQ_RES_GLBL_SUCCESS 0 82 #define ICE_AQ_RES_GLBL_IN_PROG 1 83 #define ICE_AQ_RES_GLBL_DONE 2 84 u8 reserved[2]; 85 }; 86 87 /* Get function capabilities (indirect 0x000A) 88 * Get device capabilities (indirect 0x000B) 89 */ 90 struct ice_aqc_list_caps { 91 u8 cmd_flags; 92 u8 pf_index; 93 u8 reserved[2]; 94 __le32 count; 95 __le32 addr_high; 96 __le32 addr_low; 97 }; 98 99 /* Device/Function buffer entry, repeated per reported capability */ 100 struct ice_aqc_list_caps_elem { 101 __le16 cap; 102 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 103 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_MAX_MTU 0x0047 112 #define ICE_AQC_CAPS_IWARP 0x0051 113 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 114 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 115 116 u8 major_ver; 117 u8 minor_ver; 118 /* Number of resources described by this capability */ 119 __le32 number; 120 /* Only meaningful for some types of resources */ 121 __le32 logical_id; 122 /* Only meaningful for some types of resources */ 123 __le32 phys_id; 124 __le64 rsvd1; 125 __le64 rsvd2; 126 }; 127 128 /* Manage MAC address, read command - indirect (0x0107) 129 * This struct is also used for the response 130 */ 131 struct ice_aqc_manage_mac_read { 132 __le16 flags; /* Zeroed by device driver */ 133 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 134 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 135 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 136 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 137 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8) 138 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9) 139 #define ICE_AQC_MAN_MAC_READ_S 4 140 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 141 u8 rsvd[2]; 142 u8 num_addr; /* Used in response */ 143 u8 rsvd1[3]; 144 __le32 addr_high; 145 __le32 addr_low; 146 }; 147 148 /* Response buffer format for manage MAC read command */ 149 struct ice_aqc_manage_mac_read_resp { 150 u8 lport_num; 151 u8 addr_type; 152 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 153 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 154 u8 mac_addr[ETH_ALEN]; 155 }; 156 157 /* Manage MAC address, write command - direct (0x0108) */ 158 struct ice_aqc_manage_mac_write { 159 u8 rsvd; 160 u8 flags; 161 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 162 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 163 #define ICE_AQC_MAN_MAC_WR_S 6 164 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S) 165 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 166 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 167 /* byte stream in network order */ 168 u8 mac_addr[ETH_ALEN]; 169 __le32 addr_high; 170 __le32 addr_low; 171 }; 172 173 /* Clear PXE Command and response (direct 0x0110) */ 174 struct ice_aqc_clear_pxe { 175 u8 rx_cnt; 176 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 177 u8 reserved[15]; 178 }; 179 180 /* Configure No-Drop Policy Command (direct 0x0112) */ 181 struct ice_aqc_config_no_drop_policy { 182 u8 opts; 183 #define ICE_AQC_FORCE_NO_DROP BIT(0) 184 u8 rsvd[15]; 185 }; 186 187 /* Get switch configuration (0x0200) */ 188 struct ice_aqc_get_sw_cfg { 189 /* Reserved for command and copy of request flags for response */ 190 __le16 flags; 191 /* First desc in case of command and next_elem in case of response 192 * In case of response, if it is not zero, means all the configuration 193 * was not returned and new command shall be sent with this value in 194 * the 'first desc' field 195 */ 196 __le16 element; 197 /* Reserved for command, only used for response */ 198 __le16 num_elems; 199 __le16 rsvd; 200 __le32 addr_high; 201 __le32 addr_low; 202 }; 203 204 /* Each entry in the response buffer is of the following type: */ 205 struct ice_aqc_get_sw_cfg_resp_elem { 206 /* VSI/Port Number */ 207 __le16 vsi_port_num; 208 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 209 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 210 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 211 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 212 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 213 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 214 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 215 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 216 217 /* SWID VSI/Port belongs to */ 218 __le16 swid; 219 220 /* Bit 14..0 : PF/VF number VSI belongs to 221 * Bit 15 : VF indication bit 222 */ 223 __le16 pf_vf_num; 224 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 225 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 226 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 227 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 228 }; 229 230 /* These resource type defines are used for all switch resource 231 * commands where a resource type is required, such as: 232 * Get Resource Allocation command (indirect 0x0204) 233 * Allocate Resources command (indirect 0x0208) 234 * Free Resources command (indirect 0x0209) 235 * Get Allocated Resource Descriptors Command (indirect 0x020A) 236 */ 237 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 238 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 239 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 240 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 241 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 242 #define ICE_AQC_RES_TYPE_RECIPE 0x05 243 #define ICE_AQC_RES_TYPE_PROFILE 0x06 244 #define ICE_AQC_RES_TYPE_SWID 0x07 245 #define ICE_AQC_RES_TYPE_VSI 0x08 246 #define ICE_AQC_RES_TYPE_FLU 0x09 247 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 248 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 249 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 250 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 251 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 252 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 253 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 254 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 255 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 256 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 257 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 258 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 259 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 260 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 261 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 262 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 263 /* Resource types 0x62-67 are reserved for Hash profile builder */ 264 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 265 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 266 267 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 268 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 269 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 270 271 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 272 273 #define ICE_AQC_RES_TYPE_S 0 274 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 275 276 /* Get Resource Allocation command (indirect 0x0204) */ 277 struct ice_aqc_get_res_alloc { 278 __le16 resp_elem_num; /* Used in response, reserved in command */ 279 u8 reserved[6]; 280 __le32 addr_high; 281 __le32 addr_low; 282 }; 283 284 /* Get Resource Allocation Response Buffer per response */ 285 struct ice_aqc_get_res_resp_elem { 286 __le16 res_type; /* Types defined above cmd 0x0204 */ 287 __le16 total_capacity; /* Resources available to all PF's */ 288 __le16 total_function; /* Resources allocated for a PF */ 289 __le16 total_shared; /* Resources allocated as shared */ 290 __le16 total_free; /* Resources un-allocated/not reserved by any PF */ 291 }; 292 293 /* Allocate Resources command (indirect 0x0208) 294 * Free Resources command (indirect 0x0209) 295 */ 296 struct ice_aqc_alloc_free_res_cmd { 297 __le16 num_entries; /* Number of Resource entries */ 298 u8 reserved[6]; 299 __le32 addr_high; 300 __le32 addr_low; 301 }; 302 303 /* Resource descriptor */ 304 struct ice_aqc_res_elem { 305 union { 306 __le16 sw_resp; 307 __le16 flu_resp; 308 } e; 309 }; 310 311 /* Buffer for Allocate/Free Resources commands */ 312 struct ice_aqc_alloc_free_res_elem { 313 __le16 res_type; /* Types defined above cmd 0x0204 */ 314 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 315 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 316 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 317 __le16 num_elems; 318 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN]; 319 }; 320 321 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ 322 struct ice_aqc_get_allocd_res_desc { 323 union { 324 struct { 325 __le16 res; /* Types defined above cmd 0x0204 */ 326 __le16 first_desc; 327 __le32 reserved; 328 } cmd; 329 struct { 330 __le16 res; 331 __le16 next_desc; 332 __le16 num_desc; 333 __le16 reserved; 334 } resp; 335 } ops; 336 __le32 addr_high; 337 __le32 addr_low; 338 }; 339 340 /* Add VSI (indirect 0x0210) 341 * Update VSI (indirect 0x0211) 342 * Get VSI (indirect 0x0212) 343 * Free VSI (indirect 0x0213) 344 */ 345 struct ice_aqc_add_get_update_free_vsi { 346 __le16 vsi_num; 347 #define ICE_AQ_VSI_NUM_S 0 348 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 349 #define ICE_AQ_VSI_IS_VALID BIT(15) 350 __le16 cmd_flags; 351 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 352 u8 vf_id; 353 u8 reserved; 354 __le16 vsi_flags; 355 #define ICE_AQ_VSI_TYPE_S 0 356 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 357 #define ICE_AQ_VSI_TYPE_VF 0x0 358 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 359 #define ICE_AQ_VSI_TYPE_PF 0x2 360 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 361 __le32 addr_high; 362 __le32 addr_low; 363 }; 364 365 /* Response descriptor for: 366 * Add VSI (indirect 0x0210) 367 * Update VSI (indirect 0x0211) 368 * Free VSI (indirect 0x0213) 369 */ 370 struct ice_aqc_add_update_free_vsi_resp { 371 __le16 vsi_num; 372 __le16 ext_status; 373 __le16 vsi_used; 374 __le16 vsi_free; 375 __le32 addr_high; 376 __le32 addr_low; 377 }; 378 379 struct ice_aqc_get_vsi_resp { 380 __le16 vsi_num; 381 u8 vf_id; 382 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values. 383 * These are found above in struct ice_aqc_add_get_update_free_vsi. 384 */ 385 u8 vsi_flags; 386 __le16 vsi_used; 387 __le16 vsi_free; 388 __le32 addr_high; 389 __le32 addr_low; 390 }; 391 392 struct ice_aqc_vsi_props { 393 __le16 valid_sections; 394 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 395 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 396 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 397 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 398 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 399 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 400 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 401 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 402 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 403 #define ICE_AQ_VSI_PROP_ACL_VALID BIT(10) 404 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 405 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 406 /* switch section */ 407 u8 sw_id; 408 u8 sw_flags; 409 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 410 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 411 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 412 u8 sw_flags2; 413 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 414 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 415 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 416 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 417 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 418 u8 veb_stat_id; 419 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 420 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 421 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 422 /* security section */ 423 u8 sec_flags; 424 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 425 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 426 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 427 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 428 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 429 u8 sec_reserved; 430 /* VLAN section */ 431 __le16 pvid; /* VLANS include priority bits */ 432 u8 pvlan_reserved[2]; 433 u8 vlan_flags; 434 #define ICE_AQ_VSI_VLAN_MODE_S 0 435 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 436 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 437 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 438 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 439 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 440 #define ICE_AQ_VSI_VLAN_EMOD_S 3 441 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 442 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 443 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 444 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 445 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 446 u8 pvlan_reserved2[3]; 447 /* ingress egress up sections */ 448 __le32 ingress_table; /* bitmap, 3 bits per up */ 449 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 450 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 451 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 452 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 453 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 454 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 455 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 456 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 457 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 458 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 459 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 460 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 461 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 462 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 463 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 464 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 465 __le32 egress_table; /* same defines as for ingress table */ 466 /* outer tags section */ 467 __le16 outer_tag; 468 u8 outer_tag_flags; 469 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 470 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 471 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 472 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 473 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 474 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 475 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 476 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 477 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 478 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 479 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 480 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 481 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 482 u8 outer_tag_reserved; 483 /* queue mapping section */ 484 __le16 mapping_flags; 485 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 486 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 487 __le16 q_mapping[16]; 488 #define ICE_AQ_VSI_Q_S 0 489 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 490 __le16 tc_mapping[8]; 491 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 492 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 493 #define ICE_AQ_VSI_TC_Q_NUM_S 11 494 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 495 /* queueing option section */ 496 u8 q_opt_rss; 497 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 498 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 499 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 500 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 501 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 502 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 503 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 504 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 505 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 506 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 507 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 508 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 509 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 510 u8 q_opt_tc; 511 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 512 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 513 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 514 u8 q_opt_flags; 515 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 516 u8 q_opt_reserved[3]; 517 /* outer up section */ 518 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 519 /* ACL section */ 520 __le16 acl_def_act; 521 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_S 0 522 #define ICE_AQ_VSI_ACL_DEF_RX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S) 523 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S 4 524 #define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S) 525 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_S 8 526 #define ICE_AQ_VSI_ACL_DEF_TX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S) 527 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S 12 528 #define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S) 529 /* flow director section */ 530 __le16 fd_options; 531 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 532 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 533 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 534 __le16 max_fd_fltr_dedicated; 535 __le16 max_fd_fltr_shared; 536 __le16 fd_def_q; 537 #define ICE_AQ_VSI_FD_DEF_Q_S 0 538 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 539 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 540 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 541 __le16 fd_report_opt; 542 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 543 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 544 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 545 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 546 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 547 /* PASID section */ 548 __le32 pasid_id; 549 #define ICE_AQ_VSI_PASID_ID_S 0 550 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 551 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 552 u8 reserved[24]; 553 }; 554 555 /* Add/update mirror rule - direct (0x0260) */ 556 #define ICE_AQC_RULE_ID_VALID_S 7 557 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) 558 #define ICE_AQC_RULE_ID_S 0 559 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) 560 561 /* Following defines to be used while processing caller specified mirror list 562 * of VSI indexes. 563 */ 564 /* Action: Byte.bit (1.7) 565 * 0 = Remove VSI from mirror rule 566 * 1 = Add VSI to mirror rule 567 */ 568 #define ICE_AQC_RULE_ACT_S 15 569 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S) 570 /* Action: 1.2:0.0 = Mirrored VSI */ 571 #define ICE_AQC_RULE_MIRRORED_VSI_S 0 572 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S) 573 574 /* This is to be used by add/update mirror rule Admin Queue command. 575 * In case of add mirror rule - if rule ID is specified as 576 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool. 577 * If specified rule_id is valid, then it is used. If specified rule_id 578 * is in use then new mirroring rule is added. 579 */ 580 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF 581 582 struct ice_aqc_add_update_mir_rule { 583 __le16 rule_id; 584 585 __le16 rule_type; 586 #define ICE_AQC_RULE_TYPE_S 0 587 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S) 588 /* VPORT ingress/egress */ 589 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1 590 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2 591 /* Physical port ingress mirroring. 592 * All traffic received by this port 593 */ 594 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6 595 /* Physical port egress mirroring. All traffic sent by this port */ 596 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7 597 598 /* Number of mirrored entries. 599 * The values are in the command buffer 600 */ 601 __le16 num_entries; 602 603 /* Destination VSI */ 604 __le16 dest; 605 __le32 addr_high; 606 __le32 addr_low; 607 }; 608 609 /* Delete mirror rule - direct(0x0261) */ 610 struct ice_aqc_delete_mir_rule { 611 __le16 rule_id; 612 __le16 rsvd; 613 614 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of 615 * the PF allocated resources, otherwise it is returned to the 616 * shared pool 617 */ 618 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0 619 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S) 620 __le16 flags; 621 622 u8 reserved[10]; 623 }; 624 625 /* Set/Get storm config - (direct 0x0280, 0x0281) */ 626 /* This structure holds get storm configuration response and same structure 627 * is used to perform set_storm_cfg 628 */ 629 struct ice_aqc_storm_cfg { 630 __le32 bcast_thresh_size; 631 __le32 mcast_thresh_size; 632 /* Bit 18:0 - Traffic upper threshold size 633 * Bit 31:19 - Reserved 634 */ 635 #define ICE_AQ_THRESHOLD_S 0 636 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S) 637 638 __le32 storm_ctrl_ctrl; 639 /* Bit 0: MDIPW - Drop Multicast packets in previous window 640 * Bit 1: MDICW - Drop multicast packets in current window 641 * Bit 2: BDIPW - Drop broadcast packets in previous window 642 * Bit 3: BDICW - Drop broadcast packets in current window 643 */ 644 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0) 645 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1) 646 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2) 647 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3) 648 /* Bit 7:5 : Reserved */ 649 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The 650 * interval size for applying ingress broadcast or multicast storm 651 * control. 652 */ 653 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8 654 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \ 655 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S) 656 __le32 reserved; 657 }; 658 659 #define ICE_MAX_NUM_RECIPES 64 660 661 /* Add/Get Recipe (indirect 0x0290/0x0292) */ 662 struct ice_aqc_add_get_recipe { 663 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 664 __le16 return_index; /* Input, used for Get cmd only */ 665 u8 reserved[4]; 666 __le32 addr_high; 667 __le32 addr_low; 668 }; 669 670 struct ice_aqc_recipe_content { 671 u8 rid; 672 #define ICE_AQ_RECIPE_ID_S 0 673 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S) 674 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 675 #define ICE_AQ_SW_ID_LKUP_IDX 0 676 u8 lkup_indx[5]; 677 #define ICE_AQ_RECIPE_LKUP_DATA_S 0 678 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S) 679 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 680 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 681 __le16 mask[5]; 682 u8 result_indx; 683 #define ICE_AQ_RECIPE_RESULT_DATA_S 0 684 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 685 #define ICE_AQ_RECIPE_RESULT_EN BIT(7) 686 u8 rsvd0[3]; 687 u8 act_ctrl_join_priority; 688 u8 act_ctrl_fwd_priority; 689 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0 690 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S) 691 u8 act_ctrl; 692 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0) 693 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1) 694 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 695 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4 696 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S) 697 u8 rsvd1; 698 __le32 dflt_act; 699 #define ICE_AQ_RECIPE_DFLT_ACT_S 0 700 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S) 701 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31) 702 }; 703 704 struct ice_aqc_recipe_data_elem { 705 u8 recipe_indx; 706 u8 resp_bits; 707 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0) 708 u8 rsvd0[2]; 709 u8 recipe_bitmap[8]; 710 u8 rsvd1[4]; 711 struct ice_aqc_recipe_content content; 712 u8 rsvd2[20]; 713 }; 714 715 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 716 struct ice_aqc_recipe_to_profile { 717 __le16 profile_id; 718 u8 rsvd[6]; 719 ice_declare_bitmap(recipe_assoc, ICE_MAX_NUM_RECIPES); 720 }; 721 722 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 723 */ 724 struct ice_aqc_sw_rules { 725 /* ops: add switch rules, referring the number of rules. 726 * ops: update switch rules, referring the number of filters 727 * ops: remove switch rules, referring the entry index. 728 * ops: get switch rules, referring to the number of filters. 729 */ 730 __le16 num_rules_fltr_entry_index; 731 u8 reserved[6]; 732 __le32 addr_high; 733 __le32 addr_low; 734 }; 735 736 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 737 * This structures describes the lookup rules and associated actions. "index" 738 * is returned as part of a response to a successful Add command, and can be 739 * used to identify the rule for Update/Get/Remove commands. 740 */ 741 struct ice_sw_rule_lkup_rx_tx { 742 __le16 recipe_id; 743 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 744 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 745 __le16 src; 746 __le32 act; 747 748 /* Bit 0:1 - Action type */ 749 #define ICE_SINGLE_ACT_TYPE_S 0x00 750 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 751 752 /* Bit 2 - Loop back enable 753 * Bit 3 - LAN enable 754 */ 755 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 756 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 757 758 /* Action type = 0 - Forward to VSI or VSI list */ 759 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 760 761 #define ICE_SINGLE_ACT_VSI_ID_S 4 762 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 763 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 764 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 765 /* This bit needs to be set if action is forward to VSI list */ 766 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 767 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 768 #define ICE_SINGLE_ACT_DROP BIT(18) 769 770 /* Action type = 1 - Forward to Queue of Queue group */ 771 #define ICE_SINGLE_ACT_TO_Q 0x1 772 #define ICE_SINGLE_ACT_Q_INDEX_S 4 773 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 774 #define ICE_SINGLE_ACT_Q_REGION_S 15 775 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 776 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 777 778 /* Action type = 2 - Prune */ 779 #define ICE_SINGLE_ACT_PRUNE 0x2 780 #define ICE_SINGLE_ACT_EGRESS BIT(15) 781 #define ICE_SINGLE_ACT_INGRESS BIT(16) 782 #define ICE_SINGLE_ACT_PRUNET BIT(17) 783 /* Bit 18 should be set to 0 for this action */ 784 785 /* Action type = 2 - Pointer */ 786 #define ICE_SINGLE_ACT_PTR 0x2 787 #define ICE_SINGLE_ACT_PTR_VAL_S 4 788 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 789 /* Bit 18 should be set to 1 */ 790 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 791 792 /* Action type = 3 - Other actions. Last two bits 793 * are other action identifier 794 */ 795 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 796 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 797 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 798 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 799 800 /* Bit 17:18 - Defines other actions */ 801 /* Other action = 0 - Mirror VSI */ 802 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 803 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 804 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 805 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 806 807 /* Other action = 3 - Set Stat count */ 808 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 809 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 810 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 811 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 812 813 __le16 index; /* The index of the rule in the lookup table */ 814 /* Length and values of the header to be matched per recipe or 815 * lookup-type 816 */ 817 __le16 hdr_len; 818 u8 hdr[STRUCT_HACK_VAR_LEN]; 819 }; 820 821 /* Add/Update/Remove large action command/response entry 822 * "index" is returned as part of a response to a successful Add command, and 823 * can be used to identify the action for Update/Get/Remove commands. 824 */ 825 struct ice_sw_rule_lg_act { 826 __le16 index; /* Index in large action table */ 827 __le16 size; 828 /* Max number of large actions */ 829 #define ICE_MAX_LG_ACT 4 830 /* Bit 0:1 - Action type */ 831 #define ICE_LG_ACT_TYPE_S 0 832 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 833 834 /* Action type = 0 - Forward to VSI or VSI list */ 835 #define ICE_LG_ACT_VSI_FORWARDING 0 836 #define ICE_LG_ACT_VSI_ID_S 3 837 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 838 #define ICE_LG_ACT_VSI_LIST_ID_S 3 839 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 840 /* This bit needs to be set if action is forward to VSI list */ 841 #define ICE_LG_ACT_VSI_LIST BIT(13) 842 843 #define ICE_LG_ACT_VALID_BIT BIT(16) 844 845 /* Action type = 1 - Forward to Queue of Queue group */ 846 #define ICE_LG_ACT_TO_Q 0x1 847 #define ICE_LG_ACT_Q_INDEX_S 3 848 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 849 #define ICE_LG_ACT_Q_REGION_S 14 850 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 851 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 852 853 /* Action type = 2 - Prune */ 854 #define ICE_LG_ACT_PRUNE 0x2 855 #define ICE_LG_ACT_EGRESS BIT(14) 856 #define ICE_LG_ACT_INGRESS BIT(15) 857 #define ICE_LG_ACT_PRUNET BIT(16) 858 859 /* Action type = 3 - Mirror VSI */ 860 #define ICE_LG_OTHER_ACT_MIRROR 0x3 861 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 862 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 863 864 /* Action type = 5 - Generic Value */ 865 #define ICE_LG_ACT_GENERIC 0x5 866 #define ICE_LG_ACT_GENERIC_VALUE_S 3 867 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 868 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 869 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 870 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 871 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 872 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 873 874 /* Action = 7 - Set Stat count */ 875 #define ICE_LG_ACT_STAT_COUNT 0x7 876 #define ICE_LG_ACT_STAT_COUNT_S 3 877 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 878 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */ 879 }; 880 881 /* Add/Update/Remove VSI list command/response entry 882 * "index" is returned as part of a response to a successful Add command, and 883 * can be used to identify the VSI list for Update/Get/Remove commands. 884 */ 885 struct ice_sw_rule_vsi_list { 886 __le16 index; /* Index of VSI/Prune list */ 887 __le16 number_vsi; 888 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */ 889 }; 890 891 #pragma pack(1) 892 /* Query VSI list command/response entry */ 893 struct ice_sw_rule_vsi_list_query { 894 __le16 index; 895 ice_declare_bitmap(vsi_list, ICE_MAX_VSI); 896 }; 897 #pragma pack() 898 899 #pragma pack(1) 900 /* Add switch rule response: 901 * Content of return buffer is same as the input buffer. The status field and 902 * LUT index are updated as part of the response 903 */ 904 struct ice_aqc_sw_rules_elem { 905 __le16 type; /* Switch rule type, one of T_... */ 906 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 907 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 908 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 909 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 910 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 911 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 912 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 913 __le16 status; 914 union { 915 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 916 struct ice_sw_rule_lg_act lg_act; 917 struct ice_sw_rule_vsi_list vsi_list; 918 struct ice_sw_rule_vsi_list_query vsi_list_query; 919 } pdata; 920 }; 921 922 #pragma pack() 923 924 /* PFC Ignore (direct 0x0301) 925 * The command and response use the same descriptor structure 926 */ 927 struct ice_aqc_pfc_ignore { 928 u8 tc_bitmap; 929 u8 cmd_flags; /* unused in response */ 930 #define ICE_AQC_PFC_IGNORE_SET BIT(7) 931 #define ICE_AQC_PFC_IGNORE_CLEAR 0 932 u8 reserved[14]; 933 }; 934 935 /* Set PFC Mode (direct 0x0303) 936 * Query PFC Mode (direct 0x0302) 937 */ 938 struct ice_aqc_set_query_pfc_mode { 939 u8 pfc_mode; 940 /* For Set Command response, reserved in all other cases */ 941 #define ICE_AQC_PFC_NOT_CONFIGURED 0 942 /* For Query Command response, reserved in all other cases */ 943 #define ICE_AQC_DCB_DIS 0 944 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 945 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 946 u8 rsvd[15]; 947 }; 948 949 /* Set DCB Parameters (direct 0x0306) */ 950 struct ice_aqc_set_dcb_params { 951 u8 cmd_flags; /* unused in response */ 952 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) 953 #define ICE_AQC_PERSIST_DCB_CFG BIT(1) 954 u8 valid_flags; /* unused in response */ 955 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) 956 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1) 957 u8 rsvd[14]; 958 }; 959 960 /* Get Default Topology (indirect 0x0400) */ 961 struct ice_aqc_get_topo { 962 u8 port_num; 963 u8 num_branches; 964 __le16 reserved1; 965 __le32 reserved2; 966 __le32 addr_high; 967 __le32 addr_low; 968 }; 969 970 /* Update TSE (indirect 0x0403) 971 * Get TSE (indirect 0x0404) 972 * Add TSE (indirect 0x0401) 973 * Delete TSE (indirect 0x040F) 974 * Move TSE (indirect 0x0408) 975 * Suspend Nodes (indirect 0x0409) 976 * Resume Nodes (indirect 0x040A) 977 */ 978 struct ice_aqc_sched_elem_cmd { 979 __le16 num_elem_req; /* Used by commands */ 980 __le16 num_elem_resp; /* Used by responses */ 981 __le32 reserved; 982 __le32 addr_high; 983 __le32 addr_low; 984 }; 985 986 struct ice_aqc_txsched_move_grp_info_hdr { 987 __le32 src_parent_teid; 988 __le32 dest_parent_teid; 989 __le16 num_elems; 990 __le16 reserved; 991 }; 992 993 struct ice_aqc_move_elem { 994 struct ice_aqc_txsched_move_grp_info_hdr hdr; 995 __le32 teid[STRUCT_HACK_VAR_LEN]; 996 }; 997 998 struct ice_aqc_elem_info_bw { 999 __le16 bw_profile_idx; 1000 __le16 bw_alloc; 1001 }; 1002 1003 struct ice_aqc_txsched_elem { 1004 u8 elem_type; /* Special field, reserved for some aq calls */ 1005 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 1006 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 1007 #define ICE_AQC_ELEM_TYPE_TC 0x2 1008 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 1009 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 1010 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 1011 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 1012 u8 valid_sections; 1013 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 1014 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 1015 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 1016 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 1017 u8 generic; 1018 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 1019 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 1020 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 1021 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 1022 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 1023 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 1024 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 1025 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 1026 u8 flags; /* Special field, reserved for some aq calls */ 1027 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 1028 struct ice_aqc_elem_info_bw cir_bw; 1029 struct ice_aqc_elem_info_bw eir_bw; 1030 __le16 srl_id; 1031 __le16 reserved2; 1032 }; 1033 1034 struct ice_aqc_txsched_elem_data { 1035 __le32 parent_teid; 1036 __le32 node_teid; 1037 struct ice_aqc_txsched_elem data; 1038 }; 1039 1040 struct ice_aqc_txsched_topo_grp_info_hdr { 1041 __le32 parent_teid; 1042 __le16 num_elems; 1043 __le16 reserved2; 1044 }; 1045 1046 struct ice_aqc_add_elem { 1047 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1048 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN]; 1049 }; 1050 1051 struct ice_aqc_get_topo_elem { 1052 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1053 struct ice_aqc_txsched_elem_data 1054 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1055 }; 1056 1057 struct ice_aqc_delete_elem { 1058 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1059 __le32 teid[STRUCT_HACK_VAR_LEN]; 1060 }; 1061 1062 /* Query Port ETS (indirect 0x040E) 1063 * 1064 * This indirect command is used to query port TC node configuration. 1065 */ 1066 struct ice_aqc_query_port_ets { 1067 __le32 port_teid; 1068 __le32 reserved; 1069 __le32 addr_high; 1070 __le32 addr_low; 1071 }; 1072 1073 struct ice_aqc_port_ets_elem { 1074 u8 tc_valid_bits; 1075 u8 reserved[3]; 1076 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 1077 __le32 up2tc; 1078 u8 tc_bw_share[8]; 1079 __le32 port_eir_prof_id; 1080 __le32 port_cir_prof_id; 1081 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 1082 __le32 tc_node_prio; 1083 #define ICE_TC_NODE_PRIO_S 0x4 1084 u8 reserved1[4]; 1085 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 1086 }; 1087 1088 /* Rate limiting profile for 1089 * Add RL profile (indirect 0x0410) 1090 * Query RL profile (indirect 0x0411) 1091 * Remove RL profile (indirect 0x0415) 1092 * These indirect commands acts on single or multiple 1093 * RL profiles with specified data. 1094 */ 1095 struct ice_aqc_rl_profile { 1096 __le16 num_profiles; 1097 __le16 num_processed; /* Only for response. Reserved in Command. */ 1098 u8 reserved[4]; 1099 __le32 addr_high; 1100 __le32 addr_low; 1101 }; 1102 1103 struct ice_aqc_rl_profile_elem { 1104 u8 level; 1105 u8 flags; 1106 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1107 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1108 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1109 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1110 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1111 /* The following flag is used for Query RL Profile Data */ 1112 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1113 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1114 1115 __le16 profile_id; 1116 __le16 max_burst_size; 1117 __le16 rl_multiply; 1118 __le16 wake_up_calc; 1119 __le16 rl_encode; 1120 }; 1121 1122 /* Configure L2 Node CGD (indirect 0x0414) 1123 * This indirect command allows configuring a congestion domain for given L2 1124 * node TEIDs in the scheduler topology. 1125 */ 1126 struct ice_aqc_cfg_l2_node_cgd { 1127 __le16 num_l2_nodes; 1128 u8 reserved[6]; 1129 __le32 addr_high; 1130 __le32 addr_low; 1131 }; 1132 1133 struct ice_aqc_cfg_l2_node_cgd_elem { 1134 __le32 node_teid; 1135 u8 cgd; 1136 u8 reserved[3]; 1137 }; 1138 1139 /* Query Scheduler Resource Allocation (indirect 0x0412) 1140 * This indirect command retrieves the scheduler resources allocated by 1141 * EMP Firmware to the given PF. 1142 */ 1143 struct ice_aqc_query_txsched_res { 1144 u8 reserved[8]; 1145 __le32 addr_high; 1146 __le32 addr_low; 1147 }; 1148 1149 struct ice_aqc_generic_sched_props { 1150 __le16 phys_levels; 1151 __le16 logical_levels; 1152 u8 flattening_bitmap; 1153 u8 max_device_cgds; 1154 u8 max_pf_cgds; 1155 u8 rsvd0; 1156 __le16 rdma_qsets; 1157 u8 rsvd1[22]; 1158 }; 1159 1160 struct ice_aqc_layer_props { 1161 u8 logical_layer; 1162 u8 chunk_size; 1163 __le16 max_device_nodes; 1164 __le16 max_pf_nodes; 1165 u8 rsvd0[4]; 1166 __le16 max_sibl_grp_sz; 1167 __le16 max_cir_rl_profiles; 1168 __le16 max_eir_rl_profiles; 1169 __le16 max_srl_profiles; 1170 u8 rsvd1[14]; 1171 }; 1172 1173 struct ice_aqc_query_txsched_res_resp { 1174 struct ice_aqc_generic_sched_props sched_props; 1175 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1176 }; 1177 1178 /* Query Node to Root Topology (indirect 0x0413) 1179 * This command uses ice_aqc_get_elem as its data buffer. 1180 */ 1181 struct ice_aqc_query_node_to_root { 1182 __le32 teid; 1183 __le32 num_nodes; /* Response only */ 1184 __le32 addr_high; 1185 __le32 addr_low; 1186 }; 1187 1188 /* Get PHY capabilities (indirect 0x0600) */ 1189 struct ice_aqc_get_phy_caps { 1190 u8 lport_num; 1191 u8 reserved; 1192 __le16 param0; 1193 /* 18.0 - Report qualified modules */ 1194 #define ICE_AQC_GET_PHY_RQM BIT(0) 1195 /* 18.1 - 18.2 : Report mode 1196 * 00b - Report NVM capabilities 1197 * 01b - Report topology capabilities 1198 * 10b - Report SW configured 1199 */ 1200 #define ICE_AQC_REPORT_MODE_S 1 1201 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 1202 #define ICE_AQC_REPORT_NVM_CAP 0 1203 #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 1204 #define ICE_AQC_REPORT_SW_CFG BIT(2) 1205 __le32 reserved1; 1206 __le32 addr_high; 1207 __le32 addr_low; 1208 }; 1209 1210 /* This is #define of PHY type (Extended): 1211 * The first set of defines is for phy_type_low. 1212 */ 1213 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1214 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1215 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1216 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1217 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1218 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1219 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1220 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1221 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1222 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1223 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1224 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1225 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1226 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1227 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1228 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1229 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1230 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1231 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1232 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1233 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1234 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1235 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1236 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1237 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1238 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1239 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1240 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1241 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1242 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1243 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1244 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1245 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1246 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1247 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1248 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1249 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1250 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1251 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1252 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1253 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1254 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1255 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1256 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1257 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1258 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1259 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1260 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1261 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1262 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1263 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1264 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1265 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1266 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1267 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1268 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1269 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1270 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1271 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1272 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1273 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1274 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1275 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1276 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1277 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1278 /* The second set of defines is for phy_type_high. */ 1279 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1280 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1281 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1282 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1283 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1284 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 1285 1286 struct ice_aqc_get_phy_caps_data { 1287 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1288 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1289 u8 caps; 1290 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1291 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1292 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1293 #define ICE_AQC_PHY_EN_LINK BIT(3) 1294 #define ICE_AQC_PHY_AN_MODE BIT(4) 1295 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1296 #define ICE_AQC_PHY_EN_LESM BIT(6) 1297 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1298 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1299 u8 low_power_ctrl_an; 1300 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1301 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1302 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1303 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1304 __le16 eee_cap; 1305 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1306 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1307 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1308 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1309 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1310 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1311 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1312 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1313 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1314 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1315 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1316 __le16 eeer_value; 1317 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1318 u8 phy_fw_ver[8]; 1319 u8 link_fec_options; 1320 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1321 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1322 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1323 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1324 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1325 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1326 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1327 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1328 u8 module_compliance_enforcement; 1329 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1330 u8 extended_compliance_code; 1331 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1332 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1333 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1334 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1335 #define ICE_AQC_MOD_TYPE_IDENT 1 1336 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1337 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1338 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1339 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1340 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1341 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1342 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1343 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1344 u8 qualified_module_count; 1345 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1346 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1347 struct { 1348 u8 v_oui[3]; 1349 u8 rsvd3; 1350 u8 v_part[16]; 1351 __le32 v_rev; 1352 __le64 rsvd4; 1353 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1354 }; 1355 1356 /* Set PHY capabilities (direct 0x0601) 1357 * NOTE: This command must be followed by setup link and restart auto-neg 1358 */ 1359 struct ice_aqc_set_phy_cfg { 1360 u8 lport_num; 1361 u8 reserved[7]; 1362 __le32 addr_high; 1363 __le32 addr_low; 1364 }; 1365 1366 /* Set PHY config command data structure */ 1367 struct ice_aqc_set_phy_cfg_data { 1368 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1369 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1370 u8 caps; 1371 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 1372 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1373 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1374 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1375 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1376 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1377 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1378 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1379 u8 low_power_ctrl_an; 1380 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1381 __le16 eeer_value; 1382 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1383 u8 module_compliance_enforcement; 1384 }; 1385 1386 /* Set MAC Config command data structure (direct 0x0603) */ 1387 struct ice_aqc_set_mac_cfg { 1388 __le16 max_frame_size; 1389 u8 params; 1390 #define ICE_AQ_SET_MAC_PACE_S 3 1391 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1392 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1393 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1394 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1395 u8 tx_tmr_priority; 1396 __le16 tx_tmr_value; 1397 __le16 fc_refresh_threshold; 1398 u8 drop_opts; 1399 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1400 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1401 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1402 u8 reserved[7]; 1403 }; 1404 1405 /* Restart AN command data structure (direct 0x0605) 1406 * Also used for response, with only the lport_num field present. 1407 */ 1408 struct ice_aqc_restart_an { 1409 u8 lport_num; 1410 u8 reserved; 1411 u8 cmd_flags; 1412 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1413 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1414 u8 reserved2[13]; 1415 }; 1416 1417 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1418 struct ice_aqc_get_link_status { 1419 u8 lport_num; 1420 u8 reserved; 1421 __le16 cmd_flags; 1422 #define ICE_AQ_LSE_M 0x3 1423 #define ICE_AQ_LSE_NOP 0x0 1424 #define ICE_AQ_LSE_DIS 0x2 1425 #define ICE_AQ_LSE_ENA 0x3 1426 /* only response uses this flag */ 1427 #define ICE_AQ_LSE_IS_ENABLED 0x1 1428 __le32 reserved2; 1429 __le32 addr_high; 1430 __le32 addr_low; 1431 }; 1432 1433 /* Get link status response data structure, also used for Link Status Event */ 1434 struct ice_aqc_get_link_status_data { 1435 u8 topo_media_conflict; 1436 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1437 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1438 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1439 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1440 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1441 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1442 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1443 u8 link_cfg_err; 1444 #define ICE_AQ_LINK_CFG_ERR BIT(0) 1445 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2) 1446 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) 1447 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) 1448 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1449 u8 link_info; 1450 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1451 #define ICE_AQ_LINK_FAULT BIT(1) 1452 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1453 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1454 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1455 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1456 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1457 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1458 u8 an_info; 1459 #define ICE_AQ_AN_COMPLETED BIT(0) 1460 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1461 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1462 #define ICE_AQ_FEC_EN BIT(3) 1463 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1464 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1465 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1466 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1467 u8 ext_info; 1468 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1469 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1470 /* Port Tx Suspended */ 1471 #define ICE_AQ_LINK_TX_S 2 1472 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1473 #define ICE_AQ_LINK_TX_ACTIVE 0 1474 #define ICE_AQ_LINK_TX_DRAINED 1 1475 #define ICE_AQ_LINK_TX_FLUSHED 3 1476 u8 lb_status; 1477 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0) 1478 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1) 1479 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2) 1480 #define ICE_AQ_LINK_LB_PHY_IDX_S 3 1481 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S) 1482 __le16 max_frame_size; 1483 u8 cfg; 1484 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1485 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1486 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1487 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1488 /* Pacing Config */ 1489 #define ICE_AQ_CFG_PACING_S 3 1490 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1491 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1492 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1493 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1494 /* External Device Power Ability */ 1495 u8 power_desc; 1496 #define ICE_AQ_PWR_CLASS_M 0x3F 1497 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1498 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1499 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1500 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1501 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1502 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1503 __le16 link_speed; 1504 #define ICE_AQ_LINK_SPEED_M 0x7FF 1505 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1506 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1507 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1508 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1509 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1510 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1511 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1512 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1513 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1514 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1515 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1516 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1517 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1518 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1519 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1520 }; 1521 1522 /* Set event mask command (direct 0x0613) */ 1523 struct ice_aqc_set_event_mask { 1524 u8 lport_num; 1525 u8 reserved[7]; 1526 __le16 event_mask; 1527 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1528 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1529 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1530 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1531 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1532 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1533 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1534 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1535 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1536 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) 1537 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) 1538 u8 reserved1[6]; 1539 }; 1540 1541 /* Set MAC Loopback command (direct 0x0620) */ 1542 struct ice_aqc_set_mac_lb { 1543 u8 lb_mode; 1544 #define ICE_AQ_MAC_LB_EN BIT(0) 1545 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1546 u8 reserved[15]; 1547 }; 1548 1549 struct ice_aqc_link_topo_addr { 1550 u8 lport_num; 1551 u8 lport_num_valid; 1552 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1553 u8 node_type_ctx; 1554 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1555 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1556 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1557 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1558 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1559 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1560 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1561 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1562 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1563 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1564 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1565 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1566 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1567 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1568 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1569 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1570 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1571 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1572 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1573 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1574 u8 index; 1575 __le16 handle; 1576 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1577 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1578 /* Used to decode the handle field */ 1579 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1580 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1581 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1582 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1583 /* In case of a Mezzanine type */ 1584 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1585 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1586 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1587 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1588 /* In case of a LOM type */ 1589 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1590 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1591 }; 1592 1593 /* Get Link Topology Handle (direct, 0x06E0) */ 1594 struct ice_aqc_get_link_topo { 1595 struct ice_aqc_link_topo_addr addr; 1596 u8 node_part_num; 1597 u8 rsvd[9]; 1598 }; 1599 1600 /* Set Port Identification LED (direct, 0x06E9) */ 1601 struct ice_aqc_set_port_id_led { 1602 u8 lport_num; 1603 u8 lport_num_valid; 1604 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 1605 u8 ident_mode; 1606 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1607 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1608 u8 rsvd[13]; 1609 }; 1610 1611 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1612 struct ice_aqc_sff_eeprom { 1613 u8 lport_num; 1614 u8 lport_num_valid; 1615 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1616 __le16 i2c_bus_addr; 1617 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1618 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1619 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1620 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1621 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1622 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1623 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1624 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1625 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1626 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1627 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1628 __le16 i2c_mem_addr; 1629 __le16 eeprom_page; 1630 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1631 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1632 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1633 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1634 __le32 addr_high; 1635 __le32 addr_low; 1636 }; 1637 1638 /* SW Set GPIO command (indirect 0x6EF) 1639 * SW Get GPIO command (indirect 0x6F0) 1640 */ 1641 struct ice_aqc_sw_gpio { 1642 __le16 gpio_ctrl_handle; 1643 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0 1644 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S) 1645 u8 gpio_num; 1646 #define ICE_AQC_SW_GPIO_NUMBER_S 0 1647 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S) 1648 u8 gpio_params; 1649 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1) 1650 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0) 1651 u8 rsvd[12]; 1652 }; 1653 1654 /* NVM Read command (indirect 0x0701) 1655 * NVM Erase commands (direct 0x0702) 1656 * NVM Write commands (indirect 0x0703) 1657 * NVM Write Activate commands (direct 0x0707) 1658 * NVM Shadow RAM Dump commands (direct 0x0707) 1659 */ 1660 struct ice_aqc_nvm { 1661 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1662 __le16 offset_low; 1663 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 1664 u8 cmd_flags; 1665 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1666 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 1667 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ 1668 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1669 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1670 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1671 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1672 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1673 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1674 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1675 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1676 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1677 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1678 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) 1679 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1680 #define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */ 1681 #define ICE_AQC_NVM_PERST_FLAG 1 1682 #define ICE_AQC_NVM_EMPR_FLAG 2 1683 __le16 module_typeid; 1684 __le16 length; 1685 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1686 __le32 addr_high; 1687 __le32 addr_low; 1688 }; 1689 1690 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ 1691 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */ 1692 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */ 1693 1694 #define ICE_AQC_NVM_START_POINT 0 1695 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90 1696 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */ 1697 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0) 1698 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15 1699 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15) 1700 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1 1701 1702 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46 1703 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */ 1704 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 1705 1706 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129 1707 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */ 1708 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0) 1709 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ 1710 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ 1711 1712 /* The result of netlist NVM read comes in a TLV format. The actual data 1713 * (netlist header) starts from word offset 1 (byte 2). The FW strips 1714 * out the type field from the TLV header so all the netlist fields 1715 * should adjust their offset value by 1 word (2 bytes) in order to map 1716 * their correct location. 1717 */ 1718 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B 1719 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1 1720 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */ 1721 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2 1722 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */ 1723 #define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5 1724 #define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */ 1725 1726 /* netlist ID block field offsets (word offsets) */ 1727 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2 1728 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3 1729 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4 1730 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5 1731 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6 1732 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7 1733 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8 1734 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9 1735 #define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA 1736 #define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F 1737 1738 /* Used for 0x0704 as well as for 0x0705 commands */ 1739 struct ice_aqc_nvm_cfg { 1740 u8 cmd_flags; 1741 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 1742 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 1743 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 1744 u8 reserved; 1745 __le16 count; 1746 __le16 id; 1747 u8 reserved1[2]; 1748 __le32 addr_high; 1749 __le32 addr_low; 1750 }; 1751 1752 struct ice_aqc_nvm_cfg_data { 1753 __le16 field_id; 1754 __le16 field_options; 1755 __le16 field_value; 1756 }; 1757 1758 /* NVM Checksum Command (direct, 0x0706) */ 1759 struct ice_aqc_nvm_checksum { 1760 u8 flags; 1761 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1762 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1763 u8 rsvd; 1764 __le16 checksum; /* Used only by response */ 1765 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1766 u8 rsvd2[12]; 1767 }; 1768 1769 /* Get LLDP MIB (indirect 0x0A00) 1770 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1771 * as the format is the same. 1772 */ 1773 struct ice_aqc_lldp_get_mib { 1774 u8 type; 1775 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1776 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1777 #define ICE_AQ_LLDP_MIB_LOCAL 0 1778 #define ICE_AQ_LLDP_MIB_REMOTE 1 1779 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1780 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1781 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1782 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1783 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1784 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1785 #define ICE_AQ_LLDP_TX_S 0x4 1786 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1787 #define ICE_AQ_LLDP_TX_ACTIVE 0 1788 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1789 #define ICE_AQ_LLDP_TX_FLUSHED 3 1790 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1791 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1792 * Get LLDP MIB (0x0A00) response only. 1793 */ 1794 u8 reserved1; 1795 __le16 local_len; 1796 __le16 remote_len; 1797 u8 reserved2[2]; 1798 __le32 addr_high; 1799 __le32 addr_low; 1800 }; 1801 1802 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1803 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1804 struct ice_aqc_lldp_set_mib_change { 1805 u8 command; 1806 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1807 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1808 u8 reserved[15]; 1809 }; 1810 1811 /* Add LLDP TLV (indirect 0x0A02) 1812 * Delete LLDP TLV (indirect 0x0A04) 1813 */ 1814 struct ice_aqc_lldp_add_delete_tlv { 1815 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1816 u8 reserved1[1]; 1817 __le16 len; 1818 u8 reserved2[4]; 1819 __le32 addr_high; 1820 __le32 addr_low; 1821 }; 1822 1823 /* Update LLDP TLV (indirect 0x0A03) */ 1824 struct ice_aqc_lldp_update_tlv { 1825 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1826 u8 reserved; 1827 __le16 old_len; 1828 __le16 new_offset; 1829 __le16 new_len; 1830 __le32 addr_high; 1831 __le32 addr_low; 1832 }; 1833 1834 /* Stop LLDP (direct 0x0A05) */ 1835 struct ice_aqc_lldp_stop { 1836 u8 command; 1837 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1838 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1839 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1840 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1841 u8 reserved[15]; 1842 }; 1843 1844 /* Start LLDP (direct 0x0A06) */ 1845 struct ice_aqc_lldp_start { 1846 u8 command; 1847 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1848 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1849 u8 reserved[15]; 1850 }; 1851 1852 /* Get CEE DCBX Oper Config (0x0A07) 1853 * The command uses the generic descriptor struct and 1854 * returns the struct below as an indirect response. 1855 */ 1856 struct ice_aqc_get_cee_dcb_cfg_resp { 1857 u8 oper_num_tc; 1858 u8 oper_prio_tc[4]; 1859 u8 oper_tc_bw[8]; 1860 u8 oper_pfc_en; 1861 __le16 oper_app_prio; 1862 #define ICE_AQC_CEE_APP_FCOE_S 0 1863 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1864 #define ICE_AQC_CEE_APP_ISCSI_S 3 1865 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1866 #define ICE_AQC_CEE_APP_FIP_S 8 1867 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1868 __le32 tlv_status; 1869 #define ICE_AQC_CEE_PG_STATUS_S 0 1870 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1871 #define ICE_AQC_CEE_PFC_STATUS_S 3 1872 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1873 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1874 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1875 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1876 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1877 #define ICE_AQC_CEE_FIP_STATUS_S 16 1878 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1879 u8 reserved[12]; 1880 }; 1881 1882 /* Set Local LLDP MIB (indirect 0x0A08) 1883 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1884 */ 1885 struct ice_aqc_lldp_set_local_mib { 1886 u8 type; 1887 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1888 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1889 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1890 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1891 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1892 u8 reserved0; 1893 __le16 length; 1894 u8 reserved1[4]; 1895 __le32 addr_high; 1896 __le32 addr_low; 1897 }; 1898 1899 struct ice_aqc_lldp_set_local_mib_resp { 1900 u8 status; 1901 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0) 1902 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0 1903 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M 1904 u8 reserved[15]; 1905 }; 1906 1907 /* Stop/Start LLDP Agent (direct 0x0A09) 1908 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1909 * The same structure is used for the response, with the command field 1910 * being used as the status field. 1911 */ 1912 struct ice_aqc_lldp_stop_start_specific_agent { 1913 u8 command; 1914 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1915 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1916 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1917 u8 reserved[15]; 1918 }; 1919 1920 /* LLDP Filter Control (direct 0x0A0A) */ 1921 struct ice_aqc_lldp_filter_ctrl { 1922 u8 cmd_flags; 1923 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0) 1924 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 1925 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 1926 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2 1927 u8 reserved1; 1928 __le16 vsi_num; 1929 u8 reserved2[12]; 1930 }; 1931 1932 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1933 struct ice_aqc_get_set_rss_key { 1934 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1935 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1936 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1937 __le16 vsi_id; 1938 u8 reserved[6]; 1939 __le32 addr_high; 1940 __le32 addr_low; 1941 }; 1942 1943 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1944 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1945 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1946 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1947 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1948 1949 /** 1950 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer 1951 * @standard_rss_key: 40 most significant bytes of hash key 1952 * @extended_hash_key: 12 least significant bytes of hash key 1953 * 1954 * Set/Get 40 byte hash key using standard_rss_key field, and set 1955 * extended_hash_key field to zero. Set/Get 52 byte hash key using 1956 * standard_rss_key field for 40 most significant bytes and the 1957 * extended_hash_key field for the 12 least significant bytes of hash key. 1958 */ 1959 struct ice_aqc_get_set_rss_keys { 1960 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1961 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1962 }; 1963 1964 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1965 struct ice_aqc_get_set_rss_lut { 1966 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1967 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1968 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1969 __le16 vsi_id; 1970 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1971 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1972 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1973 1974 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1975 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1976 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1977 1978 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1979 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1980 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1981 1982 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1983 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1984 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1985 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1986 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1987 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1988 1989 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1990 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1991 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1992 1993 __le16 flags; 1994 __le32 reserved; 1995 __le32 addr_high; 1996 __le32 addr_low; 1997 }; 1998 1999 /* Clear FD Table Command (direct, 0x0B06) */ 2000 struct ice_aqc_clear_fd_table { 2001 u8 clear_type; 2002 #define CL_FD_VM_VF_TYPE_VSI_IDX 1 2003 #define CL_FD_VM_VF_TYPE_PF_IDX 2 2004 u8 rsvd; 2005 __le16 vsi_index; 2006 u8 reserved[12]; 2007 }; 2008 2009 /* Allocate ACL table (indirect 0x0C10) */ 2010 #define ICE_AQC_ACL_KEY_WIDTH 40 2011 #define ICE_AQC_ACL_KEY_WIDTH_BYTES 5 2012 #define ICE_AQC_ACL_TCAM_DEPTH 512 2013 #define ICE_ACL_ENTRY_ALLOC_UNIT 64 2014 #define ICE_AQC_MAX_CONCURRENT_ACL_TBL 15 2015 #define ICE_AQC_MAX_ACTION_MEMORIES 20 2016 #define ICE_AQC_MAX_ACTION_ENTRIES 512 2017 #define ICE_AQC_ACL_SLICES 16 2018 #define ICE_AQC_ALLOC_ID_LESS_THAN_4K 0x1000 2019 /* The ACL block supports up to 8 actions per a single output. */ 2020 #define ICE_AQC_TBL_MAX_ACTION_PAIRS 4 2021 2022 #define ICE_AQC_MAX_TCAM_ALLOC_UNITS (ICE_AQC_ACL_TCAM_DEPTH / \ 2023 ICE_ACL_ENTRY_ALLOC_UNIT) 2024 #define ICE_AQC_ACL_ALLOC_UNITS (ICE_AQC_ACL_SLICES * \ 2025 ICE_AQC_MAX_TCAM_ALLOC_UNITS) 2026 2027 struct ice_aqc_acl_alloc_table { 2028 __le16 table_width; 2029 __le16 table_depth; 2030 u8 act_pairs_per_entry; 2031 /* For non-concurrent table allocation, this field needs 2032 * to be set to zero(0) otherwise it shall specify the 2033 * amount of concurrent tables whose AllocIDs are 2034 * specified in buffer. Thus the newly allocated table 2035 * is concurrent with table IDs specified in AllocIDs. 2036 */ 2037 #define ICE_AQC_ACL_ALLOC_TABLE_TYPE_NONCONCURR 0 2038 u8 table_type; 2039 __le16 reserved; 2040 __le32 addr_high; 2041 __le32 addr_low; 2042 }; 2043 2044 /* Allocate ACL table command buffer format */ 2045 struct ice_aqc_acl_alloc_table_data { 2046 /* Dependent table AllocIDs. Each word in this 15 word array specifies 2047 * a dependent table AllocID according to the amount specified in the 2048 * "table_type" field. All unused words shall be set to 0xFFFF 2049 */ 2050 #define ICE_AQC_CONCURR_ID_INVALID 0xffff 2051 __le16 alloc_ids[ICE_AQC_MAX_CONCURRENT_ACL_TBL]; 2052 }; 2053 2054 /* Deallocate ACL table (indirect 0x0C11) 2055 * Allocate ACL action-pair (indirect 0x0C12) 2056 * Deallocate ACL action-pair (indirect 0x0C13) 2057 */ 2058 2059 /* Following structure is common and used in case of deallocation 2060 * of ACL table and action-pair 2061 */ 2062 struct ice_aqc_acl_tbl_actpair { 2063 /* Alloc ID of the table being released */ 2064 __le16 alloc_id; 2065 u8 reserved[6]; 2066 __le32 addr_high; 2067 __le32 addr_low; 2068 }; 2069 2070 /* This response structure is same in case of alloc/dealloc table, 2071 * alloc/dealloc action-pair 2072 */ 2073 struct ice_aqc_acl_generic { 2074 /* if alloc_id is below 0x1000 then alllocation failed due to 2075 * unavailable resources, else this is set by FW to identify 2076 * table allocation 2077 */ 2078 __le16 alloc_id; 2079 2080 union { 2081 /* to be used only in case of alloc/dealloc table */ 2082 struct { 2083 /* Index of the first TCAM block, otherwise set to 0xFF 2084 * for a failed allocation 2085 */ 2086 u8 first_tcam; 2087 /* Index of the last TCAM block. This index shall be 2088 * set to the value of first_tcam for single TCAM block 2089 * allocation, otherwise set to 0xFF for a failed 2090 * allocation 2091 */ 2092 u8 last_tcam; 2093 } table; 2094 /* reserved in case of alloc/dealloc action-pair */ 2095 struct { 2096 __le16 reserved; 2097 } act_pair; 2098 } ops; 2099 2100 /* index of first entry (in both TCAM and action memories), 2101 * otherwise set to 0xFF for a failed allocation 2102 */ 2103 __le16 first_entry; 2104 /* index of last entry (in both TCAM and action memories), 2105 * otherwise set to 0xFF for a failed allocation 2106 */ 2107 __le16 last_entry; 2108 2109 /* Each act_mem element specifies the order of the memory 2110 * otherwise 0xFF 2111 */ 2112 u8 act_mem[ICE_AQC_MAX_ACTION_MEMORIES]; 2113 }; 2114 2115 /* Allocate ACL scenario (indirect 0x0C14). This command doesn't have separate 2116 * response buffer since original command buffer gets updated with 2117 * 'scen_id' in case of success 2118 */ 2119 struct ice_aqc_acl_alloc_scen { 2120 union { 2121 struct { 2122 u8 reserved[8]; 2123 } cmd; 2124 struct { 2125 __le16 scen_id; 2126 u8 reserved[6]; 2127 } resp; 2128 } ops; 2129 __le32 addr_high; 2130 __le32 addr_low; 2131 }; 2132 2133 /* De-allocate ACL scenario (direct 0x0C15). This command doesn't need 2134 * separate response buffer since nothing to be returned as a response 2135 * except status. 2136 */ 2137 struct ice_aqc_acl_dealloc_scen { 2138 __le16 scen_id; 2139 u8 reserved[14]; 2140 }; 2141 2142 /* Update ACL scenario (direct 0x0C1B) 2143 * Query ACL scenario (direct 0x0C23) 2144 */ 2145 struct ice_aqc_acl_update_query_scen { 2146 __le16 scen_id; 2147 u8 reserved[6]; 2148 __le32 addr_high; 2149 __le32 addr_low; 2150 }; 2151 2152 /* Input buffer format in case allocate/update ACL scenario and same format 2153 * is used for response buffer in case of query ACL scenario. 2154 * NOTE: de-allocate ACL scenario is direct command and doesn't require 2155 * "buffer", hence no buffer format. 2156 */ 2157 struct ice_aqc_acl_scen { 2158 struct { 2159 /* Byte [x] selection for the TCAM key. This value must be 2160 * set to 0x0 for unusued TCAM. 2161 * Only Bit 6..0 is used in each byte and MSB is reserved 2162 */ 2163 #define ICE_AQC_ACL_ALLOC_SCE_SELECT_M 0x7F 2164 #define ICE_AQC_ACL_BYTE_SEL_BASE 0x20 2165 #define ICE_AQC_ACL_BYTE_SEL_BASE_PID 0x3E 2166 #define ICE_AQC_ACL_BYTE_SEL_BASE_PKT_DIR ICE_AQC_ACL_BYTE_SEL_BASE 2167 #define ICE_AQC_ACL_BYTE_SEL_BASE_RNG_CHK 0x3F 2168 u8 tcam_select[5]; 2169 /* TCAM Block entry masking. This value should be set to 0x0 for 2170 * unused TCAM 2171 */ 2172 u8 chnk_msk; 2173 /* Bit 0 : masks TCAM entries 0-63 2174 * Bit 1 : masks TCAM entries 64-127 2175 * Bit 2 to 7 : follow the pattern of bit 0 and 1 2176 */ 2177 #define ICE_AQC_ACL_ALLOC_SCE_START_CMP BIT(0) 2178 #define ICE_AQC_ACL_ALLOC_SCE_START_SET BIT(1) 2179 u8 start_cmp_set; 2180 2181 } tcam_cfg[ICE_AQC_ACL_SLICES]; 2182 2183 /* Each byte, Bit 6..0: Action memory association to a TCAM block, 2184 * otherwise it shall be set to 0x0 for disabled memory action. 2185 * Bit 7 : Action memory enable for this scenario 2186 */ 2187 #define ICE_AQC_ACL_SCE_ACT_MEM_TCAM_ASSOC_M 0x7F 2188 #define ICE_AQC_ACL_SCE_ACT_MEM_EN BIT(7) 2189 u8 act_mem_cfg[ICE_AQC_MAX_ACTION_MEMORIES]; 2190 }; 2191 2192 /* Allocate ACL counters (indirect 0x0C16) */ 2193 struct ice_aqc_acl_alloc_counters { 2194 /* Amount of contiguous counters requested. Min value is 1 and 2195 * max value is 255 2196 */ 2197 #define ICE_AQC_ACL_ALLOC_CNT_MIN_AMT 0x1 2198 #define ICE_AQC_ACL_ALLOC_CNT_MAX_AMT 0xFF 2199 u8 counter_amount; 2200 2201 /* Counter type: 'single counter' which can be configured to count 2202 * either bytes or packets 2203 */ 2204 #define ICE_AQC_ACL_CNT_TYPE_SINGLE 0x0 2205 2206 /* Counter type: 'counter pair' which counts number of bytes and number 2207 * of packets. 2208 */ 2209 #define ICE_AQC_ACL_CNT_TYPE_DUAL 0x1 2210 /* requested counter type, single/dual */ 2211 u8 counters_type; 2212 2213 /* counter bank allocation shall be 0-3 for 'byte or packet counter' */ 2214 #define ICE_AQC_ACL_MAX_CNT_SINGLE 0x3 2215 /* counter bank allocation shall be 0-1 for 'byte and packet counter dual' */ 2216 #define ICE_AQC_ACL_MAX_CNT_DUAL 0x1 2217 /* requested counter bank allocation */ 2218 u8 bank_alloc; 2219 2220 u8 reserved; 2221 2222 union { 2223 /* Applicable only in case of command */ 2224 struct { 2225 u8 reserved[12]; 2226 } cmd; 2227 /* Applicable only in case of response */ 2228 #define ICE_AQC_ACL_ALLOC_CNT_INVAL 0xFFFF 2229 struct { 2230 /* Index of first allocated counter. 0xFFFF in case 2231 * of unsuccessful allocation 2232 */ 2233 __le16 first_counter; 2234 /* Index of last allocated counter. 0xFFFF in case 2235 * of unsuccessful allocation 2236 */ 2237 __le16 last_counter; 2238 u8 rsvd[8]; 2239 } resp; 2240 } ops; 2241 }; 2242 2243 /* De-allocate ACL counters (direct 0x0C17) */ 2244 struct ice_aqc_acl_dealloc_counters { 2245 /* first counter being released */ 2246 __le16 first_counter; 2247 /* last counter being released */ 2248 __le16 last_counter; 2249 /* requested counter type, single/dual */ 2250 u8 counters_type; 2251 /* requested counter bank allocation */ 2252 u8 bank_alloc; 2253 u8 reserved[10]; 2254 }; 2255 2256 /* De-allocate ACL resources (direct 0x0C1A). Used by SW to release all the 2257 * resources allocated for it using a single command 2258 */ 2259 struct ice_aqc_acl_dealloc_res { 2260 u8 reserved[16]; 2261 }; 2262 2263 /* Program ACL actionpair (indirect 0x0C1C) 2264 * Query ACL actionpair (indirect 0x0C25) 2265 */ 2266 struct ice_aqc_acl_actpair { 2267 /* action mem index to program/update */ 2268 u8 act_mem_index; 2269 u8 reserved; 2270 /* The entry index in action memory to be programmed/updated */ 2271 __le16 act_entry_index; 2272 __le32 reserved2; 2273 __le32 addr_high; 2274 __le32 addr_low; 2275 }; 2276 2277 /* Input buffer format for program/query action-pair admin command */ 2278 struct ice_acl_act_entry { 2279 /* Action priority, values must be between 0..7 */ 2280 #define ICE_AQC_ACT_PRIO_VALID_MAX 7 2281 #define ICE_AQC_ACT_PRIO_MSK MAKEMASK(0xff, 0) 2282 u8 prio; 2283 /* Action meta-data identifier. This field should be set to 0x0 2284 * for a NOP action 2285 */ 2286 #define ICE_AQC_ACT_MDID_S 8 2287 #define ICE_AQC_ACT_MDID_MSK MAKEMASK(0xff00, ICE_AQC_ACT_MDID_S) 2288 u8 mdid; 2289 /* Action value */ 2290 #define ICE_AQC_ACT_VALUE_S 16 2291 #define ICE_AQC_ACT_VALUE_MSK MAKEMASK(0xffff0000, 16) 2292 __le16 value; 2293 }; 2294 2295 #define ICE_ACL_NUM_ACT_PER_ACT_PAIR 2 2296 struct ice_aqc_actpair { 2297 struct ice_acl_act_entry act[ICE_ACL_NUM_ACT_PER_ACT_PAIR]; 2298 }; 2299 2300 /* Generic format used to describe either input or response buffer 2301 * for admin commands related to ACL profile 2302 */ 2303 struct ice_aqc_acl_prof_generic_frmt { 2304 /* The first byte of the byte selection base is reserved to keep the 2305 * first byte of the field vector where the packet direction info is 2306 * available. Thus we should start at index 1 of the field vector to 2307 * map its entries to the byte selection base. 2308 */ 2309 #define ICE_AQC_ACL_PROF_BYTE_SEL_START_IDX 1 2310 /* In each byte: 2311 * Bit 0..5 = Byte selection for the byte selection base from the 2312 * extracted fields (expressed as byte offset in extracted fields). 2313 * Applicable values are 0..63 2314 * Bit 6..7 = Reserved 2315 */ 2316 #define ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS 30 2317 u8 byte_selection[ICE_AQC_ACL_PROF_BYTE_SEL_ELEMS]; 2318 /* In each byte: 2319 * Bit 0..4 = Word selection for the word selection base from the 2320 * extracted fields (expressed as word offset in extracted fields). 2321 * Applicable values are 0..31 2322 * Bit 5..7 = Reserved 2323 */ 2324 #define ICE_AQC_ACL_PROF_WORD_SEL_ELEMS 32 2325 u8 word_selection[ICE_AQC_ACL_PROF_WORD_SEL_ELEMS]; 2326 /* In each byte: 2327 * Bit 0..3 = Double word selection for the double-word selection base 2328 * from the extracted fields (expressed as double-word offset in 2329 * extracted fields). 2330 * Applicable values are 0..15 2331 * Bit 4..7 = Reserved 2332 */ 2333 #define ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS 15 2334 u8 dword_selection[ICE_AQC_ACL_PROF_DWORD_SEL_ELEMS]; 2335 /* Scenario numbers for individual Physical Function's */ 2336 #define ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS 8 2337 u8 pf_scenario_num[ICE_AQC_ACL_PROF_PF_SCEN_NUM_ELEMS]; 2338 }; 2339 2340 /* Program ACL profile extraction (indirect 0x0C1D) 2341 * Program ACL profile ranges (indirect 0x0C1E) 2342 * Query ACL profile (indirect 0x0C21) 2343 * Query ACL profile ranges (indirect 0x0C22) 2344 */ 2345 struct ice_aqc_acl_profile { 2346 u8 profile_id; /* Programmed/Updated profile ID */ 2347 u8 reserved[7]; 2348 __le32 addr_high; 2349 __le32 addr_low; 2350 }; 2351 2352 /* Input buffer format for program profile extraction admin command and 2353 * response buffer format for query profile admin command is as defined 2354 * in struct ice_aqc_acl_prof_generic_frmt 2355 */ 2356 2357 /* Input buffer format for program profile ranges and query profile ranges 2358 * admin commands. Same format is used for response buffer in case of query 2359 * profile ranges command 2360 */ 2361 struct ice_acl_rng_data { 2362 /* The range checker output shall be sent when the value 2363 * related to this range checker is lower than low boundary 2364 */ 2365 __be16 low_boundary; 2366 /* The range checker output shall be sent when the value 2367 * related to this range checker is higher than high boundary 2368 */ 2369 __be16 high_boundary; 2370 /* A value of '0' in bit shall clear the relevant bit input 2371 * to the range checker 2372 */ 2373 __be16 mask; 2374 }; 2375 2376 struct ice_aqc_acl_profile_ranges { 2377 #define ICE_AQC_ACL_PROF_RANGES_NUM_CFG 8 2378 struct ice_acl_rng_data checker_cfg[ICE_AQC_ACL_PROF_RANGES_NUM_CFG]; 2379 }; 2380 2381 /* Program ACL entry (indirect 0x0C20) 2382 * Query ACL entry (indirect 0x0C24) 2383 */ 2384 struct ice_aqc_acl_entry { 2385 u8 tcam_index; /* Updated TCAM block index */ 2386 u8 reserved; 2387 __le16 entry_index; /* Updated entry index */ 2388 __le32 reserved2; 2389 __le32 addr_high; 2390 __le32 addr_low; 2391 }; 2392 2393 /* Input buffer format in case of program ACL entry and response buffer format 2394 * in case of query ACL entry 2395 */ 2396 struct ice_aqc_acl_data { 2397 /* Entry key and entry key invert are 40 bits wide. 2398 * Byte 0..4 : entry key and Byte 5..7 are reserved 2399 * Byte 8..12: entry key invert and Byte 13..15 are reserved 2400 */ 2401 struct { 2402 u8 val[5]; 2403 u8 reserved[3]; 2404 } entry_key, entry_key_invert; 2405 }; 2406 2407 /* Query ACL counter (direct 0x0C27) */ 2408 struct ice_aqc_acl_query_counter { 2409 /* Queried counter index */ 2410 __le16 counter_index; 2411 /* Queried counter bank */ 2412 u8 counter_bank; 2413 union { 2414 struct { 2415 u8 reserved[13]; 2416 } cmd; 2417 struct { 2418 /* Holds counter value/packet counter value */ 2419 u8 val[5]; 2420 u8 reserved[8]; 2421 } resp; 2422 } ops; 2423 }; 2424 2425 /* Add Tx LAN Queues (indirect 0x0C30) */ 2426 struct ice_aqc_add_txqs { 2427 u8 num_qgrps; 2428 u8 reserved[3]; 2429 __le32 reserved1; 2430 __le32 addr_high; 2431 __le32 addr_low; 2432 }; 2433 2434 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 2435 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 2436 */ 2437 struct ice_aqc_add_txqs_perq { 2438 __le16 txq_id; 2439 u8 rsvd[2]; 2440 __le32 q_teid; 2441 u8 txq_ctx[22]; 2442 u8 rsvd2[2]; 2443 struct ice_aqc_txsched_elem info; 2444 }; 2445 2446 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2447 * is an array of the following structs. Please note that the length of 2448 * each struct ice_aqc_add_tx_qgrp is variable due 2449 * to the variable number of queues in each group! 2450 */ 2451 struct ice_aqc_add_tx_qgrp { 2452 __le32 parent_teid; 2453 u8 num_txqs; 2454 u8 rsvd[3]; 2455 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN]; 2456 }; 2457 2458 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2459 struct ice_aqc_dis_txqs { 2460 u8 cmd_type; 2461 #define ICE_AQC_Q_DIS_CMD_S 0 2462 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2463 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2464 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2465 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2466 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2467 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2468 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2469 u8 num_entries; 2470 __le16 vmvf_and_timeout; 2471 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2472 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2473 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2474 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2475 __le32 blocked_cgds; 2476 __le32 addr_high; 2477 __le32 addr_low; 2478 }; 2479 2480 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2481 * contains the following structures, arrayed one after the 2482 * other. 2483 * Note: Since the q_id is 16 bits wide, if the 2484 * number of queues is even, then 2 bytes of alignment MUST be 2485 * added before the start of the next group, to allow correct 2486 * alignment of the parent_teid field. 2487 */ 2488 #pragma pack(1) 2489 struct ice_aqc_dis_txq_item { 2490 __le32 parent_teid; 2491 u8 num_qs; 2492 u8 rsvd; 2493 /* The length of the q_id array varies according to num_qs */ 2494 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2495 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2496 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2497 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2498 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2499 __le16 q_id[STRUCT_HACK_VAR_LEN]; 2500 }; 2501 2502 #pragma pack() 2503 2504 /* Tx LAN Queues Cleanup Event (0x0C31) */ 2505 struct ice_aqc_txqs_cleanup { 2506 __le16 caller_opc; 2507 __le16 cmd_tag; 2508 u8 reserved[12]; 2509 }; 2510 2511 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ 2512 struct ice_aqc_move_txqs { 2513 u8 cmd_type; 2514 #define ICE_AQC_Q_CMD_TYPE_S 0 2515 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 2516 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 2517 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 2518 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 2519 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 2520 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 2521 u8 num_qs; 2522 u8 rsvd; 2523 u8 timeout; 2524 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 2525 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 2526 __le32 blocked_cgds; 2527 __le32 addr_high; 2528 __le32 addr_low; 2529 }; 2530 2531 /* Per-queue data buffer for the Move Tx LAN Queues command/response */ 2532 struct ice_aqc_move_txqs_elem { 2533 __le16 txq_id; 2534 u8 q_cgd; 2535 u8 rsvd; 2536 __le32 q_teid; 2537 }; 2538 2539 /* Indirect data buffer for the Move Tx LAN Queues command/response */ 2540 struct ice_aqc_move_txqs_data { 2541 __le32 src_teid; 2542 __le32 dest_teid; 2543 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN]; 2544 }; 2545 2546 /* Download Package (indirect 0x0C40) */ 2547 /* Also used for Update Package (indirect 0x0C42 and 0x0C41) */ 2548 struct ice_aqc_download_pkg { 2549 u8 flags; 2550 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2551 u8 reserved[3]; 2552 __le32 reserved1; 2553 __le32 addr_high; 2554 __le32 addr_low; 2555 }; 2556 2557 struct ice_aqc_download_pkg_resp { 2558 __le32 error_offset; 2559 __le32 error_info; 2560 __le32 addr_high; 2561 __le32 addr_low; 2562 }; 2563 2564 /* Get Package Info List (indirect 0x0C43) */ 2565 struct ice_aqc_get_pkg_info_list { 2566 __le32 reserved1; 2567 __le32 reserved2; 2568 __le32 addr_high; 2569 __le32 addr_low; 2570 }; 2571 2572 /* Version format for packages */ 2573 struct ice_pkg_ver { 2574 u8 major; 2575 u8 minor; 2576 u8 update; 2577 u8 draft; 2578 }; 2579 2580 #define ICE_PKG_NAME_SIZE 32 2581 #define ICE_SEG_ID_SIZE 28 2582 #define ICE_SEG_NAME_SIZE 28 2583 2584 struct ice_aqc_get_pkg_info { 2585 struct ice_pkg_ver ver; 2586 char name[ICE_SEG_NAME_SIZE]; 2587 __le32 track_id; 2588 u8 is_in_nvm; 2589 u8 is_active; 2590 u8 is_active_at_boot; 2591 u8 is_modified; 2592 }; 2593 2594 /* Get Package Info List response buffer format (0x0C43) */ 2595 struct ice_aqc_get_pkg_info_resp { 2596 __le32 count; 2597 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN]; 2598 }; 2599 2600 /* Driver Shared Parameters (direct, 0x0C90) */ 2601 struct ice_aqc_driver_shared_params { 2602 u8 set_or_get_op; 2603 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2604 #define ICE_AQC_DRIVER_PARAM_SET 0 2605 #define ICE_AQC_DRIVER_PARAM_GET 1 2606 u8 param_indx; 2607 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2608 u8 rsvd[2]; 2609 __le32 param_val; 2610 __le32 addr_high; 2611 __le32 addr_low; 2612 }; 2613 2614 /* Lan Queue Overflow Event (direct, 0x1001) */ 2615 struct ice_aqc_event_lan_overflow { 2616 __le32 prtdcb_ruptq; 2617 __le32 qtx_ctl; 2618 u8 reserved[8]; 2619 }; 2620 2621 /* Set Health Status (direct 0xFF20) */ 2622 struct ice_aqc_set_health_status_config { 2623 u8 event_source; 2624 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0) 2625 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1) 2626 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2) 2627 u8 reserved[15]; 2628 }; 2629 2630 /* Get Health Status codes (indirect 0xFF21) */ 2631 struct ice_aqc_get_supported_health_status_codes { 2632 __le16 health_code_count; 2633 u8 reserved[6]; 2634 __le32 addr_high; 2635 __le32 addr_low; 2636 }; 2637 2638 /* Get Health Status (indirect 0xFF22) */ 2639 struct ice_aqc_get_health_status { 2640 __le16 health_status_count; 2641 u8 reserved[6]; 2642 __le32 addr_high; 2643 __le32 addr_low; 2644 }; 2645 2646 /* Get Health Status event buffer entry, (0xFF22) 2647 * repeated per reported health status 2648 */ 2649 struct ice_aqc_health_status_elem { 2650 __le16 health_status_code; 2651 __le16 event_source; 2652 #define ICE_AQC_HEALTH_STATUS_PF (0x1) 2653 #define ICE_AQC_HEALTH_STATUS_PORT (0x2) 2654 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3) 2655 __le32 internal_data1; 2656 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF) 2657 __le32 internal_data2; 2658 }; 2659 2660 /* Clear Health Status (direct 0xFF23) */ 2661 struct ice_aqc_clear_health_status { 2662 __le32 reserved[4]; 2663 }; 2664 2665 /** 2666 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2667 * @flags: ICE_AQ_FLAG_* flags 2668 * @opcode: AQ command opcode 2669 * @datalen: length in bytes of indirect/external data buffer 2670 * @retval: return value from firmware 2671 * @cookie_high: opaque data high-half 2672 * @cookie_low: opaque data low-half 2673 * @params: command-specific parameters 2674 * 2675 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2676 * (ATQ). The firmware writes back onto the command descriptor and returns 2677 * the result of the command. Asynchronous events that are not an immediate 2678 * result of the command are written to the Admin Receive Queue (ARQ) using 2679 * the same descriptor format. Descriptors are in little-endian notation with 2680 * 32-bit words. 2681 */ 2682 struct ice_aq_desc { 2683 __le16 flags; 2684 __le16 opcode; 2685 __le16 datalen; 2686 __le16 retval; 2687 __le32 cookie_high; 2688 __le32 cookie_low; 2689 union { 2690 u8 raw[16]; 2691 struct ice_aqc_generic generic; 2692 struct ice_aqc_get_ver get_ver; 2693 struct ice_aqc_driver_ver driver_ver; 2694 struct ice_aqc_q_shutdown q_shutdown; 2695 struct ice_aqc_req_res res_owner; 2696 struct ice_aqc_manage_mac_read mac_read; 2697 struct ice_aqc_manage_mac_write mac_write; 2698 struct ice_aqc_clear_pxe clear_pxe; 2699 struct ice_aqc_config_no_drop_policy no_drop; 2700 struct ice_aqc_add_update_mir_rule add_update_rule; 2701 struct ice_aqc_delete_mir_rule del_rule; 2702 struct ice_aqc_list_caps get_cap; 2703 struct ice_aqc_get_phy_caps get_phy; 2704 struct ice_aqc_set_phy_cfg set_phy; 2705 struct ice_aqc_restart_an restart_an; 2706 struct ice_aqc_sff_eeprom read_write_sff_param; 2707 struct ice_aqc_set_port_id_led set_port_id_led; 2708 struct ice_aqc_get_sw_cfg get_sw_conf; 2709 struct ice_aqc_sw_rules sw_rules; 2710 struct ice_aqc_storm_cfg storm_conf; 2711 struct ice_aqc_add_get_recipe add_get_recipe; 2712 struct ice_aqc_recipe_to_profile recipe_to_profile; 2713 struct ice_aqc_get_topo get_topo; 2714 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2715 struct ice_aqc_query_txsched_res query_sched_res; 2716 struct ice_aqc_query_node_to_root query_node_to_root; 2717 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 2718 struct ice_aqc_query_port_ets port_ets; 2719 struct ice_aqc_rl_profile rl_profile; 2720 struct ice_aqc_nvm nvm; 2721 struct ice_aqc_nvm_cfg nvm_cfg; 2722 struct ice_aqc_nvm_checksum nvm_checksum; 2723 struct ice_aqc_pfc_ignore pfc_ignore; 2724 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2725 struct ice_aqc_set_dcb_params set_dcb_params; 2726 struct ice_aqc_lldp_get_mib lldp_get_mib; 2727 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2728 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv; 2729 struct ice_aqc_lldp_update_tlv lldp_update_tlv; 2730 struct ice_aqc_lldp_stop lldp_stop; 2731 struct ice_aqc_lldp_start lldp_start; 2732 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2733 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2734 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2735 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2736 struct ice_aqc_get_set_rss_key get_set_rss_key; 2737 struct ice_aqc_clear_fd_table clear_fd_table; 2738 struct ice_aqc_acl_alloc_table alloc_table; 2739 struct ice_aqc_acl_tbl_actpair tbl_actpair; 2740 struct ice_aqc_acl_alloc_scen alloc_scen; 2741 struct ice_aqc_acl_dealloc_scen dealloc_scen; 2742 struct ice_aqc_acl_update_query_scen update_query_scen; 2743 struct ice_aqc_acl_alloc_counters alloc_counters; 2744 struct ice_aqc_acl_dealloc_counters dealloc_counters; 2745 struct ice_aqc_acl_dealloc_res dealloc_res; 2746 struct ice_aqc_acl_entry program_query_entry; 2747 struct ice_aqc_acl_actpair program_query_actpair; 2748 struct ice_aqc_acl_profile profile; 2749 struct ice_aqc_acl_query_counter query_counter; 2750 struct ice_aqc_add_txqs add_txqs; 2751 struct ice_aqc_dis_txqs dis_txqs; 2752 struct ice_aqc_move_txqs move_txqs; 2753 struct ice_aqc_txqs_cleanup txqs_cleanup; 2754 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2755 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2756 struct ice_aqc_get_vsi_resp get_vsi_resp; 2757 struct ice_aqc_download_pkg download_pkg; 2758 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 2759 struct ice_aqc_driver_shared_params drv_shared_params; 2760 struct ice_aqc_set_mac_lb set_mac_lb; 2761 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2762 struct ice_aqc_get_res_alloc get_res; 2763 struct ice_aqc_get_allocd_res_desc get_res_desc; 2764 struct ice_aqc_set_mac_cfg set_mac_cfg; 2765 struct ice_aqc_set_event_mask set_event_mask; 2766 struct ice_aqc_get_link_status get_link_status; 2767 struct ice_aqc_event_lan_overflow lan_overflow; 2768 struct ice_aqc_get_link_topo get_link_topo; 2769 struct ice_aqc_set_health_status_config 2770 set_health_status_config; 2771 struct ice_aqc_get_supported_health_status_codes 2772 get_supported_health_status_codes; 2773 struct ice_aqc_get_health_status get_health_status; 2774 struct ice_aqc_clear_health_status clear_health_status; 2775 } params; 2776 }; 2777 2778 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2779 #define ICE_AQ_LG_BUF 512 2780 2781 /* Flags sub-structure 2782 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 2783 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 2784 */ 2785 2786 /* command flags and offsets */ 2787 #define ICE_AQ_FLAG_DD_S 0 2788 #define ICE_AQ_FLAG_CMP_S 1 2789 #define ICE_AQ_FLAG_ERR_S 2 2790 #define ICE_AQ_FLAG_VFE_S 3 2791 #define ICE_AQ_FLAG_LB_S 9 2792 #define ICE_AQ_FLAG_RD_S 10 2793 #define ICE_AQ_FLAG_VFC_S 11 2794 #define ICE_AQ_FLAG_BUF_S 12 2795 #define ICE_AQ_FLAG_SI_S 13 2796 #define ICE_AQ_FLAG_EI_S 14 2797 #define ICE_AQ_FLAG_FE_S 15 2798 2799 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 2800 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 2801 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2802 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 2803 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2804 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2805 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 2806 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2807 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2808 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 2809 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 2810 2811 /* error codes */ 2812 enum ice_aq_err { 2813 ICE_AQ_RC_OK = 0, /* Success */ 2814 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2815 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2816 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 2817 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 2818 ICE_AQ_RC_EIO = 5, /* I/O error */ 2819 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 2820 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 2821 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 2822 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2823 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 2824 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 2825 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2826 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2827 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2828 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 2829 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2830 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2831 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 2832 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 2833 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 2834 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2835 ICE_AQ_RC_EFBIG = 22, /* File too big */ 2836 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 2837 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2838 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2839 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2840 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2841 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2842 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 2843 }; 2844 2845 /* Admin Queue command opcodes */ 2846 enum ice_adminq_opc { 2847 /* AQ commands */ 2848 ice_aqc_opc_get_ver = 0x0001, 2849 ice_aqc_opc_driver_ver = 0x0002, 2850 ice_aqc_opc_q_shutdown = 0x0003, 2851 ice_aqc_opc_get_exp_err = 0x0005, 2852 2853 /* resource ownership */ 2854 ice_aqc_opc_req_res = 0x0008, 2855 ice_aqc_opc_release_res = 0x0009, 2856 2857 /* device/function capabilities */ 2858 ice_aqc_opc_list_func_caps = 0x000A, 2859 ice_aqc_opc_list_dev_caps = 0x000B, 2860 2861 /* manage MAC address */ 2862 ice_aqc_opc_manage_mac_read = 0x0107, 2863 ice_aqc_opc_manage_mac_write = 0x0108, 2864 2865 /* PXE */ 2866 ice_aqc_opc_clear_pxe_mode = 0x0110, 2867 2868 ice_aqc_opc_config_no_drop_policy = 0x0112, 2869 2870 /* internal switch commands */ 2871 ice_aqc_opc_get_sw_cfg = 0x0200, 2872 2873 /* Alloc/Free/Get Resources */ 2874 ice_aqc_opc_get_res_alloc = 0x0204, 2875 ice_aqc_opc_alloc_res = 0x0208, 2876 ice_aqc_opc_free_res = 0x0209, 2877 ice_aqc_opc_get_allocd_res_desc = 0x020A, 2878 2879 /* VSI commands */ 2880 ice_aqc_opc_add_vsi = 0x0210, 2881 ice_aqc_opc_update_vsi = 0x0211, 2882 ice_aqc_opc_get_vsi_params = 0x0212, 2883 ice_aqc_opc_free_vsi = 0x0213, 2884 2885 /* Mirroring rules - add/update, delete */ 2886 ice_aqc_opc_add_update_mir_rule = 0x0260, 2887 ice_aqc_opc_del_mir_rule = 0x0261, 2888 2889 /* storm configuration */ 2890 ice_aqc_opc_set_storm_cfg = 0x0280, 2891 ice_aqc_opc_get_storm_cfg = 0x0281, 2892 2893 /* recipe commands */ 2894 ice_aqc_opc_add_recipe = 0x0290, 2895 ice_aqc_opc_recipe_to_profile = 0x0291, 2896 ice_aqc_opc_get_recipe = 0x0292, 2897 ice_aqc_opc_get_recipe_to_profile = 0x0293, 2898 2899 /* switch rules population commands */ 2900 ice_aqc_opc_add_sw_rules = 0x02A0, 2901 ice_aqc_opc_update_sw_rules = 0x02A1, 2902 ice_aqc_opc_remove_sw_rules = 0x02A2, 2903 ice_aqc_opc_get_sw_rules = 0x02A3, 2904 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2905 2906 /* DCB commands */ 2907 ice_aqc_opc_pfc_ignore = 0x0301, 2908 ice_aqc_opc_query_pfc_mode = 0x0302, 2909 ice_aqc_opc_set_pfc_mode = 0x0303, 2910 ice_aqc_opc_set_dcb_params = 0x0306, 2911 2912 /* transmit scheduler commands */ 2913 ice_aqc_opc_get_dflt_topo = 0x0400, 2914 ice_aqc_opc_add_sched_elems = 0x0401, 2915 ice_aqc_opc_cfg_sched_elems = 0x0403, 2916 ice_aqc_opc_get_sched_elems = 0x0404, 2917 ice_aqc_opc_move_sched_elems = 0x0408, 2918 ice_aqc_opc_suspend_sched_elems = 0x0409, 2919 ice_aqc_opc_resume_sched_elems = 0x040A, 2920 ice_aqc_opc_query_port_ets = 0x040E, 2921 ice_aqc_opc_delete_sched_elems = 0x040F, 2922 ice_aqc_opc_add_rl_profiles = 0x0410, 2923 ice_aqc_opc_query_rl_profiles = 0x0411, 2924 ice_aqc_opc_query_sched_res = 0x0412, 2925 ice_aqc_opc_query_node_to_root = 0x0413, 2926 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 2927 ice_aqc_opc_remove_rl_profiles = 0x0415, 2928 2929 /* PHY commands */ 2930 ice_aqc_opc_get_phy_caps = 0x0600, 2931 ice_aqc_opc_set_phy_cfg = 0x0601, 2932 ice_aqc_opc_set_mac_cfg = 0x0603, 2933 ice_aqc_opc_restart_an = 0x0605, 2934 ice_aqc_opc_get_link_status = 0x0607, 2935 ice_aqc_opc_set_event_mask = 0x0613, 2936 ice_aqc_opc_set_mac_lb = 0x0620, 2937 ice_aqc_opc_get_link_topo = 0x06E0, 2938 ice_aqc_opc_set_port_id_led = 0x06E9, 2939 ice_aqc_opc_get_port_options = 0x06EA, 2940 ice_aqc_opc_set_port_option = 0x06EB, 2941 ice_aqc_opc_set_gpio = 0x06EC, 2942 ice_aqc_opc_get_gpio = 0x06ED, 2943 ice_aqc_opc_sff_eeprom = 0x06EE, 2944 ice_aqc_opc_sw_set_gpio = 0x06EF, 2945 ice_aqc_opc_sw_get_gpio = 0x06F0, 2946 2947 /* NVM commands */ 2948 ice_aqc_opc_nvm_read = 0x0701, 2949 ice_aqc_opc_nvm_erase = 0x0702, 2950 ice_aqc_opc_nvm_write = 0x0703, 2951 ice_aqc_opc_nvm_cfg_read = 0x0704, 2952 ice_aqc_opc_nvm_cfg_write = 0x0705, 2953 ice_aqc_opc_nvm_checksum = 0x0706, 2954 ice_aqc_opc_nvm_write_activate = 0x0707, 2955 ice_aqc_opc_nvm_sr_dump = 0x0707, 2956 ice_aqc_opc_nvm_save_factory_settings = 0x0708, 2957 ice_aqc_opc_nvm_update_empr = 0x0709, 2958 2959 /* LLDP commands */ 2960 ice_aqc_opc_lldp_get_mib = 0x0A00, 2961 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2962 ice_aqc_opc_lldp_add_tlv = 0x0A02, 2963 ice_aqc_opc_lldp_update_tlv = 0x0A03, 2964 ice_aqc_opc_lldp_delete_tlv = 0x0A04, 2965 ice_aqc_opc_lldp_stop = 0x0A05, 2966 ice_aqc_opc_lldp_start = 0x0A06, 2967 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2968 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 2969 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 2970 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 2971 2972 /* RSS commands */ 2973 ice_aqc_opc_set_rss_key = 0x0B02, 2974 ice_aqc_opc_set_rss_lut = 0x0B03, 2975 ice_aqc_opc_get_rss_key = 0x0B04, 2976 ice_aqc_opc_get_rss_lut = 0x0B05, 2977 ice_aqc_opc_clear_fd_table = 0x0B06, 2978 /* ACL commands */ 2979 ice_aqc_opc_alloc_acl_tbl = 0x0C10, 2980 ice_aqc_opc_dealloc_acl_tbl = 0x0C11, 2981 ice_aqc_opc_alloc_acl_actpair = 0x0C12, 2982 ice_aqc_opc_dealloc_acl_actpair = 0x0C13, 2983 ice_aqc_opc_alloc_acl_scen = 0x0C14, 2984 ice_aqc_opc_dealloc_acl_scen = 0x0C15, 2985 ice_aqc_opc_alloc_acl_counters = 0x0C16, 2986 ice_aqc_opc_dealloc_acl_counters = 0x0C17, 2987 ice_aqc_opc_dealloc_acl_res = 0x0C1A, 2988 ice_aqc_opc_update_acl_scen = 0x0C1B, 2989 ice_aqc_opc_program_acl_actpair = 0x0C1C, 2990 ice_aqc_opc_program_acl_prof_extraction = 0x0C1D, 2991 ice_aqc_opc_program_acl_prof_ranges = 0x0C1E, 2992 ice_aqc_opc_program_acl_entry = 0x0C20, 2993 ice_aqc_opc_query_acl_prof = 0x0C21, 2994 ice_aqc_opc_query_acl_prof_ranges = 0x0C22, 2995 ice_aqc_opc_query_acl_scen = 0x0C23, 2996 ice_aqc_opc_query_acl_entry = 0x0C24, 2997 ice_aqc_opc_query_acl_actpair = 0x0C25, 2998 ice_aqc_opc_query_acl_counter = 0x0C27, 2999 3000 /* Tx queue handling commands/events */ 3001 ice_aqc_opc_add_txqs = 0x0C30, 3002 ice_aqc_opc_dis_txqs = 0x0C31, 3003 ice_aqc_opc_txqs_cleanup = 0x0C31, 3004 ice_aqc_opc_move_recfg_txqs = 0x0C32, 3005 3006 /* package commands */ 3007 ice_aqc_opc_download_pkg = 0x0C40, 3008 ice_aqc_opc_upload_section = 0x0C41, 3009 ice_aqc_opc_update_pkg = 0x0C42, 3010 ice_aqc_opc_get_pkg_info_list = 0x0C43, 3011 3012 ice_aqc_opc_driver_shared_params = 0x0C90, 3013 3014 /* Standalone Commands/Events */ 3015 ice_aqc_opc_event_lan_overflow = 0x1001, 3016 3017 /* SystemDiagnostic commands */ 3018 ice_aqc_opc_set_health_status_config = 0xFF20, 3019 ice_aqc_opc_get_supported_health_status_codes = 0xFF21, 3020 ice_aqc_opc_get_health_status = 0xFF22, 3021 ice_aqc_opc_clear_health_status = 0xFF23 3022 }; 3023 3024 #endif /* _ICE_ADMINQ_CMD_H_ */ 3025