Searched refs:dcache_line_size (Results 1 – 9 of 9) sorted by relevance
466 for ( ; va < eva; va += cpuinfo.dcache_line_size) { in icache_sync()516 for ( ; va < eva; va += cpuinfo.dcache_line_size) { in dcache_wb_pou()545 for ( ; va < eva; va += cpuinfo.dcache_line_size) { in dcache_inv_poc()569 for ( ; va < eva; va += cpuinfo.dcache_line_size) { in dcache_inv_poc_dma()592 for ( ; va < eva; va += cpuinfo.dcache_line_size) { in dcache_wb_poc()610 for ( ; va < eva; va += cpuinfo.dcache_line_size) { in dcache_wbinv_poc()620 for ( ; va < eva; va += cpuinfo.dcache_line_size) { in dcache_wbinv_poc()
115 int dcache_line_size; member
51 .dcache_line_size = 32,183 cpuinfo.dcache_line_size = in cpuinfo_init()188 cpuinfo.dcache_line_size = in cpuinfo_init()193 cpuinfo.dcache_line_mask = cpuinfo.dcache_line_size - 1; in cpuinfo_init()
132 ASSYM(DCACHE_LINE_SIZE, offsetof(struct cpuinfo, dcache_line_size));
67 #define BUSDMA_DCACHE_ALIGN cpuinfo.dcache_line_size
58 ldr x3, =dcache_line_size /* Load the D cache line size */
190 return (((paddr | size) & (dcache_line_size - 1)) != 0); in cacheline_bounce()280 dcache_line_size); in bounce_bus_dma_tag_create()282 dcache_line_size); in bounce_bus_dma_tag_create()1049 if (va & (dcache_line_size - 1)) in dma_preread_safe()1051 if ((va + size) & (dcache_line_size - 1)) in dma_preread_safe()
1188 int64_t dcache_line_size; /* The minimum D cache line size */ variable1661 if (dcache_line_size == 0) { in identify_cache()1666 dcache_line_size = CTR_DLINE_SIZE(ctr); in identify_cache()1670 idcache_line_size = MIN(dcache_line_size, icache_line_size); in identify_cache()1673 if (dcache_line_size != CTR_DLINE_SIZE(ctr)) { in identify_cache()1675 dcache_line_size, CTR_DLINE_SIZE(ctr)); in identify_cache()
215 extern int64_t dcache_line_size;