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Searched refs:cycles (Results 1 – 25 of 141) sorted by relevance

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/f-stack/freebsd/mips/ingenic/
H A Djz4780_nemc.c114 uint32_t smcr, cycles; in jz4780_nemc_configure_bank() local
129 cycles = JZ4780_NEMC_NS_TO_TICKS(sc, val); in jz4780_nemc_configure_bank()
130 if (cycles > 15) { in jz4780_nemc_configure_bank()
133 "ingenic,nemc-tAS", val, cycles, 15); in jz4780_nemc_configure_bank()
137 smcr |= cycles << JZ_NEMC_SMCR_TAS_SHIFT; in jz4780_nemc_configure_bank()
141 cycles = JZ4780_NEMC_NS_TO_TICKS(sc, val); in jz4780_nemc_configure_bank()
142 if (cycles > 15) { in jz4780_nemc_configure_bank()
149 smcr |= cycles << JZ_NEMC_SMCR_TAH_SHIFT; in jz4780_nemc_configure_bank()
154 if (cycles > 31) { in jz4780_nemc_configure_bank()
166 if (cycles > 31) { in jz4780_nemc_configure_bank()
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/f-stack/dpdk/app/test/
H A Dtest_cycles.c29 uint64_t cycles, prev_cycles; in check_wait_one_second() local
36 cycles = rte_get_timer_cycles(); in check_wait_one_second()
38 if ((uint64_t)(cycles - prev_cycles) > (hz + max_inc)) { in check_wait_one_second()
42 if ((uint64_t)(cycles - prev_cycles) < (hz - max_inc)) { in check_wait_one_second()
54 uint64_t start_cycles, cycles, prev_cycles; in test_cycles() local
62 cycles = rte_get_timer_cycles(); in test_cycles()
63 if ((uint64_t)(cycles - prev_cycles) > max_inc) { in test_cycles()
67 prev_cycles = cycles; in test_cycles()
H A Dtest_rcu_qsbr_perf.c60 uint64_t begin, cycles; in test_rcu_qsbr_reader_perf() local
83 cycles = rte_rdtsc_precise() - begin; in test_rcu_qsbr_reader_perf()
101 uint64_t begin, cycles; in test_rcu_qsbr_writer_perf() local
115 cycles = rte_rdtsc_precise() - begin; in test_rcu_qsbr_writer_perf()
116 rte_atomic64_add(&check_cycles, cycles); in test_rcu_qsbr_writer_perf()
289 uint64_t begin, cycles; in test_rcu_qsbr_hash_reader() local
319 cycles = rte_rdtsc_precise() - begin; in test_rcu_qsbr_hash_reader()
385 uint64_t token, begin, cycles; in test_rcu_qsbr_sw_sv_1qs() local
455 cycles = rte_rdtsc_precise() - begin; in test_rcu_qsbr_sw_sv_1qs()
504 uint64_t token, begin, cycles; in test_rcu_qsbr_sw_sv_1qs_non_blocking() local
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H A Dtest_trace_perf.c49 double cycles, ns; in measure_perf() local
57 cycles = total_calls ? (double)total_cycles / (double)total_calls : 0; in measure_perf()
58 cycles /= STEP; in measure_perf()
59 cycles /= 100; /* CENT_OPS */ in measure_perf()
61 ns = (cycles / (double)hz) * 1E9; in measure_perf()
62 printf("%16s: cycles=%f ns=%f\n", str, cycles, ns); in measure_perf()
H A Dtest_efd_perf.c74 static uint64_t cycles[NUM_KEYSIZES][NUM_OPERATIONS]; variable
191 cycles[params->cycle][ADD] = time_taken / KEYS_TO_ADD; in timed_adds()
224 cycles[params->cycle][LOOKUP] = time_taken / NUM_LOOKUPS; in timed_lookups()
268 cycles[params->cycle][LOOKUP_MULTI] = time_taken / NUM_LOOKUPS; in timed_lookups_multi()
297 cycles[params->cycle][DELETE] = time_taken / KEYS_TO_ADD; in timed_deletes()
369 printf("%-18"PRIu64, cycles[i][j]); in run_all_tbl_perf_tests()
H A Dtest_hash_readwrite.c62 uint64_t begin, cycles; in test_hash_readwrite_worker() local
112 cycles = rte_rdtsc_precise() - begin; in test_hash_readwrite_worker()
113 rte_atomic64_add(&gcycles, cycles); in test_hash_readwrite_worker()
298 uint64_t begin, cycles; in test_rw_reader() local
315 cycles = rte_rdtsc_precise() - begin; in test_rw_reader()
316 rte_atomic64_add(&gread_cycles, cycles); in test_rw_reader()
326 uint64_t begin, cycles; in test_rw_writer() local
349 cycles = rte_rdtsc_precise() - begin; in test_rw_writer()
350 rte_atomic64_add(&gwrite_cycles, cycles); in test_rw_writer()
H A Dtest_member_perf.c68 static uint64_t cycles[NUM_TYPE][NUM_KEYSIZES][NUM_OPERATIONS]; variable
231 cycles[type][params->cycle][ADD] = time_taken / KEYS_TO_ADD; in timed_adds()
266 cycles[type][params->cycle][LOOKUP] = time_taken / NUM_LOOKUPS; in timed_lookups()
313 cycles[type][params->cycle][LOOKUP_BULK] = time_taken / NUM_LOOKUPS; in timed_lookups_bulk()
353 cycles[type][params->cycle][LOOKUP_MULTI] = time_taken / NUM_LOOKUPS; in timed_lookups_multimatch()
407 cycles[type][params->cycle][LOOKUP_MULTI_BULK] = time_taken / in timed_lookups_multimatch_bulk()
434 cycles[type][params->cycle][DELETE] = time_taken / KEYS_TO_ADD; in timed_deletes()
480 cycles[type][params->cycle][LOOKUP_MISS] = time_taken / NUM_LOOKUPS; in timed_miss_lookup()
585 printf("%-18"PRIu64, cycles[j][i][k]); in run_all_tbl_perf_tests()
H A Dtest_hash_multiwriter.c57 uint64_t begin, cycles; in test_hash_multiwriter_worker() local
86 cycles = rte_rdtsc_precise() - begin; in test_hash_multiwriter_worker()
87 rte_atomic64_add(&gcycles, cycles); in test_hash_multiwriter_worker()
/f-stack/freebsd/contrib/device-tree/Bindings/bus/
H A Dqcom,ebi2.txt34 FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
77 - qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to
82 - qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles
86 - qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for
88 - qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the
90 - qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1
92 - qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1
99 - qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE
102 - qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
131 qcom,xmem-recovery-cycles = <0>;
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H A Dnvidia,tegra20-gmi.txt56 - nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the
58 - nvidia,snor-hold-width: Number of cycles CE stays asserted after the
61 - nvidia,snor-adv-width: Number of cycles during which ADV stays asserted.
63 - nvidia,snor-ce-width: Number of cycles before CE is asserted.
65 - nvidia,snor-we-width: Number of cycles during which WE stays asserted.
67 - nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
69 - nvidia,snor-wait-width: Number of cycles before READY is asserted.
/f-stack/freebsd/contrib/device-tree/Bindings/mtd/
H A Dfsmc-nand.txt15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
17 cycles.
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
21 Only valid for write transactions. Zero means zero cycles,
22 255 means 255 cycles.
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
25 one cycle, 255 means 256 cycles.
26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
28 255 means 256 cycles.
29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
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/f-stack/freebsd/crypto/openssl/arm/
H A Dsha256-armv4.S23 @ lute" terms is ~2250 cycles per 64-byte block or ~35 cycles per
29 @ Cortex A8 core and ~20 cycles per processed byte.
34 @ improvement on Cortex A8 core and ~15.4 cycles per processed byte.
39 @ byte in 12.5 cycles or 23% faster than integer-only code. Snapdragon
40 @ S4 does it in 12.5 cycles too, but it's 50% faster than integer-only
H A Dsha512-armv4.S23 @ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
29 @ Cortex A8 core and ~40 cycles per processed byte.
34 @ improvement on Coxtex A8 core and ~38 cycles per byte.
39 @ one byte in 23.3 cycles or ~60% faster than integer-only code.
/f-stack/freebsd/contrib/octeon-sdk/
H A Dcvmx-tim.h212 …const uint64_t cycles = cvmx_clock_get_count(CVMX_CLOCK_TIM); /* Get our reference time early fo… in cvmx_tim_add_entry() local
232 work_bucket = (((ticks_from_now * cvmx_tim.tick_cycles) + cycles - cvmx_tim.start_time) in cvmx_tim_add_entry()
289 delete_info->commit_cycles = cycles + (ticks_from_now - 2) * cvmx_tim.tick_cycles; in cvmx_tim_add_entry()
314 const uint64_t cycles = cvmx_clock_get_count(CVMX_CLOCK_TIM); in cvmx_tim_delete_entry() local
316 if ((int64_t)(cycles - delete_info->commit_cycles) < 0) in cvmx_tim_delete_entry()
/f-stack/app/redis-5.0.5/utils/
H A Dcorrupt_rdb.c16 int fd, cycles; in main() local
25 cycles = atoi(argv[2]); in main()
33 while(cycles--) { in main()
/f-stack/freebsd/contrib/ncsw/inc/
H A Dncsw_ext.h154 #define CYCLES_TO_USEC(cycles,clk) ((cycles) / (clk)) argument
158 #define CYCLES_TO_NSEC(cycles,clk) (((cycles) * 1000) / (clk)) argument
162 #define CYCLES_TO_PSEC(cycles,clk) (((cycles) * 1000000) / (clk)) argument
/f-stack/freebsd/contrib/device-tree/Bindings/mmc/
H A Dsdhci-pxa.yaml65 mrvl,clk-delay-cycles:
66 description: Specify a number of cycles to delay for tuning.
87 mrvl,clk-delay-cycles = <31>;
99 mrvl,clk-delay-cycles = <0x1F>;
/f-stack/dpdk/lib/librte_graph/
H A Dgraph_stats.c63 const uint64_t cycles = stat->cycles; in print_node() local
72 call_delta ? (double)((cycles - stat->prev_cycles) / call_delta) in print_node()
331 uint64_t calls = 0, cycles = 0, objs = 0, realloc_count = 0; in cluster_node_arregate_stats() local
341 cycles += node->total_cycles; in cluster_node_arregate_stats()
347 stat->cycles = cycles; in cluster_node_arregate_stats()
360 stat->prev_cycles = stat->cycles; in cluster_node_store_prev_stats()
398 node->cycles = 0; in rte_graph_cluster_stats_reset()
/f-stack/freebsd/contrib/device-tree/Bindings/c6x/
H A Dclocks.txt24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
/f-stack/dpdk/doc/guides/sample_app_ug/
H A Drxtx_callbacks.rst14 prior to transmission to calculate the elapsed time, in CPU cycles.
161 each packet (see the *cycles* section of the *DPDK API Documentation* for
177 uint64_t cycles = 0;
182 cycles += now - *tsc_field(pkts[i]);
184 latency_numbers.total_cycles += cycles;
188 printf("Latency = %"PRIu64" cycles\n",
198 the total number of cycles used. Once more than 100 million packets have been
/f-stack/freebsd/contrib/device-tree/Bindings/misc/
H A Difm-csi.txt14 - ifm,csi-wait-cycles: sensor bus wait cycles
34 ifm,csi-wait-cycles = <0>;
/f-stack/dpdk/examples/rxtx_callbacks/
H A Dmain.c77 uint64_t cycles = 0; in calc_latency() local
87 cycles += now - *tsc_field(pkts[i]); in calc_latency()
92 latency_numbers.total_cycles += cycles; in calc_latency()
197 uint64_t cycles = rte_rdtsc(); in port_init() local
200 uint64_t c_freq = cycles - cycles_base; in port_init()
/f-stack/dpdk/lib/librte_eal/include/
H A Drte_time.h36 rte_cyclecounter_cycles_to_ns(struct rte_timecounter *tc, uint64_t cycles) in rte_cyclecounter_cycles_to_ns() argument
41 ns = cycles + tc->nsec_frac; in rte_cyclecounter_cycles_to_ns()
/f-stack/freebsd/contrib/device-tree/Bindings/regulator/
H A Dti-abb-regulator.txt22 - ti,clock-cycles: SoC specific data about count of system ti,clock-cycles used for
24 cycles for SR2_WTCNT_VALUE).
79 ti,clock-cycles = <8>;
99 ti,clock-cycles = <16>;
126 ti,clock-cycles = <16>;
/f-stack/freebsd/contrib/device-tree/Bindings/media/i2c/
H A Dtda1997x.txt11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
19 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
161 * 2 pixclk cycles.

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