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Searched refs:cvmx_write_csr (Results 1 – 25 of 71) sorted by relevance

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/f-stack/freebsd/contrib/octeon-sdk/
H A Dcvmx-helper-rgmii.c161 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); in cvmx_helper_rgmii_internal_loopback()
162 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); in cvmx_helper_rgmii_internal_loopback()
203 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64); in __cvmx_helper_rgmii_enable()
207 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64); in __cvmx_helper_rgmii_enable()
352 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), in __cvmx_helper_rgmii_link_set()
360 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); in __cvmx_helper_rgmii_link_set()
422 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 5); in __cvmx_helper_rgmii_link_set()
428 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); in __cvmx_helper_rgmii_link_set()
466 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), in __cvmx_helper_rgmii_link_set()
473 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); in __cvmx_helper_rgmii_link_set()
[all …]
H A Dcvmx-helper-xaui.c123 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64); in __cvmx_helper_xaui_probe()
142 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64); in __cvmx_helper_xaui_probe()
163 cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); in __cvmx_helper_xaui_probe()
214 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0,interface), 0x0); in __cvmx_helper_xaui_link_init()
215 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); in __cvmx_helper_xaui_link_init()
216 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); in __cvmx_helper_xaui_link_init()
263 cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1); in __cvmx_helper_xaui_link_init()
264 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512); in __cvmx_helper_xaui_link_init()
265 cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192); in __cvmx_helper_xaui_link_init()
282 cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface), ~0x0ull); in __cvmx_helper_xaui_link_init()
[all …]
H A Dcvmx-spi.c235 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0); in cvmx_spi_reset_cb()
237 cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0); in cvmx_spi_reset_cb()
240 cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0); in cvmx_spi_reset_cb()
241 cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0); in cvmx_spi_reset_cb()
244 cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); in cvmx_spi_reset_cb()
271 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64); in cvmx_spi_reset_cb()
273 cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64); in cvmx_spi_reset_cb()
286 cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); in cvmx_spi_reset_cb()
291 cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); in cvmx_spi_reset_cb()
458 cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); in cvmx_spi_clock_detect_cb()
[all …]
H A Dcvmx-dma-engine.c182 cvmx_write_csr(CVMX_DPI_ENGX_BUF(0), dpi_engx_buf.u64); in cvmx_dma_engine_initialize()
183 cvmx_write_csr(CVMX_DPI_ENGX_BUF(1), dpi_engx_buf.u64); in cvmx_dma_engine_initialize()
184 cvmx_write_csr(CVMX_DPI_ENGX_BUF(2), dpi_engx_buf.u64); in cvmx_dma_engine_initialize()
185 cvmx_write_csr(CVMX_DPI_ENGX_BUF(3), dpi_engx_buf.u64); in cvmx_dma_engine_initialize()
198 cvmx_write_csr(CVMX_DPI_DMA_CONTROL, dma_control.u64); in cvmx_dma_engine_initialize()
206 cvmx_write_csr(CVMX_DPI_CTL, dpi_ctl.u64); in cvmx_dma_engine_initialize()
219 cvmx_write_csr(CVMX_NPI_DMA_CONTROL, dma_control.u64); in cvmx_dma_engine_initialize()
266 cvmx_write_csr(CVMX_DPI_DMA_CONTROL, dma_control.u64); in cvmx_dma_engine_shutdown()
276 cvmx_write_csr(CVMX_NPI_DMA_CONTROL, dma_control.u64); in cvmx_dma_engine_shutdown()
291 cvmx_write_csr(CVMX_NPI_HIGHP_IBUFF_SADDR, 0); in cvmx_dma_engine_shutdown()
[all …]
H A Dcvmx-zip.c82 cvmx_write_csr(CVMX_ZIP_CMD_BUF, zip_cmd_buf.u64); in cvmx_zip_initialize()
83 cvmx_write_csr(CVMX_ZIP_ERROR, 1); in cvmx_zip_initialize()
123 cvmx_write_csr(CVMX_ZIP_QUEX_BUF(queue), zip_que_buf.u64); in cvmx_zip_queue_initialize()
128 cvmx_write_csr(CVMX_ZIP_QUEX_MAP(queue), que_map.u64); in cvmx_zip_queue_initialize()
133 cvmx_write_csr(CVMX_ZIP_QUE_ENA, que_ena.u64); in cvmx_zip_queue_initialize()
136 cvmx_write_csr(CVMX_ZIP_QUE_PRI, 0x3); in cvmx_zip_queue_initialize()
144 cvmx_write_csr(CVMX_ZIP_INT_REG, int_reg.u64); in cvmx_zip_queue_initialize()
168 cvmx_write_csr(CVMX_ZIP_CMD_CTL, zip_cmd_ctl.u64); in cvmx_zip_shutdown()
195 cvmx_write_csr(CVMX_ZIP_CMD_CTL, zip_cmd_ctl.u64); in cvmx_zip_queue_shutdown()
213 cvmx_write_csr(CVMX_ADDR_DID(CVMX_FULL_DID(7, 0)), 8); in cvmx_zip_submit()
[all …]
H A Dcvmx-mgmt-port.c225 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); in cvmx_mgmt_port_initialize()
295 cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64); in cvmx_mgmt_port_initialize()
328 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); in cvmx_mgmt_port_initialize()
569 cvmx_write_csr(CVMX_MIXX_ORING2(port), 1); in cvmx_mgmt_port_send()
624 cvmx_write_csr(CVMX_MIXX_ORING2(port), 1); in cvmx_mgmt_port_sendm()
701 cvmx_write_csr(CVMX_MIXX_IRING2(port), 1); in cvmx_mgmt_port_receive()
742 cvmx_write_csr(CVMX_MIXX_IRING2(port), 1); in cvmx_mgmt_port_receive()
744 cvmx_write_csr(CVMX_MIXX_IRCNT(port), 1); in cvmx_mgmt_port_receive()
788 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), 1); in cvmx_mgmt_port_set_mac()
850 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), 0); in cvmx_mgmt_port_set_multicast_list()
[all …]
H A Dcvmx-helper-sgmii.c112 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); in __cvmx_helper_sgmii_hardware_init_one_time()
320 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); in __cvmx_helper_sgmii_hardware_init_link_speed()
321 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); in __cvmx_helper_sgmii_hardware_init_link_speed()
328 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); in __cvmx_helper_sgmii_hardware_init_link_speed()
329 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); in __cvmx_helper_sgmii_hardware_init_link_speed()
336 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 512); in __cvmx_helper_sgmii_hardware_init_link_speed()
387 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64); in __cvmx_helper_sgmii_hardware_init()
406 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64); in __cvmx_helper_sgmii_hardware_init()
467 cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); in __cvmx_helper_sgmii_probe()
511 cvmx_write_csr(CVMX_GMXX_BPID_MSK(interface), bpid_msk.u64); in __cvmx_helper_sgmii_enable()
[all …]
H A Dcvmx-interrupt.c149 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r'); in cvmx_safe_printf()
150 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++); in cvmx_safe_printf()
520 cvmx_write_csr(mask_reg, 1ull << (sum_bit - 60)); in __cvmx_interrupt_ciu2()
545 cvmx_write_csr(mask_reg, 1ull << src_bit); in __cvmx_interrupt_ciu2()
741 cvmx_write_csr(reg, 1ull << bit); in __cvmx_interrupt_ciu2_mask_unmask_irq()
962 cvmx_write_csr(CVMX_CIU2_EN_PPX_IP2_RML(cvmx_get_core_num()), 0); in cvmx_interrupt_ciu2_initialize()
963 cvmx_write_csr(CVMX_CIU2_EN_PPX_IP3_RML(cvmx_get_core_num()), 0); in cvmx_interrupt_ciu2_initialize()
968 cvmx_write_csr(CVMX_CIU2_EN_PPX_IP2_IO(cvmx_get_core_num()), 0); in cvmx_interrupt_ciu2_initialize()
969 cvmx_write_csr(CVMX_CIU2_EN_PPX_IP3_IO(cvmx_get_core_num()), 0); in cvmx_interrupt_ciu2_initialize()
970 cvmx_write_csr(CVMX_CIU2_EN_PPX_IP4_IO(cvmx_get_core_num()), 0); in cvmx_interrupt_ciu2_initialize()
[all …]
H A Dcvmx-pcie.c550 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); in __cvmx_pcie_rc_initialize_gen1()
553 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); in __cvmx_pcie_rc_initialize_gen1()
581 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); in __cvmx_pcie_rc_initialize_gen1()
583 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); in __cvmx_pcie_rc_initialize_gen1()
692 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0); in __cvmx_pcie_rc_initialize_gen1()
1001 cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64); in __cvmx_pcie_rc_initialize_gen2()
1010 cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64); in __cvmx_pcie_rc_initialize_gen2()
1133 cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0); in __cvmx_pcie_rc_initialize_gen2()
1138 cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0); in __cvmx_pcie_rc_initialize_gen2()
1504 cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64); in cvmx_pcie_ep_initialize()
[all …]
H A Dcvmx-ipd.h124 cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64); in cvmx_ipd_config()
128 cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64); in cvmx_ipd_config()
132 cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64); in cvmx_ipd_config()
136 cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64); in cvmx_ipd_config()
140 cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK,second_back_struct.u64); in cvmx_ipd_config()
144 cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64); in cvmx_ipd_config()
149 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64); in cvmx_ipd_config()
182 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); in cvmx_ipd_enable()
194 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); in cvmx_ipd_disable()
H A Dcvmx-ilk.c201 cvmx_write_csr (CVMX_ILK_SER_CFG, ilk_ser_cfg.u64); in cvmx_ilk_start_interface()
207 cvmx_write_csr (CVMX_ILK_TXX_CFG0(interface), ilk_txx_cfg0.u64); in cvmx_ilk_start_interface()
208 cvmx_write_csr (CVMX_ILK_RXX_CFG0(interface), ilk_rxx_cfg0.u64); in cvmx_ilk_start_interface()
339 cvmx_write_csr (CVMX_ILK_RXF_MEM_PMAP, chpknd->pknd); in cvmx_ilk_rx_set_pknd()
719 cvmx_write_csr (CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64); in cvmx_ilk_bp_conf()
867 cvmx_write_csr (CVMX_ILK_RXF_IDX_PMAP, ilk_rxf_idx_pmap.u64); in cvmx_ilk_reg_dump_rx()
996 cvmx_write_csr (CVMX_ILK_GBL_INT, ilk_gbl_int.u64); in cvmx_ilk_runtime_status()
1239 cvmx_write_csr (CVMX_ILK_RXX_IDX_STAT0(interface), in cvmx_ilk_show_stats()
1248 cvmx_write_csr (CVMX_ILK_RXX_IDX_STAT1(interface), in cvmx_ilk_show_stats()
1261 cvmx_write_csr (CVMX_ILK_TXX_IDX_STAT0(interface), in cvmx_ilk_show_stats()
[all …]
H A Dcvmx-helper.c825 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64); in __cvmx_helper_global_setup_pko()
904 cvmx_write_csr(CVMX_IPD_INT_ENB, 0); in __cvmx_helper_backpressure_is_misaligned()
993 cvmx_write_csr(CVMX_IPD_INT_SUM, 0x1f); in __cvmx_helper_backpressure_is_misaligned()
994 cvmx_write_csr(CVMX_IPD_INT_ENB, ipd_int_enb); in __cvmx_helper_backpressure_is_misaligned()
1130 cvmx_write_csr(CVMX_SSO_CFG, sso_cfg.u64); in cvmx_helper_initialize_sso()
1164 cvmx_write_csr(CVMX_SSO_CFG, sso_cfg.u64); in cvmx_helper_initialize_sso()
1185 cvmx_write_csr(CVMX_SSO_CFG, sso_cfg.u64); in cvmx_helper_uninitialize_sso()
1212 cvmx_write_csr(CVMX_SSO_CFG, sso_cfg.u64); in cvmx_helper_uninitialize_sso()
1241 cvmx_write_csr(CVMX_SSO_CFG, sso_cfg.u64); in cvmx_helper_uninitialize_sso()
1276 cvmx_write_csr(CVMX_L2C_CTL, l2c_ctl.u64); in cvmx_helper_initialize_packet_io_global()
[all …]
H A Dcvmx-helper-errata.c123 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0); in __cvmx_helper_errata_fix_ipd_ptr_alignment()
144 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT)); in __cvmx_helper_errata_fix_ipd_ptr_alignment()
193 …cvmx_write_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), gmx_cfg.u64… in __cvmx_helper_errata_fix_ipd_ptr_alignment()
194 … cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT)); in __cvmx_helper_errata_fix_ipd_ptr_alignment()
195 … cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT)); in __cvmx_helper_errata_fix_ipd_ptr_alignment()
222 … cvmx_write_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), prtx_cfg); in __cvmx_helper_errata_fix_ipd_ptr_alignment()
223 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), tx_ptr_en); in __cvmx_helper_errata_fix_ipd_ptr_alignment()
224 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), rx_ptr_en); in __cvmx_helper_errata_fix_ipd_ptr_alignment()
225 …cvmx_write_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), rxx_jabbe… in __cvmx_helper_errata_fix_ipd_ptr_alignment()
226 …cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), frame_ma… in __cvmx_helper_errata_fix_ipd_ptr_alignment()
[all …]
H A Dcvmx-ipd.c124 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64); in __cvmx_ipd_free_ptr_v1()
132 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64); in __cvmx_ipd_free_ptr_v1()
151 cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, ipd_prc_port_ptr_fifo_ctl.u64); in __cvmx_ipd_free_ptr_v1()
169 cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, ipd_prc_hold_ptr_fifo_ctl.u64); in __cvmx_ipd_free_ptr_v1()
186 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64); in __cvmx_ipd_free_ptr_v1()
191 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64); in __cvmx_ipd_free_ptr_v1()
240 cvmx_write_csr(CVMX_IPD_FREE_PTR_FIFO_CTL, ipd_free_ptr_fifo_ctl.u64); in __cvmx_ipd_free_ptr_v2()
256 cvmx_write_csr(CVMX_IPD_PORT_PTR_FIFO_CTL, ipd_port_ptr_fifo_ctl.u64); in __cvmx_ipd_free_ptr_v2()
261 cvmx_write_csr(CVMX_IPD_PORT_PTR_FIFO_CTL, ipd_port_ptr_fifo_ctl.u64); in __cvmx_ipd_free_ptr_v2()
277 cvmx_write_csr(CVMX_IPD_HOLD_PTR_FIFO_CTL, ipd_hold_ptr_fifo_ctl.u64); in __cvmx_ipd_free_ptr_v2()
[all …]
H A Dcvmx-llm.c714 cvmx_write_csr (CVMX_DFA_DDR2_CFG, dfaCfg.u64); in cn31xx_dfa_memory_init()
721 cvmx_write_csr (CVMX_DFA_DDR2_PLL, dfaPll.u64); in cn31xx_dfa_memory_init()
724 cvmx_write_csr (CVMX_DFA_DDR2_PLL, dfaPll.u64); in cn31xx_dfa_memory_init()
728 cvmx_write_csr (CVMX_DFA_DDR2_PLL, dfaPll.u64); in cn31xx_dfa_memory_init()
743 cvmx_write_csr (CVMX_DFA_DDR2_CFG, dfaCfg.u64); in cn31xx_dfa_memory_init()
772 cvmx_write_csr (CVMX_DFA_DDR2_TMG, dfaTmg.u64); in cn31xx_dfa_memory_init()
776 cvmx_write_csr (CVMX_DFA_DDR2_CFG, dfaCfg.u64); in cn31xx_dfa_memory_init()
811 cvmx_write_csr(CVMX_DFA_MEMCFG0, memcfg0.u64); in write_rld_cfg()
913 cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0); in write_rld_cfg()
922 cvmx_write_csr (CVMX_DFA_MEMCFG2, memcfg2.u64); in write_rld_cfg()
[all …]
H A Dcvmx-uart.c62 cvmx_write_csr(CVMX_MIO_UARTX_IER(uart), ier.u64); in cvmx_uart_enable_intr()
110 cvmx_write_csr(CVMX_MIO_UARTX_FCR(uart_index), fcrval.u64); in cvmx_uart_setup2()
128 cvmx_write_csr(CVMX_MIO_UARTX_LCR(uart_index), lcrval.u64); in cvmx_uart_setup2()
130 cvmx_write_csr(CVMX_MIO_UARTX_DLL(uart_index), divisor & 0xff); in cvmx_uart_setup2()
131 cvmx_write_csr(CVMX_MIO_UARTX_DLH(uart_index), (divisor>>8) & 0xff); in cvmx_uart_setup2()
134 cvmx_write_csr(CVMX_MIO_UARTX_LCR(uart_index), lcrval.u64); in cvmx_uart_setup2()
155 cvmx_write_csr(CVMX_MIO_UARTX_MCR(uart_index), mcrval.u64); in cvmx_uart_setup2()
H A Dcvmx-gpio.h89 cvmx_write_csr(CVMX_CIU_INTX_SUM0(core * 2), ciu_sum0.u64); in cvmx_gpio_interrupt_clear()
92 cvmx_write_csr(CVMX_GPIO_INT_CLR, (clear_mask & ~0xf0)); in cvmx_gpio_interrupt_clear()
100 cvmx_write_csr(CVMX_GPIO_INT_CLR, gpio_int_clr.u64); in cvmx_gpio_interrupt_clear()
123 cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(bit), gpio_xbit.u64); in cvmx_gpio_cfg()
136 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), gpio_bit.u64); in cvmx_gpio_cfg()
163 cvmx_write_csr(CVMX_GPIO_TX_CLR, gpio_tx_clr.u64); in cvmx_gpio_clear()
177 cvmx_write_csr(CVMX_GPIO_TX_SET, gpio_tx_set.u64); in cvmx_gpio_set()
H A Dcvmx-pko.c582 cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64); in cvmx_pko_initialize_global()
613 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); in cvmx_pko_initialize_global()
615 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); in cvmx_pko_initialize_global()
617 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 0); in cvmx_pko_initialize_global()
622 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 3); in cvmx_pko_initialize_global()
624 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); in cvmx_pko_initialize_global()
626 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); in cvmx_pko_initialize_global()
628 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 0); in cvmx_pko_initialize_global()
697 cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64); in cvmx_pko_enable()
708 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); in cvmx_pko_disable()
[all …]
H A Dcvmx-higig.h343 cvmx_write_csr(CVMX_PIP_PRT_CFGX(pknd), pip_prt_cfg.u64); in cvmx_higig_initialize()
355 cvmx_write_csr(CVMX_PIP_HG_PRI_QOS, pip_hg_pri_qos.u64); in cvmx_higig_initialize()
363 cvmx_write_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface), gmx_rx_udd_skp.u64); in cvmx_higig_initialize()
368 cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface), gmx_rx_frm_ctl.u64); in cvmx_higig_initialize()
373 cvmx_write_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface), gmx_tx_min_pkt.u64); in cvmx_higig_initialize()
378 cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmx_tx_append.u64); in cvmx_higig_initialize()
384 cvmx_write_csr(CVMX_GMXX_TX_IFG(interface), gmx_tx_ifg.u64); in cvmx_higig_initialize()
391 cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64); in cvmx_higig_initialize()
403 cvmx_write_csr(CVMX_GMXX_HG2_CONTROL(interface), gmx_hg2_control.u64); in cvmx_higig_initialize()
409 cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmx_tx_xaui_ctl.u64); in cvmx_higig_initialize()
H A Dcvmx-tra.c376 cvmx_write_csr(CVMX_TRAX_CTL(tad), control.u64); in cvmx_tra_setup()
377 cvmx_write_csr(CVMX_TRAX_FILT_CMD(tad), filt_cmd.u64); in cvmx_tra_setup()
378 cvmx_write_csr(CVMX_TRAX_FILT_SID(tad), filt_sid.u64); in cvmx_tra_setup()
379 cvmx_write_csr(CVMX_TRAX_FILT_DID(tad), filt_did.u64); in cvmx_tra_setup()
380 cvmx_write_csr(CVMX_TRAX_FILT_ADR_ADR(tad), address); in cvmx_tra_setup()
435 cvmx_write_csr(CVMX_TRAX_CTL(tra), control.u64); in cvmx_tra_setup_v2()
436 cvmx_write_csr(CVMX_TRAX_FILT_CMD(tra), filt_cmd.u64); in cvmx_tra_setup_v2()
437 cvmx_write_csr(CVMX_TRAX_FILT_SID(tra), filt_sid.u64); in cvmx_tra_setup_v2()
438 cvmx_write_csr(CVMX_TRAX_FILT_DID(tra), filt_did.u64); in cvmx_tra_setup_v2()
439 cvmx_write_csr(CVMX_TRAX_FILT_ADR_ADR(tra), address); in cvmx_tra_setup_v2()
[all …]
H A Dcvmx-raid.c81 cvmx_write_csr(CVMX_RAD_REG_POLYNOMIAL, polynomial.u64); in cvmx_raid_initialize()
94 cvmx_write_csr(CVMX_RAD_REG_CMD_BUF, rad_reg_cmd_buf.u64); in cvmx_raid_initialize()
119 cvmx_write_csr(CVMX_RAD_REG_CTL, rad_reg_ctl.u64); in cvmx_raid_shutdown()
123 cvmx_write_csr(CVMX_RAD_REG_CMD_BUF, 0); in cvmx_raid_shutdown()
142 cvmx_write_csr(CVMX_ADDR_DID(CVMX_FULL_DID(14, 0)), num_words); in cvmx_raid_submit()
H A Dcvmx-helper-jtag.c100 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); in cvmx_helper_qlm_jtag_init()
129 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); in cvmx_helper_qlm_jtag_shift()
138 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); in cvmx_helper_qlm_jtag_shift()
187 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); in cvmx_helper_qlm_jtag_update()
195 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); in cvmx_helper_qlm_jtag_update()
218 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); in cvmx_helper_qlm_jtag_capture()
225 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); in cvmx_helper_qlm_jtag_capture()
/f-stack/freebsd/mips/cavium/octe/
H A Dethernet-common.c85 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN(index, interface), 0); in cvm_oct_common_set_multicast_list()
87 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN(index, interface), 1); in cvm_oct_common_set_multicast_list()
89 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); in cvm_oct_common_set_multicast_list()
154 cvmx_write_csr(CVMX_GMXX_SMACX(index, interface), mac); in cvm_oct_common_set_mac_address()
155 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM0(index, interface), ptr[0]); in cvm_oct_common_set_mac_address()
156 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM1(index, interface), ptr[1]); in cvm_oct_common_set_mac_address()
157 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM2(index, interface), ptr[2]); in cvm_oct_common_set_mac_address()
158 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM3(index, interface), ptr[3]); in cvm_oct_common_set_mac_address()
159 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM4(index, interface), ptr[4]); in cvm_oct_common_set_mac_address()
160 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM5(index, interface), ptr[5]); in cvm_oct_common_set_mac_address()
[all …]
H A Dethernet-spi.c68 cvmx_write_csr(CVMX_SPXX_INT_REG(1), spx_int_reg.u64); in cvm_oct_spi_rml_interrupt()
96 cvmx_write_csr(CVMX_STXX_INT_REG(1), stx_int_reg.u64); in cvm_oct_spi_rml_interrupt()
119 cvmx_write_csr(CVMX_SPXX_INT_MSK(1), 0); in cvm_oct_spi_rml_interrupt()
120 cvmx_write_csr(CVMX_STXX_INT_MSK(1), 0); in cvm_oct_spi_rml_interrupt()
130 cvmx_write_csr(CVMX_SPXX_INT_REG(0), spx_int_reg.u64); in cvm_oct_spi_rml_interrupt()
158 cvmx_write_csr(CVMX_STXX_INT_REG(0), stx_int_reg.u64); in cvm_oct_spi_rml_interrupt()
181 cvmx_write_csr(CVMX_SPXX_INT_MSK(0), 0); in cvm_oct_spi_rml_interrupt()
182 cvmx_write_csr(CVMX_STXX_INT_MSK(0), 0); in cvm_oct_spi_rml_interrupt()
206 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64); in cvm_oct_spi_enable_error_reporting()
300 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0); in cvm_oct_spi_uninit()
[all …]
H A Dethernet-rgmii.c94 cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface), gmxx_rxx_frm_ctl.u64); in cvm_oct_rgmii_poll()
99 cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); in cvm_oct_rgmii_poll()
102 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), gmxx_rxx_int_reg.u64); in cvm_oct_rgmii_poll()
124 cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface), gmxx_rxx_frm_ctl.u64); in cvm_oct_rgmii_poll()
128 cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); in cvm_oct_rgmii_poll()
131 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), gmxx_rxx_int_reg.u64); in cvm_oct_rgmii_poll()
168 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), gmx_rx_int_reg.u64); in cvm_oct_rgmii_rml_interrupt()
192 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), gmx_rx_int_reg.u64); in cvm_oct_rgmii_rml_interrupt()
257 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, interface), gmx_rx_int_en.u64); in cvm_oct_rgmii_init()
284 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, interface), gmx_rx_int_en.u64); in cvm_oct_rgmii_uninit()

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