1 /***********************license start***************
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38 ***********************license end**************************************/
39
40
41 /**
42 * cvmx-spx0-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon spx0.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52 #ifndef __CVMX_SPX0_DEFS_H__
53 #define __CVMX_SPX0_DEFS_H__
54
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_SPX0_PLL_BW_CTL CVMX_SPX0_PLL_BW_CTL_FUNC()
CVMX_SPX0_PLL_BW_CTL_FUNC(void)57 static inline uint64_t CVMX_SPX0_PLL_BW_CTL_FUNC(void)
58 {
59 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
60 cvmx_warn("CVMX_SPX0_PLL_BW_CTL not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001180090000388ull);
62 }
63 #else
64 #define CVMX_SPX0_PLL_BW_CTL (CVMX_ADD_IO_SEG(0x0001180090000388ull))
65 #endif
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 #define CVMX_SPX0_PLL_SETTING CVMX_SPX0_PLL_SETTING_FUNC()
CVMX_SPX0_PLL_SETTING_FUNC(void)68 static inline uint64_t CVMX_SPX0_PLL_SETTING_FUNC(void)
69 {
70 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
71 cvmx_warn("CVMX_SPX0_PLL_SETTING not supported on this chip\n");
72 return CVMX_ADD_IO_SEG(0x0001180090000380ull);
73 }
74 #else
75 #define CVMX_SPX0_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180090000380ull))
76 #endif
77
78 /**
79 * cvmx_spx0_pll_bw_ctl
80 */
81 union cvmx_spx0_pll_bw_ctl {
82 uint64_t u64;
83 struct cvmx_spx0_pll_bw_ctl_s {
84 #ifdef __BIG_ENDIAN_BITFIELD
85 uint64_t reserved_5_63 : 59;
86 uint64_t bw_ctl : 5; /**< Core PLL bandwidth control */
87 #else
88 uint64_t bw_ctl : 5;
89 uint64_t reserved_5_63 : 59;
90 #endif
91 } s;
92 struct cvmx_spx0_pll_bw_ctl_s cn38xx;
93 struct cvmx_spx0_pll_bw_ctl_s cn38xxp2;
94 };
95 typedef union cvmx_spx0_pll_bw_ctl cvmx_spx0_pll_bw_ctl_t;
96
97 /**
98 * cvmx_spx0_pll_setting
99 */
100 union cvmx_spx0_pll_setting {
101 uint64_t u64;
102 struct cvmx_spx0_pll_setting_s {
103 #ifdef __BIG_ENDIAN_BITFIELD
104 uint64_t reserved_17_63 : 47;
105 uint64_t setting : 17; /**< Core PLL setting */
106 #else
107 uint64_t setting : 17;
108 uint64_t reserved_17_63 : 47;
109 #endif
110 } s;
111 struct cvmx_spx0_pll_setting_s cn38xx;
112 struct cvmx_spx0_pll_setting_s cn38xxp2;
113 };
114 typedef union cvmx_spx0_pll_setting cvmx_spx0_pll_setting_t;
115
116 #endif
117