1 /***********************license start***************
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38 ***********************license end**************************************/
39
40
41 /**
42 * cvmx-led-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon led.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52 #ifndef __CVMX_LED_DEFS_H__
53 #define __CVMX_LED_DEFS_H__
54
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_LED_BLINK CVMX_LED_BLINK_FUNC()
CVMX_LED_BLINK_FUNC(void)57 static inline uint64_t CVMX_LED_BLINK_FUNC(void)
58 {
59 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
60 cvmx_warn("CVMX_LED_BLINK not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001180000001A48ull);
62 }
63 #else
64 #define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
65 #endif
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 #define CVMX_LED_CLK_PHASE CVMX_LED_CLK_PHASE_FUNC()
CVMX_LED_CLK_PHASE_FUNC(void)68 static inline uint64_t CVMX_LED_CLK_PHASE_FUNC(void)
69 {
70 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
71 cvmx_warn("CVMX_LED_CLK_PHASE not supported on this chip\n");
72 return CVMX_ADD_IO_SEG(0x0001180000001A08ull);
73 }
74 #else
75 #define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
76 #endif
77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
78 #define CVMX_LED_CYLON CVMX_LED_CYLON_FUNC()
CVMX_LED_CYLON_FUNC(void)79 static inline uint64_t CVMX_LED_CYLON_FUNC(void)
80 {
81 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
82 cvmx_warn("CVMX_LED_CYLON not supported on this chip\n");
83 return CVMX_ADD_IO_SEG(0x0001180000001AF8ull);
84 }
85 #else
86 #define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
87 #endif
88 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
89 #define CVMX_LED_DBG CVMX_LED_DBG_FUNC()
CVMX_LED_DBG_FUNC(void)90 static inline uint64_t CVMX_LED_DBG_FUNC(void)
91 {
92 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
93 cvmx_warn("CVMX_LED_DBG not supported on this chip\n");
94 return CVMX_ADD_IO_SEG(0x0001180000001A18ull);
95 }
96 #else
97 #define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
98 #endif
99 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
100 #define CVMX_LED_EN CVMX_LED_EN_FUNC()
CVMX_LED_EN_FUNC(void)101 static inline uint64_t CVMX_LED_EN_FUNC(void)
102 {
103 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
104 cvmx_warn("CVMX_LED_EN not supported on this chip\n");
105 return CVMX_ADD_IO_SEG(0x0001180000001A00ull);
106 }
107 #else
108 #define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull))
109 #endif
110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
111 #define CVMX_LED_POLARITY CVMX_LED_POLARITY_FUNC()
CVMX_LED_POLARITY_FUNC(void)112 static inline uint64_t CVMX_LED_POLARITY_FUNC(void)
113 {
114 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
115 cvmx_warn("CVMX_LED_POLARITY not supported on this chip\n");
116 return CVMX_ADD_IO_SEG(0x0001180000001A50ull);
117 }
118 #else
119 #define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull))
120 #endif
121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
122 #define CVMX_LED_PRT CVMX_LED_PRT_FUNC()
CVMX_LED_PRT_FUNC(void)123 static inline uint64_t CVMX_LED_PRT_FUNC(void)
124 {
125 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
126 cvmx_warn("CVMX_LED_PRT not supported on this chip\n");
127 return CVMX_ADD_IO_SEG(0x0001180000001A10ull);
128 }
129 #else
130 #define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull))
131 #endif
132 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
133 #define CVMX_LED_PRT_FMT CVMX_LED_PRT_FMT_FUNC()
CVMX_LED_PRT_FMT_FUNC(void)134 static inline uint64_t CVMX_LED_PRT_FMT_FUNC(void)
135 {
136 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
137 cvmx_warn("CVMX_LED_PRT_FMT not supported on this chip\n");
138 return CVMX_ADD_IO_SEG(0x0001180000001A30ull);
139 }
140 #else
141 #define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull))
142 #endif
143 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_LED_PRT_STATUSX(unsigned long offset)144 static inline uint64_t CVMX_LED_PRT_STATUSX(unsigned long offset)
145 {
146 if (!(
147 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
148 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
149 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7)))))
150 cvmx_warn("CVMX_LED_PRT_STATUSX(%lu) is invalid on this chip\n", offset);
151 return CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8;
152 }
153 #else
154 #define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8)
155 #endif
156 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_LED_UDD_CNTX(unsigned long offset)157 static inline uint64_t CVMX_LED_UDD_CNTX(unsigned long offset)
158 {
159 if (!(
160 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
161 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
162 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
163 cvmx_warn("CVMX_LED_UDD_CNTX(%lu) is invalid on this chip\n", offset);
164 return CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8;
165 }
166 #else
167 #define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8)
168 #endif
169 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_LED_UDD_DATX(unsigned long offset)170 static inline uint64_t CVMX_LED_UDD_DATX(unsigned long offset)
171 {
172 if (!(
173 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
174 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
175 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
176 cvmx_warn("CVMX_LED_UDD_DATX(%lu) is invalid on this chip\n", offset);
177 return CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8;
178 }
179 #else
180 #define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8)
181 #endif
182 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_LED_UDD_DAT_CLRX(unsigned long offset)183 static inline uint64_t CVMX_LED_UDD_DAT_CLRX(unsigned long offset)
184 {
185 if (!(
186 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
187 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
188 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
189 cvmx_warn("CVMX_LED_UDD_DAT_CLRX(%lu) is invalid on this chip\n", offset);
190 return CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16;
191 }
192 #else
193 #define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16)
194 #endif
195 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_LED_UDD_DAT_SETX(unsigned long offset)196 static inline uint64_t CVMX_LED_UDD_DAT_SETX(unsigned long offset)
197 {
198 if (!(
199 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
200 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
201 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
202 cvmx_warn("CVMX_LED_UDD_DAT_SETX(%lu) is invalid on this chip\n", offset);
203 return CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16;
204 }
205 #else
206 #define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16)
207 #endif
208
209 /**
210 * cvmx_led_blink
211 *
212 * LED_BLINK = LED Blink Rate (in led_clks)
213 *
214 */
215 union cvmx_led_blink {
216 uint64_t u64;
217 struct cvmx_led_blink_s {
218 #ifdef __BIG_ENDIAN_BITFIELD
219 uint64_t reserved_8_63 : 56;
220 uint64_t rate : 8; /**< LED Blink rate in led_latch clks
221 RATE must be > 0 */
222 #else
223 uint64_t rate : 8;
224 uint64_t reserved_8_63 : 56;
225 #endif
226 } s;
227 struct cvmx_led_blink_s cn38xx;
228 struct cvmx_led_blink_s cn38xxp2;
229 struct cvmx_led_blink_s cn56xx;
230 struct cvmx_led_blink_s cn56xxp1;
231 struct cvmx_led_blink_s cn58xx;
232 struct cvmx_led_blink_s cn58xxp1;
233 };
234 typedef union cvmx_led_blink cvmx_led_blink_t;
235
236 /**
237 * cvmx_led_clk_phase
238 *
239 * LED_CLK_PHASE = LED Clock Phase (in 64 eclks)
240 *
241 *
242 * Notes:
243 * Example:
244 * Given a 2ns eclk, an LED_CLK_PHASE[PHASE] = 1, indicates that each
245 * led_clk phase is 64 eclks, or 128ns. The led_clk period is 2*phase,
246 * or 256ns which is 3.9MHz. The default value of 4, yields an led_clk
247 * period of 64*4*2ns*2 = 1024ns or ~1MHz (977KHz).
248 */
249 union cvmx_led_clk_phase {
250 uint64_t u64;
251 struct cvmx_led_clk_phase_s {
252 #ifdef __BIG_ENDIAN_BITFIELD
253 uint64_t reserved_7_63 : 57;
254 uint64_t phase : 7; /**< Number of 64 eclks in order to create the led_clk */
255 #else
256 uint64_t phase : 7;
257 uint64_t reserved_7_63 : 57;
258 #endif
259 } s;
260 struct cvmx_led_clk_phase_s cn38xx;
261 struct cvmx_led_clk_phase_s cn38xxp2;
262 struct cvmx_led_clk_phase_s cn56xx;
263 struct cvmx_led_clk_phase_s cn56xxp1;
264 struct cvmx_led_clk_phase_s cn58xx;
265 struct cvmx_led_clk_phase_s cn58xxp1;
266 };
267 typedef union cvmx_led_clk_phase cvmx_led_clk_phase_t;
268
269 /**
270 * cvmx_led_cylon
271 *
272 * LED_CYLON = LED CYLON Effect (should remain undocumented)
273 *
274 */
275 union cvmx_led_cylon {
276 uint64_t u64;
277 struct cvmx_led_cylon_s {
278 #ifdef __BIG_ENDIAN_BITFIELD
279 uint64_t reserved_16_63 : 48;
280 uint64_t rate : 16; /**< LED Cylon Effect when RATE!=0
281 Changes at RATE*LATCH period */
282 #else
283 uint64_t rate : 16;
284 uint64_t reserved_16_63 : 48;
285 #endif
286 } s;
287 struct cvmx_led_cylon_s cn38xx;
288 struct cvmx_led_cylon_s cn38xxp2;
289 struct cvmx_led_cylon_s cn56xx;
290 struct cvmx_led_cylon_s cn56xxp1;
291 struct cvmx_led_cylon_s cn58xx;
292 struct cvmx_led_cylon_s cn58xxp1;
293 };
294 typedef union cvmx_led_cylon cvmx_led_cylon_t;
295
296 /**
297 * cvmx_led_dbg
298 *
299 * LED_DBG = LED Debug Port information
300 *
301 */
302 union cvmx_led_dbg {
303 uint64_t u64;
304 struct cvmx_led_dbg_s {
305 #ifdef __BIG_ENDIAN_BITFIELD
306 uint64_t reserved_1_63 : 63;
307 uint64_t dbg_en : 1; /**< Add Debug Port Data to the LED shift chain
308 Debug Data is shifted out LSB to MSB */
309 #else
310 uint64_t dbg_en : 1;
311 uint64_t reserved_1_63 : 63;
312 #endif
313 } s;
314 struct cvmx_led_dbg_s cn38xx;
315 struct cvmx_led_dbg_s cn38xxp2;
316 struct cvmx_led_dbg_s cn56xx;
317 struct cvmx_led_dbg_s cn56xxp1;
318 struct cvmx_led_dbg_s cn58xx;
319 struct cvmx_led_dbg_s cn58xxp1;
320 };
321 typedef union cvmx_led_dbg cvmx_led_dbg_t;
322
323 /**
324 * cvmx_led_en
325 *
326 * LED_EN = LED Interface Enable
327 *
328 *
329 * Notes:
330 * The LED interface is comprised of a shift chain with a parallel latch. LED
331 * data is shifted out on each fallingg edge of led_clk and then captured by
332 * led_lat.
333 *
334 * The LED shift chain is comprised of the following...
335 *
336 * 32 - UDD header
337 * 6x8 - per port status
338 * 17 - debug port
339 * 32 - UDD trailer
340 *
341 * for a total of 129 bits.
342 *
343 * UDD header is programmable from 0-32 bits (LED_UDD_CNT0) and will shift out
344 * LSB to MSB (LED_UDD_DAT0[0], LED_UDD_DAT0[1],
345 * ... LED_UDD_DAT0[LED_UDD_CNT0].
346 *
347 * The per port status is also variable. Systems can control which ports send
348 * data (LED_PRT) as well as the status content (LED_PRT_FMT and
349 * LED_PRT_STATUS*). When multiple ports are enabled, they come out in lowest
350 * port to highest port (prt0, prt1, ...).
351 *
352 * The debug port data can also be added to the LED chain (LED_DBG). When
353 * enabled, the debug data shifts out LSB to MSB.
354 *
355 * The UDD trailer data is identical to the header data, but uses LED_UDD_CNT1
356 * and LED_UDD_DAT1.
357 */
358 union cvmx_led_en {
359 uint64_t u64;
360 struct cvmx_led_en_s {
361 #ifdef __BIG_ENDIAN_BITFIELD
362 uint64_t reserved_1_63 : 63;
363 uint64_t en : 1; /**< Enable the LED interface shift-chain */
364 #else
365 uint64_t en : 1;
366 uint64_t reserved_1_63 : 63;
367 #endif
368 } s;
369 struct cvmx_led_en_s cn38xx;
370 struct cvmx_led_en_s cn38xxp2;
371 struct cvmx_led_en_s cn56xx;
372 struct cvmx_led_en_s cn56xxp1;
373 struct cvmx_led_en_s cn58xx;
374 struct cvmx_led_en_s cn58xxp1;
375 };
376 typedef union cvmx_led_en cvmx_led_en_t;
377
378 /**
379 * cvmx_led_polarity
380 *
381 * LED_POLARITY = LED Polarity
382 *
383 */
384 union cvmx_led_polarity {
385 uint64_t u64;
386 struct cvmx_led_polarity_s {
387 #ifdef __BIG_ENDIAN_BITFIELD
388 uint64_t reserved_1_63 : 63;
389 uint64_t polarity : 1; /**< LED active polarity
390 0 = active HIGH LED
391 1 = active LOW LED (invert led_dat) */
392 #else
393 uint64_t polarity : 1;
394 uint64_t reserved_1_63 : 63;
395 #endif
396 } s;
397 struct cvmx_led_polarity_s cn38xx;
398 struct cvmx_led_polarity_s cn38xxp2;
399 struct cvmx_led_polarity_s cn56xx;
400 struct cvmx_led_polarity_s cn56xxp1;
401 struct cvmx_led_polarity_s cn58xx;
402 struct cvmx_led_polarity_s cn58xxp1;
403 };
404 typedef union cvmx_led_polarity cvmx_led_polarity_t;
405
406 /**
407 * cvmx_led_prt
408 *
409 * LED_PRT = LED Port status information
410 *
411 *
412 * Notes:
413 * Note:
414 * the PRT vector enables information of the 8 RGMII ports connected to
415 * Octane. It does not reflect the actual programmed PHY addresses.
416 */
417 union cvmx_led_prt {
418 uint64_t u64;
419 struct cvmx_led_prt_s {
420 #ifdef __BIG_ENDIAN_BITFIELD
421 uint64_t reserved_8_63 : 56;
422 uint64_t prt_en : 8; /**< Which ports are enabled to display status
423 PRT_EN<3:0> coresponds to RGMII ports 3-0 on int0
424 PRT_EN<7:4> coresponds to RGMII ports 7-4 on int1
425 Only applies when interface is in RGMII mode
426 The status format is defined by LED_PRT_FMT */
427 #else
428 uint64_t prt_en : 8;
429 uint64_t reserved_8_63 : 56;
430 #endif
431 } s;
432 struct cvmx_led_prt_s cn38xx;
433 struct cvmx_led_prt_s cn38xxp2;
434 struct cvmx_led_prt_s cn56xx;
435 struct cvmx_led_prt_s cn56xxp1;
436 struct cvmx_led_prt_s cn58xx;
437 struct cvmx_led_prt_s cn58xxp1;
438 };
439 typedef union cvmx_led_prt cvmx_led_prt_t;
440
441 /**
442 * cvmx_led_prt_fmt
443 *
444 * LED_PRT_FMT = LED Port Status Infomation Format
445 *
446 *
447 * Notes:
448 * TX: RGMII TX block is sending packet data or extends on the port
449 * RX: RGMII RX block has received non-idle cycle
450 *
451 * For short transfers, LEDs will remain on for at least one blink cycle
452 */
453 union cvmx_led_prt_fmt {
454 uint64_t u64;
455 struct cvmx_led_prt_fmt_s {
456 #ifdef __BIG_ENDIAN_BITFIELD
457 uint64_t reserved_4_63 : 60;
458 uint64_t format : 4; /**< Port Status Information for each enabled port in
459 LED_PRT. The formats are below
460 0x0: [ LED_PRT_STATUS[0] ]
461 0x1: [ LED_PRT_STATUS[1:0] ]
462 0x2: [ LED_PRT_STATUS[3:0] ]
463 0x3: [ LED_PRT_STATUS[5:0] ]
464 0x4: [ (RX|TX), LED_PRT_STATUS[0] ]
465 0x5: [ (RX|TX), LED_PRT_STATUS[1:0] ]
466 0x6: [ (RX|TX), LED_PRT_STATUS[3:0] ]
467 0x8: [ Tx, Rx, LED_PRT_STATUS[0] ]
468 0x9: [ Tx, Rx, LED_PRT_STATUS[1:0] ]
469 0xa: [ Tx, Rx, LED_PRT_STATUS[3:0] ] */
470 #else
471 uint64_t format : 4;
472 uint64_t reserved_4_63 : 60;
473 #endif
474 } s;
475 struct cvmx_led_prt_fmt_s cn38xx;
476 struct cvmx_led_prt_fmt_s cn38xxp2;
477 struct cvmx_led_prt_fmt_s cn56xx;
478 struct cvmx_led_prt_fmt_s cn56xxp1;
479 struct cvmx_led_prt_fmt_s cn58xx;
480 struct cvmx_led_prt_fmt_s cn58xxp1;
481 };
482 typedef union cvmx_led_prt_fmt cvmx_led_prt_fmt_t;
483
484 /**
485 * cvmx_led_prt_status#
486 *
487 * LED_PRT_STATUS = LED Port Status information
488 *
489 */
490 union cvmx_led_prt_statusx {
491 uint64_t u64;
492 struct cvmx_led_prt_statusx_s {
493 #ifdef __BIG_ENDIAN_BITFIELD
494 uint64_t reserved_6_63 : 58;
495 uint64_t status : 6; /**< Bits that software can set to be added to the
496 LED shift chain - depending on LED_PRT_FMT
497 LED_PRT_STATUS(3..0) corespond to RGMII ports 3-0
498 on interface0
499 LED_PRT_STATUS(7..4) corespond to RGMII ports 7-4
500 on interface1
501 Only applies when interface is in RGMII mode */
502 #else
503 uint64_t status : 6;
504 uint64_t reserved_6_63 : 58;
505 #endif
506 } s;
507 struct cvmx_led_prt_statusx_s cn38xx;
508 struct cvmx_led_prt_statusx_s cn38xxp2;
509 struct cvmx_led_prt_statusx_s cn56xx;
510 struct cvmx_led_prt_statusx_s cn56xxp1;
511 struct cvmx_led_prt_statusx_s cn58xx;
512 struct cvmx_led_prt_statusx_s cn58xxp1;
513 };
514 typedef union cvmx_led_prt_statusx cvmx_led_prt_statusx_t;
515
516 /**
517 * cvmx_led_udd_cnt#
518 *
519 * LED_UDD_CNT = LED UDD Counts
520 *
521 */
522 union cvmx_led_udd_cntx {
523 uint64_t u64;
524 struct cvmx_led_udd_cntx_s {
525 #ifdef __BIG_ENDIAN_BITFIELD
526 uint64_t reserved_6_63 : 58;
527 uint64_t cnt : 6; /**< Number of bits of user-defined data to include in
528 the LED shift chain. Legal values: 0-32. */
529 #else
530 uint64_t cnt : 6;
531 uint64_t reserved_6_63 : 58;
532 #endif
533 } s;
534 struct cvmx_led_udd_cntx_s cn38xx;
535 struct cvmx_led_udd_cntx_s cn38xxp2;
536 struct cvmx_led_udd_cntx_s cn56xx;
537 struct cvmx_led_udd_cntx_s cn56xxp1;
538 struct cvmx_led_udd_cntx_s cn58xx;
539 struct cvmx_led_udd_cntx_s cn58xxp1;
540 };
541 typedef union cvmx_led_udd_cntx cvmx_led_udd_cntx_t;
542
543 /**
544 * cvmx_led_udd_dat#
545 *
546 * LED_UDD_DAT = User defined data (header or trailer)
547 *
548 *
549 * Notes:
550 * Bits come out LSB to MSB on the shift chain. If LED_UDD_CNT is set to 4
551 * then the bits comes out LED_UDD_DAT[0], LED_UDD_DAT[1], LED_UDD_DAT[2],
552 * LED_UDD_DAT[3].
553 */
554 union cvmx_led_udd_datx {
555 uint64_t u64;
556 struct cvmx_led_udd_datx_s {
557 #ifdef __BIG_ENDIAN_BITFIELD
558 uint64_t reserved_32_63 : 32;
559 uint64_t dat : 32; /**< Header or trailer UDD data to be displayed on
560 the LED shift chain. Number of bits to include
561 is controled by LED_UDD_CNT */
562 #else
563 uint64_t dat : 32;
564 uint64_t reserved_32_63 : 32;
565 #endif
566 } s;
567 struct cvmx_led_udd_datx_s cn38xx;
568 struct cvmx_led_udd_datx_s cn38xxp2;
569 struct cvmx_led_udd_datx_s cn56xx;
570 struct cvmx_led_udd_datx_s cn56xxp1;
571 struct cvmx_led_udd_datx_s cn58xx;
572 struct cvmx_led_udd_datx_s cn58xxp1;
573 };
574 typedef union cvmx_led_udd_datx cvmx_led_udd_datx_t;
575
576 /**
577 * cvmx_led_udd_dat_clr#
578 *
579 * LED_UDD_DAT_CLR = User defined data (header or trailer)
580 *
581 */
582 union cvmx_led_udd_dat_clrx {
583 uint64_t u64;
584 struct cvmx_led_udd_dat_clrx_s {
585 #ifdef __BIG_ENDIAN_BITFIELD
586 uint64_t reserved_32_63 : 32;
587 uint64_t clr : 32; /**< Bitwise clear for the Header or trailer UDD data to
588 be displayed on the LED shift chain. */
589 #else
590 uint64_t clr : 32;
591 uint64_t reserved_32_63 : 32;
592 #endif
593 } s;
594 struct cvmx_led_udd_dat_clrx_s cn38xx;
595 struct cvmx_led_udd_dat_clrx_s cn38xxp2;
596 struct cvmx_led_udd_dat_clrx_s cn56xx;
597 struct cvmx_led_udd_dat_clrx_s cn56xxp1;
598 struct cvmx_led_udd_dat_clrx_s cn58xx;
599 struct cvmx_led_udd_dat_clrx_s cn58xxp1;
600 };
601 typedef union cvmx_led_udd_dat_clrx cvmx_led_udd_dat_clrx_t;
602
603 /**
604 * cvmx_led_udd_dat_set#
605 *
606 * LED_UDD_DAT_SET = User defined data (header or trailer)
607 *
608 */
609 union cvmx_led_udd_dat_setx {
610 uint64_t u64;
611 struct cvmx_led_udd_dat_setx_s {
612 #ifdef __BIG_ENDIAN_BITFIELD
613 uint64_t reserved_32_63 : 32;
614 uint64_t set : 32; /**< Bitwise set for the Header or trailer UDD data to
615 be displayed on the LED shift chain. */
616 #else
617 uint64_t set : 32;
618 uint64_t reserved_32_63 : 32;
619 #endif
620 } s;
621 struct cvmx_led_udd_dat_setx_s cn38xx;
622 struct cvmx_led_udd_dat_setx_s cn38xxp2;
623 struct cvmx_led_udd_dat_setx_s cn56xx;
624 struct cvmx_led_udd_dat_setx_s cn56xxp1;
625 struct cvmx_led_udd_dat_setx_s cn58xx;
626 struct cvmx_led_udd_dat_setx_s cn58xxp1;
627 };
628 typedef union cvmx_led_udd_dat_setx cvmx_led_udd_dat_setx_t;
629
630 #endif
631