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39
40
41 /**
42 * cvmx-l2d-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon l2d.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52 #ifndef __CVMX_L2D_DEFS_H__
53 #define __CVMX_L2D_DEFS_H__
54
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_L2D_BST0 CVMX_L2D_BST0_FUNC()
CVMX_L2D_BST0_FUNC(void)57 static inline uint64_t CVMX_L2D_BST0_FUNC(void)
58 {
59 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
60 cvmx_warn("CVMX_L2D_BST0 not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001180080000780ull);
62 }
63 #else
64 #define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull))
65 #endif
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 #define CVMX_L2D_BST1 CVMX_L2D_BST1_FUNC()
CVMX_L2D_BST1_FUNC(void)68 static inline uint64_t CVMX_L2D_BST1_FUNC(void)
69 {
70 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
71 cvmx_warn("CVMX_L2D_BST1 not supported on this chip\n");
72 return CVMX_ADD_IO_SEG(0x0001180080000788ull);
73 }
74 #else
75 #define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull))
76 #endif
77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
78 #define CVMX_L2D_BST2 CVMX_L2D_BST2_FUNC()
CVMX_L2D_BST2_FUNC(void)79 static inline uint64_t CVMX_L2D_BST2_FUNC(void)
80 {
81 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
82 cvmx_warn("CVMX_L2D_BST2 not supported on this chip\n");
83 return CVMX_ADD_IO_SEG(0x0001180080000790ull);
84 }
85 #else
86 #define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull))
87 #endif
88 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
89 #define CVMX_L2D_BST3 CVMX_L2D_BST3_FUNC()
CVMX_L2D_BST3_FUNC(void)90 static inline uint64_t CVMX_L2D_BST3_FUNC(void)
91 {
92 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
93 cvmx_warn("CVMX_L2D_BST3 not supported on this chip\n");
94 return CVMX_ADD_IO_SEG(0x0001180080000798ull);
95 }
96 #else
97 #define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull))
98 #endif
99 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
100 #define CVMX_L2D_ERR CVMX_L2D_ERR_FUNC()
CVMX_L2D_ERR_FUNC(void)101 static inline uint64_t CVMX_L2D_ERR_FUNC(void)
102 {
103 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
104 cvmx_warn("CVMX_L2D_ERR not supported on this chip\n");
105 return CVMX_ADD_IO_SEG(0x0001180080000010ull);
106 }
107 #else
108 #define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull))
109 #endif
110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
111 #define CVMX_L2D_FADR CVMX_L2D_FADR_FUNC()
CVMX_L2D_FADR_FUNC(void)112 static inline uint64_t CVMX_L2D_FADR_FUNC(void)
113 {
114 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
115 cvmx_warn("CVMX_L2D_FADR not supported on this chip\n");
116 return CVMX_ADD_IO_SEG(0x0001180080000018ull);
117 }
118 #else
119 #define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull))
120 #endif
121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
122 #define CVMX_L2D_FSYN0 CVMX_L2D_FSYN0_FUNC()
CVMX_L2D_FSYN0_FUNC(void)123 static inline uint64_t CVMX_L2D_FSYN0_FUNC(void)
124 {
125 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
126 cvmx_warn("CVMX_L2D_FSYN0 not supported on this chip\n");
127 return CVMX_ADD_IO_SEG(0x0001180080000020ull);
128 }
129 #else
130 #define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull))
131 #endif
132 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
133 #define CVMX_L2D_FSYN1 CVMX_L2D_FSYN1_FUNC()
CVMX_L2D_FSYN1_FUNC(void)134 static inline uint64_t CVMX_L2D_FSYN1_FUNC(void)
135 {
136 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
137 cvmx_warn("CVMX_L2D_FSYN1 not supported on this chip\n");
138 return CVMX_ADD_IO_SEG(0x0001180080000028ull);
139 }
140 #else
141 #define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull))
142 #endif
143 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
144 #define CVMX_L2D_FUS0 CVMX_L2D_FUS0_FUNC()
CVMX_L2D_FUS0_FUNC(void)145 static inline uint64_t CVMX_L2D_FUS0_FUNC(void)
146 {
147 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
148 cvmx_warn("CVMX_L2D_FUS0 not supported on this chip\n");
149 return CVMX_ADD_IO_SEG(0x00011800800007A0ull);
150 }
151 #else
152 #define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull))
153 #endif
154 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
155 #define CVMX_L2D_FUS1 CVMX_L2D_FUS1_FUNC()
CVMX_L2D_FUS1_FUNC(void)156 static inline uint64_t CVMX_L2D_FUS1_FUNC(void)
157 {
158 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
159 cvmx_warn("CVMX_L2D_FUS1 not supported on this chip\n");
160 return CVMX_ADD_IO_SEG(0x00011800800007A8ull);
161 }
162 #else
163 #define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull))
164 #endif
165 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
166 #define CVMX_L2D_FUS2 CVMX_L2D_FUS2_FUNC()
CVMX_L2D_FUS2_FUNC(void)167 static inline uint64_t CVMX_L2D_FUS2_FUNC(void)
168 {
169 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
170 cvmx_warn("CVMX_L2D_FUS2 not supported on this chip\n");
171 return CVMX_ADD_IO_SEG(0x00011800800007B0ull);
172 }
173 #else
174 #define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull))
175 #endif
176 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
177 #define CVMX_L2D_FUS3 CVMX_L2D_FUS3_FUNC()
CVMX_L2D_FUS3_FUNC(void)178 static inline uint64_t CVMX_L2D_FUS3_FUNC(void)
179 {
180 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
181 cvmx_warn("CVMX_L2D_FUS3 not supported on this chip\n");
182 return CVMX_ADD_IO_SEG(0x00011800800007B8ull);
183 }
184 #else
185 #define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
186 #endif
187
188 /**
189 * cvmx_l2d_bst0
190 *
191 * L2D_BST0 = L2C Data Store QUAD0 BIST Status Register
192 *
193 */
194 union cvmx_l2d_bst0 {
195 uint64_t u64;
196 struct cvmx_l2d_bst0_s {
197 #ifdef __BIG_ENDIAN_BITFIELD
198 uint64_t reserved_35_63 : 29;
199 uint64_t ftl : 1; /**< L2C Data Store Fatal Defect(across all QUADs)
200 2 or more columns were detected bad across all
201 QUADs[0-3]. Please refer to individual quad failures
202 for bad column = 0x7e to determine which QUAD was in
203 error. */
204 uint64_t q0stat : 34; /**< Bist Results for QUAD0
205 Failure \#1 Status
206 [16:14] bad bank
207 [13:7] bad high column
208 [6:0] bad low column
209 Failure \#2 Status
210 [33:31] bad bank
211 [30:24] bad high column
212 [23:17] bad low column
213 NOTES: For bad high/low column reporting:
214 0x7f: No failure
215 0x7e: Fatal Defect: 2 or more bad columns
216 0-0x45: Bad column
217 NOTE: If there are less than 2 failures then the
218 bad bank will be 0x7. */
219 #else
220 uint64_t q0stat : 34;
221 uint64_t ftl : 1;
222 uint64_t reserved_35_63 : 29;
223 #endif
224 } s;
225 struct cvmx_l2d_bst0_s cn30xx;
226 struct cvmx_l2d_bst0_s cn31xx;
227 struct cvmx_l2d_bst0_s cn38xx;
228 struct cvmx_l2d_bst0_s cn38xxp2;
229 struct cvmx_l2d_bst0_s cn50xx;
230 struct cvmx_l2d_bst0_s cn52xx;
231 struct cvmx_l2d_bst0_s cn52xxp1;
232 struct cvmx_l2d_bst0_s cn56xx;
233 struct cvmx_l2d_bst0_s cn56xxp1;
234 struct cvmx_l2d_bst0_s cn58xx;
235 struct cvmx_l2d_bst0_s cn58xxp1;
236 };
237 typedef union cvmx_l2d_bst0 cvmx_l2d_bst0_t;
238
239 /**
240 * cvmx_l2d_bst1
241 *
242 * L2D_BST1 = L2C Data Store QUAD1 BIST Status Register
243 *
244 */
245 union cvmx_l2d_bst1 {
246 uint64_t u64;
247 struct cvmx_l2d_bst1_s {
248 #ifdef __BIG_ENDIAN_BITFIELD
249 uint64_t reserved_34_63 : 30;
250 uint64_t q1stat : 34; /**< Bist Results for QUAD1
251 Failure \#1 Status
252 [16:14] bad bank
253 [13:7] bad high column
254 [6:0] bad low column
255 Failure \#2 Status
256 [33:31] bad bank
257 [30:24] bad high column
258 [23:17] bad low column
259 NOTES: For bad high/low column reporting:
260 0x7f: No failure
261 0x7e: Fatal Defect: 2 or more bad columns
262 0-0x45: Bad column
263 NOTE: If there are less than 2 failures then the
264 bad bank will be 0x7. */
265 #else
266 uint64_t q1stat : 34;
267 uint64_t reserved_34_63 : 30;
268 #endif
269 } s;
270 struct cvmx_l2d_bst1_s cn30xx;
271 struct cvmx_l2d_bst1_s cn31xx;
272 struct cvmx_l2d_bst1_s cn38xx;
273 struct cvmx_l2d_bst1_s cn38xxp2;
274 struct cvmx_l2d_bst1_s cn50xx;
275 struct cvmx_l2d_bst1_s cn52xx;
276 struct cvmx_l2d_bst1_s cn52xxp1;
277 struct cvmx_l2d_bst1_s cn56xx;
278 struct cvmx_l2d_bst1_s cn56xxp1;
279 struct cvmx_l2d_bst1_s cn58xx;
280 struct cvmx_l2d_bst1_s cn58xxp1;
281 };
282 typedef union cvmx_l2d_bst1 cvmx_l2d_bst1_t;
283
284 /**
285 * cvmx_l2d_bst2
286 *
287 * L2D_BST2 = L2C Data Store QUAD2 BIST Status Register
288 *
289 */
290 union cvmx_l2d_bst2 {
291 uint64_t u64;
292 struct cvmx_l2d_bst2_s {
293 #ifdef __BIG_ENDIAN_BITFIELD
294 uint64_t reserved_34_63 : 30;
295 uint64_t q2stat : 34; /**< Bist Results for QUAD2
296 Failure \#1 Status
297 [16:14] bad bank
298 [13:7] bad high column
299 [6:0] bad low column
300 Failure \#2 Status
301 [33:31] bad bank
302 [30:24] bad high column
303 [23:17] bad low column
304 NOTES: For bad high/low column reporting:
305 0x7f: No failure
306 0x7e: Fatal Defect: 2 or more bad columns
307 0-0x45: Bad column
308 NOTE: If there are less than 2 failures then the
309 bad bank will be 0x7. */
310 #else
311 uint64_t q2stat : 34;
312 uint64_t reserved_34_63 : 30;
313 #endif
314 } s;
315 struct cvmx_l2d_bst2_s cn30xx;
316 struct cvmx_l2d_bst2_s cn31xx;
317 struct cvmx_l2d_bst2_s cn38xx;
318 struct cvmx_l2d_bst2_s cn38xxp2;
319 struct cvmx_l2d_bst2_s cn50xx;
320 struct cvmx_l2d_bst2_s cn52xx;
321 struct cvmx_l2d_bst2_s cn52xxp1;
322 struct cvmx_l2d_bst2_s cn56xx;
323 struct cvmx_l2d_bst2_s cn56xxp1;
324 struct cvmx_l2d_bst2_s cn58xx;
325 struct cvmx_l2d_bst2_s cn58xxp1;
326 };
327 typedef union cvmx_l2d_bst2 cvmx_l2d_bst2_t;
328
329 /**
330 * cvmx_l2d_bst3
331 *
332 * L2D_BST3 = L2C Data Store QUAD3 BIST Status Register
333 *
334 */
335 union cvmx_l2d_bst3 {
336 uint64_t u64;
337 struct cvmx_l2d_bst3_s {
338 #ifdef __BIG_ENDIAN_BITFIELD
339 uint64_t reserved_34_63 : 30;
340 uint64_t q3stat : 34; /**< Bist Results for QUAD3
341 Failure \#1 Status
342 [16:14] bad bank
343 [13:7] bad high column
344 [6:0] bad low column
345 Failure \#2 Status
346 [33:31] bad bank
347 [30:24] bad high column
348 [23:17] bad low column
349 NOTES: For bad high/low column reporting:
350 0x7f: No failure
351 0x7e: Fatal Defect: 2 or more bad columns
352 0-0x45: Bad column
353 NOTE: If there are less than 2 failures then the
354 bad bank will be 0x7. */
355 #else
356 uint64_t q3stat : 34;
357 uint64_t reserved_34_63 : 30;
358 #endif
359 } s;
360 struct cvmx_l2d_bst3_s cn30xx;
361 struct cvmx_l2d_bst3_s cn31xx;
362 struct cvmx_l2d_bst3_s cn38xx;
363 struct cvmx_l2d_bst3_s cn38xxp2;
364 struct cvmx_l2d_bst3_s cn50xx;
365 struct cvmx_l2d_bst3_s cn52xx;
366 struct cvmx_l2d_bst3_s cn52xxp1;
367 struct cvmx_l2d_bst3_s cn56xx;
368 struct cvmx_l2d_bst3_s cn56xxp1;
369 struct cvmx_l2d_bst3_s cn58xx;
370 struct cvmx_l2d_bst3_s cn58xxp1;
371 };
372 typedef union cvmx_l2d_bst3 cvmx_l2d_bst3_t;
373
374 /**
375 * cvmx_l2d_err
376 *
377 * L2D_ERR = L2 Data Errors
378 *
379 * Description: L2 Data ECC SEC/DED Errors and Interrupt Enable
380 */
381 union cvmx_l2d_err {
382 uint64_t u64;
383 struct cvmx_l2d_err_s {
384 #ifdef __BIG_ENDIAN_BITFIELD
385 uint64_t reserved_6_63 : 58;
386 uint64_t bmhclsel : 1; /**< L2 Bit Map Half CacheLine ECC Selector
387
388 When L2C_DBG[L2T]=1/L2D_ERR[ECC_ENA]=0, the BMHCLSEL selects
389 which half cacheline to conditionally latch into
390 the L2D_FSYN0/L2D_FSYN1 registers when an LDD command
391 is detected from the diagnostic PP (see L2C_DBG[PPNUM]).
392 - 0: OW[0-3] ECC (from first 1/2 cacheline) is selected to
393 be conditionally latched into the L2D_FSYN0/1 CSRs.
394 - 1: OW[4-7] ECC (from last 1/2 cacheline) is selected to
395 be conditionally latched into
396 the L2D_FSYN0/1 CSRs. */
397 uint64_t ded_err : 1; /**< L2D Double Error detected (DED) */
398 uint64_t sec_err : 1; /**< L2D Single Error corrected (SEC) */
399 uint64_t ded_intena : 1; /**< L2 Data ECC Double Error Detect(DED) Interrupt Enable bit
400 When set, allows interrupts to be reported on double bit
401 (uncorrectable) errors from the L2 Data Arrays. */
402 uint64_t sec_intena : 1; /**< L2 Data ECC Single Error Correct(SEC) Interrupt Enable bit
403 When set, allows interrupts to be reported on single bit
404 (correctable) errors from the L2 Data Arrays. */
405 uint64_t ecc_ena : 1; /**< L2 Data ECC Enable
406 When set, enables 10-bit SEC/DED codeword for 128bit L2
407 Data Arrays. */
408 #else
409 uint64_t ecc_ena : 1;
410 uint64_t sec_intena : 1;
411 uint64_t ded_intena : 1;
412 uint64_t sec_err : 1;
413 uint64_t ded_err : 1;
414 uint64_t bmhclsel : 1;
415 uint64_t reserved_6_63 : 58;
416 #endif
417 } s;
418 struct cvmx_l2d_err_s cn30xx;
419 struct cvmx_l2d_err_s cn31xx;
420 struct cvmx_l2d_err_s cn38xx;
421 struct cvmx_l2d_err_s cn38xxp2;
422 struct cvmx_l2d_err_s cn50xx;
423 struct cvmx_l2d_err_s cn52xx;
424 struct cvmx_l2d_err_s cn52xxp1;
425 struct cvmx_l2d_err_s cn56xx;
426 struct cvmx_l2d_err_s cn56xxp1;
427 struct cvmx_l2d_err_s cn58xx;
428 struct cvmx_l2d_err_s cn58xxp1;
429 };
430 typedef union cvmx_l2d_err cvmx_l2d_err_t;
431
432 /**
433 * cvmx_l2d_fadr
434 *
435 * L2D_FADR = L2 Failing Address
436 *
437 * Description: L2 Data ECC SEC/DED Failing Address
438 *
439 * Notes:
440 * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data store index.
441 * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
442 */
443 union cvmx_l2d_fadr {
444 uint64_t u64;
445 struct cvmx_l2d_fadr_s {
446 #ifdef __BIG_ENDIAN_BITFIELD
447 uint64_t reserved_19_63 : 45;
448 uint64_t fadru : 1; /**< Failing L2 Data Store Upper Index bit(MSB) */
449 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
450 error) */
451 uint64_t fset : 3; /**< Failing SET# */
452 uint64_t fadr : 11; /**< Failing L2 Data Store Lower Index bits
453 (NOTE: L2 Data Store Index is for each 1/2 cacheline)
454 [FADRU, FADR[10:1]]: cacheline index[17:7]
455 FADR[0]: 1/2 cacheline index
456 NOTE: FADR[1] is used to select between upper/lower 1MB
457 physical L2 Data Store banks. */
458 #else
459 uint64_t fadr : 11;
460 uint64_t fset : 3;
461 uint64_t fowmsk : 4;
462 uint64_t fadru : 1;
463 uint64_t reserved_19_63 : 45;
464 #endif
465 } s;
466 struct cvmx_l2d_fadr_cn30xx {
467 #ifdef __BIG_ENDIAN_BITFIELD
468 uint64_t reserved_18_63 : 46;
469 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
470 error) */
471 uint64_t reserved_13_13 : 1;
472 uint64_t fset : 2; /**< Failing SET# */
473 uint64_t reserved_9_10 : 2;
474 uint64_t fadr : 9; /**< Failing L2 Data Store Index(1of512 = 1/2 CL address) */
475 #else
476 uint64_t fadr : 9;
477 uint64_t reserved_9_10 : 2;
478 uint64_t fset : 2;
479 uint64_t reserved_13_13 : 1;
480 uint64_t fowmsk : 4;
481 uint64_t reserved_18_63 : 46;
482 #endif
483 } cn30xx;
484 struct cvmx_l2d_fadr_cn31xx {
485 #ifdef __BIG_ENDIAN_BITFIELD
486 uint64_t reserved_18_63 : 46;
487 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
488 error) */
489 uint64_t reserved_13_13 : 1;
490 uint64_t fset : 2; /**< Failing SET# */
491 uint64_t reserved_10_10 : 1;
492 uint64_t fadr : 10; /**< Failing L2 Data Store Index
493 (1 of 1024 = half cacheline indices) */
494 #else
495 uint64_t fadr : 10;
496 uint64_t reserved_10_10 : 1;
497 uint64_t fset : 2;
498 uint64_t reserved_13_13 : 1;
499 uint64_t fowmsk : 4;
500 uint64_t reserved_18_63 : 46;
501 #endif
502 } cn31xx;
503 struct cvmx_l2d_fadr_cn38xx {
504 #ifdef __BIG_ENDIAN_BITFIELD
505 uint64_t reserved_18_63 : 46;
506 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
507 error) */
508 uint64_t fset : 3; /**< Failing SET# */
509 uint64_t fadr : 11; /**< Failing L2 Data Store Index (1of2K = 1/2 CL address) */
510 #else
511 uint64_t fadr : 11;
512 uint64_t fset : 3;
513 uint64_t fowmsk : 4;
514 uint64_t reserved_18_63 : 46;
515 #endif
516 } cn38xx;
517 struct cvmx_l2d_fadr_cn38xx cn38xxp2;
518 struct cvmx_l2d_fadr_cn50xx {
519 #ifdef __BIG_ENDIAN_BITFIELD
520 uint64_t reserved_18_63 : 46;
521 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
522 error) */
523 uint64_t fset : 3; /**< Failing SET# */
524 uint64_t reserved_8_10 : 3;
525 uint64_t fadr : 8; /**< Failing L2 Data Store Lower Index bits
526 (NOTE: L2 Data Store Index is for each 1/2 cacheline)
527 FADR[7:1]: cacheline index[13:7]
528 FADR[0]: 1/2 cacheline index */
529 #else
530 uint64_t fadr : 8;
531 uint64_t reserved_8_10 : 3;
532 uint64_t fset : 3;
533 uint64_t fowmsk : 4;
534 uint64_t reserved_18_63 : 46;
535 #endif
536 } cn50xx;
537 struct cvmx_l2d_fadr_cn52xx {
538 #ifdef __BIG_ENDIAN_BITFIELD
539 uint64_t reserved_18_63 : 46;
540 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
541 error) */
542 uint64_t fset : 3; /**< Failing SET# */
543 uint64_t reserved_10_10 : 1;
544 uint64_t fadr : 10; /**< Failing L2 Data Store Lower Index bits
545 (NOTE: L2 Data Store Index is for each 1/2 cacheline)
546 FADR[9:1]: cacheline index[15:7]
547 FADR[0]: 1/2 cacheline index */
548 #else
549 uint64_t fadr : 10;
550 uint64_t reserved_10_10 : 1;
551 uint64_t fset : 3;
552 uint64_t fowmsk : 4;
553 uint64_t reserved_18_63 : 46;
554 #endif
555 } cn52xx;
556 struct cvmx_l2d_fadr_cn52xx cn52xxp1;
557 struct cvmx_l2d_fadr_s cn56xx;
558 struct cvmx_l2d_fadr_s cn56xxp1;
559 struct cvmx_l2d_fadr_s cn58xx;
560 struct cvmx_l2d_fadr_s cn58xxp1;
561 };
562 typedef union cvmx_l2d_fadr cvmx_l2d_fadr_t;
563
564 /**
565 * cvmx_l2d_fsyn0
566 *
567 * L2D_FSYN0 = L2 Failing Syndrome [OW0,4 / OW1,5]
568 *
569 * Description: L2 Data ECC SEC/DED Failing Syndrome for lower cache line
570 *
571 * Notes:
572 * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
573 * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
574 */
575 union cvmx_l2d_fsyn0 {
576 uint64_t u64;
577 struct cvmx_l2d_fsyn0_s {
578 #ifdef __BIG_ENDIAN_BITFIELD
579 uint64_t reserved_20_63 : 44;
580 uint64_t fsyn_ow1 : 10; /**< Failing L2 Data Store SYNDROME OW[1,5]
581 When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR]
582 or L2D_ERR[DED_ERR] are set, this field represents
583 the failing OWECC syndrome for the half cacheline
584 indexed by L2D_FADR[FADR].
585 NOTE: The L2D_FADR[FOWMSK] further qualifies which
586 OW lane(1of4) detected the error.
587 When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD
588 command from the diagnostic PP will conditionally latch
589 the raw OWECC for the selected half cacheline.
590 (see: L2D_ERR[BMHCLSEL] */
591 uint64_t fsyn_ow0 : 10; /**< Failing L2 Data Store SYNDROME OW[0,4]
592 When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR]
593 or L2D_ERR[DED_ERR] are set, this field represents
594 the failing OWECC syndrome for the half cacheline
595 indexed by L2D_FADR[FADR].
596 NOTE: The L2D_FADR[FOWMSK] further qualifies which
597 OW lane(1of4) detected the error.
598 When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD
599 (L1 load-miss) from the diagnostic PP will conditionally
600 latch the raw OWECC for the selected half cacheline.
601 (see: L2D_ERR[BMHCLSEL] */
602 #else
603 uint64_t fsyn_ow0 : 10;
604 uint64_t fsyn_ow1 : 10;
605 uint64_t reserved_20_63 : 44;
606 #endif
607 } s;
608 struct cvmx_l2d_fsyn0_s cn30xx;
609 struct cvmx_l2d_fsyn0_s cn31xx;
610 struct cvmx_l2d_fsyn0_s cn38xx;
611 struct cvmx_l2d_fsyn0_s cn38xxp2;
612 struct cvmx_l2d_fsyn0_s cn50xx;
613 struct cvmx_l2d_fsyn0_s cn52xx;
614 struct cvmx_l2d_fsyn0_s cn52xxp1;
615 struct cvmx_l2d_fsyn0_s cn56xx;
616 struct cvmx_l2d_fsyn0_s cn56xxp1;
617 struct cvmx_l2d_fsyn0_s cn58xx;
618 struct cvmx_l2d_fsyn0_s cn58xxp1;
619 };
620 typedef union cvmx_l2d_fsyn0 cvmx_l2d_fsyn0_t;
621
622 /**
623 * cvmx_l2d_fsyn1
624 *
625 * L2D_FSYN1 = L2 Failing Syndrome [OW2,6 / OW3,7]
626 *
627 * Description: L2 Data ECC SEC/DED Failing Syndrome for upper cache line
628 *
629 * Notes:
630 * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
631 * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
632 */
633 union cvmx_l2d_fsyn1 {
634 uint64_t u64;
635 struct cvmx_l2d_fsyn1_s {
636 #ifdef __BIG_ENDIAN_BITFIELD
637 uint64_t reserved_20_63 : 44;
638 uint64_t fsyn_ow3 : 10; /**< Failing L2 Data Store SYNDROME OW[3,7] */
639 uint64_t fsyn_ow2 : 10; /**< Failing L2 Data Store SYNDROME OW[2,5] */
640 #else
641 uint64_t fsyn_ow2 : 10;
642 uint64_t fsyn_ow3 : 10;
643 uint64_t reserved_20_63 : 44;
644 #endif
645 } s;
646 struct cvmx_l2d_fsyn1_s cn30xx;
647 struct cvmx_l2d_fsyn1_s cn31xx;
648 struct cvmx_l2d_fsyn1_s cn38xx;
649 struct cvmx_l2d_fsyn1_s cn38xxp2;
650 struct cvmx_l2d_fsyn1_s cn50xx;
651 struct cvmx_l2d_fsyn1_s cn52xx;
652 struct cvmx_l2d_fsyn1_s cn52xxp1;
653 struct cvmx_l2d_fsyn1_s cn56xx;
654 struct cvmx_l2d_fsyn1_s cn56xxp1;
655 struct cvmx_l2d_fsyn1_s cn58xx;
656 struct cvmx_l2d_fsyn1_s cn58xxp1;
657 };
658 typedef union cvmx_l2d_fsyn1 cvmx_l2d_fsyn1_t;
659
660 /**
661 * cvmx_l2d_fus0
662 *
663 * L2D_FUS0 = L2C Data Store QUAD0 Fuse Register
664 *
665 */
666 union cvmx_l2d_fus0 {
667 uint64_t u64;
668 struct cvmx_l2d_fus0_s {
669 #ifdef __BIG_ENDIAN_BITFIELD
670 uint64_t reserved_34_63 : 30;
671 uint64_t q0fus : 34; /**< Fuse Register for QUAD0
672 This is purely for debug and not needed in the general
673 manufacturing flow.
674 Note that the fuse are complementary (Assigning a
675 fuse to 1 will read as a zero). This means the case
676 where no fuses are blown result in these csr's showing
677 all ones.
678 Failure \#1 Fuse Mapping
679 [16:14] bad bank
680 [13:7] bad high column
681 [6:0] bad low column
682 Failure \#2 Fuse Mapping
683 [33:31] bad bank
684 [30:24] bad high column
685 [23:17] bad low column */
686 #else
687 uint64_t q0fus : 34;
688 uint64_t reserved_34_63 : 30;
689 #endif
690 } s;
691 struct cvmx_l2d_fus0_s cn30xx;
692 struct cvmx_l2d_fus0_s cn31xx;
693 struct cvmx_l2d_fus0_s cn38xx;
694 struct cvmx_l2d_fus0_s cn38xxp2;
695 struct cvmx_l2d_fus0_s cn50xx;
696 struct cvmx_l2d_fus0_s cn52xx;
697 struct cvmx_l2d_fus0_s cn52xxp1;
698 struct cvmx_l2d_fus0_s cn56xx;
699 struct cvmx_l2d_fus0_s cn56xxp1;
700 struct cvmx_l2d_fus0_s cn58xx;
701 struct cvmx_l2d_fus0_s cn58xxp1;
702 };
703 typedef union cvmx_l2d_fus0 cvmx_l2d_fus0_t;
704
705 /**
706 * cvmx_l2d_fus1
707 *
708 * L2D_FUS1 = L2C Data Store QUAD1 Fuse Register
709 *
710 */
711 union cvmx_l2d_fus1 {
712 uint64_t u64;
713 struct cvmx_l2d_fus1_s {
714 #ifdef __BIG_ENDIAN_BITFIELD
715 uint64_t reserved_34_63 : 30;
716 uint64_t q1fus : 34; /**< Fuse Register for QUAD1
717 This is purely for debug and not needed in the general
718 manufacturing flow.
719 Note that the fuse are complementary (Assigning a
720 fuse to 1 will read as a zero). This means the case
721 where no fuses are blown result in these csr's showing
722 all ones.
723 Failure \#1 Fuse Mapping
724 [16:14] bad bank
725 [13:7] bad high column
726 [6:0] bad low column
727 Failure \#2 Fuse Mapping
728 [33:31] bad bank
729 [30:24] bad high column
730 [23:17] bad low column */
731 #else
732 uint64_t q1fus : 34;
733 uint64_t reserved_34_63 : 30;
734 #endif
735 } s;
736 struct cvmx_l2d_fus1_s cn30xx;
737 struct cvmx_l2d_fus1_s cn31xx;
738 struct cvmx_l2d_fus1_s cn38xx;
739 struct cvmx_l2d_fus1_s cn38xxp2;
740 struct cvmx_l2d_fus1_s cn50xx;
741 struct cvmx_l2d_fus1_s cn52xx;
742 struct cvmx_l2d_fus1_s cn52xxp1;
743 struct cvmx_l2d_fus1_s cn56xx;
744 struct cvmx_l2d_fus1_s cn56xxp1;
745 struct cvmx_l2d_fus1_s cn58xx;
746 struct cvmx_l2d_fus1_s cn58xxp1;
747 };
748 typedef union cvmx_l2d_fus1 cvmx_l2d_fus1_t;
749
750 /**
751 * cvmx_l2d_fus2
752 *
753 * L2D_FUS2 = L2C Data Store QUAD2 Fuse Register
754 *
755 */
756 union cvmx_l2d_fus2 {
757 uint64_t u64;
758 struct cvmx_l2d_fus2_s {
759 #ifdef __BIG_ENDIAN_BITFIELD
760 uint64_t reserved_34_63 : 30;
761 uint64_t q2fus : 34; /**< Fuse Register for QUAD2
762 This is purely for debug and not needed in the general
763 manufacturing flow.
764 Note that the fuse are complementary (Assigning a
765 fuse to 1 will read as a zero). This means the case
766 where no fuses are blown result in these csr's showing
767 all ones.
768 Failure \#1 Fuse Mapping
769 [16:14] bad bank
770 [13:7] bad high column
771 [6:0] bad low column
772 Failure \#2 Fuse Mapping
773 [33:31] bad bank
774 [30:24] bad high column
775 [23:17] bad low column */
776 #else
777 uint64_t q2fus : 34;
778 uint64_t reserved_34_63 : 30;
779 #endif
780 } s;
781 struct cvmx_l2d_fus2_s cn30xx;
782 struct cvmx_l2d_fus2_s cn31xx;
783 struct cvmx_l2d_fus2_s cn38xx;
784 struct cvmx_l2d_fus2_s cn38xxp2;
785 struct cvmx_l2d_fus2_s cn50xx;
786 struct cvmx_l2d_fus2_s cn52xx;
787 struct cvmx_l2d_fus2_s cn52xxp1;
788 struct cvmx_l2d_fus2_s cn56xx;
789 struct cvmx_l2d_fus2_s cn56xxp1;
790 struct cvmx_l2d_fus2_s cn58xx;
791 struct cvmx_l2d_fus2_s cn58xxp1;
792 };
793 typedef union cvmx_l2d_fus2 cvmx_l2d_fus2_t;
794
795 /**
796 * cvmx_l2d_fus3
797 *
798 * L2D_FUS3 = L2C Data Store QUAD3 Fuse Register
799 *
800 */
801 union cvmx_l2d_fus3 {
802 uint64_t u64;
803 struct cvmx_l2d_fus3_s {
804 #ifdef __BIG_ENDIAN_BITFIELD
805 uint64_t reserved_40_63 : 24;
806 uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control
807 These bits are used to 'observe' the EMA[1:0] inputs
808 for the L2 Data Store RAMs which are controlled by
809 either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR.
810 From poweron (dc_ok), the EMA_CTL are driven from
811 FUSE[141:140]. However after the 1st CSR write to the
812 MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
813 from the MIO_FUSE_EMA[EMA] register permanently
814 (until dc_ok). */
815 uint64_t reserved_34_36 : 3;
816 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
817 This is purely for debug and not needed in the general
818 manufacturing flow.
819 Note that the fuses are complementary (Assigning a
820 fuse to 1 will read as a zero). This means the case
821 where no fuses are blown result in these csr's showing
822 all ones.
823 Failure \#1 Fuse Mapping
824 [16:14] bad bank
825 [13:7] bad high column
826 [6:0] bad low column
827 Failure \#2 Fuse Mapping
828 [33:31] bad bank
829 [30:24] bad high column
830 [23:17] bad low column */
831 #else
832 uint64_t q3fus : 34;
833 uint64_t reserved_34_36 : 3;
834 uint64_t ema_ctl : 3;
835 uint64_t reserved_40_63 : 24;
836 #endif
837 } s;
838 struct cvmx_l2d_fus3_cn30xx {
839 #ifdef __BIG_ENDIAN_BITFIELD
840 uint64_t reserved_35_63 : 29;
841 uint64_t crip_64k : 1; /**< This is purely for debug and not needed in the general
842 manufacturing flow.
843 If the FUSE is not-blown, then this bit should read
844 as 0. If the FUSE is blown, then this bit should read
845 as 1. */
846 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
847 This is purely for debug and not needed in the general
848 manufacturing flow.
849 Note that the fuses are complementary (Assigning a
850 fuse to 1 will read as a zero). This means the case
851 where no fuses are blown result in these csr's showing
852 all ones.
853 Failure \#1 Fuse Mapping
854 [16:15] UNUSED
855 [14] bad bank
856 [13:7] bad high column
857 [6:0] bad low column
858 Failure \#2 Fuse Mapping
859 [33:32] UNUSED
860 [31] bad bank
861 [30:24] bad high column
862 [23:17] bad low column */
863 #else
864 uint64_t q3fus : 34;
865 uint64_t crip_64k : 1;
866 uint64_t reserved_35_63 : 29;
867 #endif
868 } cn30xx;
869 struct cvmx_l2d_fus3_cn31xx {
870 #ifdef __BIG_ENDIAN_BITFIELD
871 uint64_t reserved_35_63 : 29;
872 uint64_t crip_128k : 1; /**< This is purely for debug and not needed in the general
873 manufacturing flow.
874 If the FUSE is not-blown, then this bit should read
875 as 0. If the FUSE is blown, then this bit should read
876 as 1. */
877 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
878 This is purely for debug and not needed in the general
879 manufacturing flow.
880 Note that the fuses are complementary (Assigning a
881 fuse to 1 will read as a zero). This means the case
882 where no fuses are blown result in these csr's showing
883 all ones.
884 Failure \#1 Fuse Mapping
885 [16:15] UNUSED
886 [14] bad bank
887 [13:7] bad high column
888 [6:0] bad low column
889 Failure \#2 Fuse Mapping
890 [33:32] UNUSED
891 [31] bad bank
892 [30:24] bad high column
893 [23:17] bad low column */
894 #else
895 uint64_t q3fus : 34;
896 uint64_t crip_128k : 1;
897 uint64_t reserved_35_63 : 29;
898 #endif
899 } cn31xx;
900 struct cvmx_l2d_fus3_cn38xx {
901 #ifdef __BIG_ENDIAN_BITFIELD
902 uint64_t reserved_36_63 : 28;
903 uint64_t crip_256k : 1; /**< This is purely for debug and not needed in the general
904 manufacturing flow.
905 If the FUSE is not-blown, then this bit should read
906 as 0. If the FUSE is blown, then this bit should read
907 as 1.
908 *** NOTE: Pass2 Addition */
909 uint64_t crip_512k : 1; /**< This is purely for debug and not needed in the general
910 manufacturing flow.
911 If the FUSE is not-blown, then this bit should read
912 as 0. If the FUSE is blown, then this bit should read
913 as 1.
914 *** NOTE: Pass2 Addition */
915 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
916 This is purely for debug and not needed in the general
917 manufacturing flow.
918 Note that the fuses are complementary (Assigning a
919 fuse to 1 will read as a zero). This means the case
920 where no fuses are blown result in these csr's showing
921 all ones.
922 Failure \#1 Fuse Mapping
923 [16:14] bad bank
924 [13:7] bad high column
925 [6:0] bad low column
926 Failure \#2 Fuse Mapping
927 [33:31] bad bank
928 [30:24] bad high column
929 [23:17] bad low column */
930 #else
931 uint64_t q3fus : 34;
932 uint64_t crip_512k : 1;
933 uint64_t crip_256k : 1;
934 uint64_t reserved_36_63 : 28;
935 #endif
936 } cn38xx;
937 struct cvmx_l2d_fus3_cn38xx cn38xxp2;
938 struct cvmx_l2d_fus3_cn50xx {
939 #ifdef __BIG_ENDIAN_BITFIELD
940 uint64_t reserved_40_63 : 24;
941 uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control
942 These bits are used to 'observe' the EMA[2:0] inputs
943 for the L2 Data Store RAMs which are controlled by
944 either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
945 From poweron (dc_ok), the EMA_CTL are driven from
946 FUSE[141:140]. However after the 1st CSR write to the
947 MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
948 from the MIO_FUSE_EMA[EMA] register permanently
949 (until dc_ok). */
950 uint64_t reserved_36_36 : 1;
951 uint64_t crip_32k : 1; /**< This is purely for debug and not needed in the general
952 manufacturing flow.
953 If the FUSE is not-blown, then this bit should read
954 as 0. If the FUSE is blown, then this bit should read
955 as 1. */
956 uint64_t crip_64k : 1; /**< This is purely for debug and not needed in the general
957 manufacturing flow.
958 If the FUSE is not-blown, then this bit should read
959 as 0. If the FUSE is blown, then this bit should read
960 as 1. */
961 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
962 This is purely for debug and not needed in the general
963 manufacturing flow.
964 Note that the fuses are complementary (Assigning a
965 fuse to 1 will read as a zero). This means the case
966 where no fuses are blown result in these csr's showing
967 all ones.
968 Failure \#1 Fuse Mapping
969 [16:14] UNUSED (5020 uses single physical bank per quad)
970 [13:7] bad high column
971 [6:0] bad low column
972 Failure \#2 Fuse Mapping
973 [33:31] UNUSED (5020 uses single physical bank per quad)
974 [30:24] bad high column
975 [23:17] bad low column */
976 #else
977 uint64_t q3fus : 34;
978 uint64_t crip_64k : 1;
979 uint64_t crip_32k : 1;
980 uint64_t reserved_36_36 : 1;
981 uint64_t ema_ctl : 3;
982 uint64_t reserved_40_63 : 24;
983 #endif
984 } cn50xx;
985 struct cvmx_l2d_fus3_cn52xx {
986 #ifdef __BIG_ENDIAN_BITFIELD
987 uint64_t reserved_40_63 : 24;
988 uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control
989 These bits are used to 'observe' the EMA[2:0] inputs
990 for the L2 Data Store RAMs which are controlled by
991 either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
992 From poweron (dc_ok), the EMA_CTL are driven from
993 FUSE[141:140]. However after the 1st CSR write to the
994 MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
995 from the MIO_FUSE_EMA[EMA] register permanently
996 (until dc_ok). */
997 uint64_t reserved_36_36 : 1;
998 uint64_t crip_128k : 1; /**< This is purely for debug and not needed in the general
999 manufacturing flow.
1000 If the FUSE is not-blown, then this bit should read
1001 as 0. If the FUSE is blown, then this bit should read
1002 as 1. */
1003 uint64_t crip_256k : 1; /**< This is purely for debug and not needed in the general
1004 manufacturing flow.
1005 If the FUSE is not-blown, then this bit should read
1006 as 0. If the FUSE is blown, then this bit should read
1007 as 1. */
1008 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
1009 This is purely for debug and not needed in the general
1010 manufacturing flow.
1011 Note that the fuses are complementary (Assigning a
1012 fuse to 1 will read as a zero). This means the case
1013 where no fuses are blown result in these csr's showing
1014 all ones.
1015 Failure \#1 Fuse Mapping
1016 [16:14] UNUSED (5020 uses single physical bank per quad)
1017 [13:7] bad high column
1018 [6:0] bad low column
1019 Failure \#2 Fuse Mapping
1020 [33:31] UNUSED (5020 uses single physical bank per quad)
1021 [30:24] bad high column
1022 [23:17] bad low column */
1023 #else
1024 uint64_t q3fus : 34;
1025 uint64_t crip_256k : 1;
1026 uint64_t crip_128k : 1;
1027 uint64_t reserved_36_36 : 1;
1028 uint64_t ema_ctl : 3;
1029 uint64_t reserved_40_63 : 24;
1030 #endif
1031 } cn52xx;
1032 struct cvmx_l2d_fus3_cn52xx cn52xxp1;
1033 struct cvmx_l2d_fus3_cn56xx {
1034 #ifdef __BIG_ENDIAN_BITFIELD
1035 uint64_t reserved_40_63 : 24;
1036 uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control
1037 These bits are used to 'observe' the EMA[2:0] inputs
1038 for the L2 Data Store RAMs which are controlled by
1039 either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
1040 From poweron (dc_ok), the EMA_CTL are driven from
1041 FUSE[141:140]. However after the 1st CSR write to the
1042 MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
1043 from the MIO_FUSE_EMA[EMA] register permanently
1044 (until dc_ok). */
1045 uint64_t reserved_36_36 : 1;
1046 uint64_t crip_512k : 1; /**< This is purely for debug and not needed in the general
1047 manufacturing flow.
1048 If the FUSE is not-blown, then this bit should read
1049 as 0. If the FUSE is blown, then this bit should read
1050 as 1.
1051 *** NOTE: Pass2 Addition */
1052 uint64_t crip_1024k : 1; /**< This is purely for debug and not needed in the general
1053 manufacturing flow.
1054 If the FUSE is not-blown, then this bit should read
1055 as 0. If the FUSE is blown, then this bit should read
1056 as 1.
1057 *** NOTE: Pass2 Addition */
1058 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
1059 This is purely for debug and not needed in the general
1060 manufacturing flow.
1061 Note that the fuses are complementary (Assigning a
1062 fuse to 1 will read as a zero). This means the case
1063 where no fuses are blown result in these csr's showing
1064 all ones.
1065 Failure \#1 Fuse Mapping
1066 [16:14] bad bank
1067 [13:7] bad high column
1068 [6:0] bad low column
1069 Failure \#2 Fuse Mapping
1070 [33:31] bad bank
1071 [30:24] bad high column
1072 [23:17] bad low column */
1073 #else
1074 uint64_t q3fus : 34;
1075 uint64_t crip_1024k : 1;
1076 uint64_t crip_512k : 1;
1077 uint64_t reserved_36_36 : 1;
1078 uint64_t ema_ctl : 3;
1079 uint64_t reserved_40_63 : 24;
1080 #endif
1081 } cn56xx;
1082 struct cvmx_l2d_fus3_cn56xx cn56xxp1;
1083 struct cvmx_l2d_fus3_cn58xx {
1084 #ifdef __BIG_ENDIAN_BITFIELD
1085 uint64_t reserved_39_63 : 25;
1086 uint64_t ema_ctl : 2; /**< L2 Data Store EMA Control
1087 These bits are used to 'observe' the EMA[1:0] inputs
1088 for the L2 Data Store RAMs which are controlled by
1089 either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR.
1090 From poweron (dc_ok), the EMA_CTL are driven from
1091 FUSE[141:140]. However after the 1st CSR write to the
1092 MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
1093 from the MIO_FUSE_EMA[EMA] register permanently
1094 (until dc_ok). */
1095 uint64_t reserved_36_36 : 1;
1096 uint64_t crip_512k : 1; /**< This is purely for debug and not needed in the general
1097 manufacturing flow.
1098 If the FUSE is not-blown, then this bit should read
1099 as 0. If the FUSE is blown, then this bit should read
1100 as 1.
1101 *** NOTE: Pass2 Addition */
1102 uint64_t crip_1024k : 1; /**< This is purely for debug and not needed in the general
1103 manufacturing flow.
1104 If the FUSE is not-blown, then this bit should read
1105 as 0. If the FUSE is blown, then this bit should read
1106 as 1.
1107 *** NOTE: Pass2 Addition */
1108 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
1109 This is purely for debug and not needed in the general
1110 manufacturing flow.
1111 Note that the fuses are complementary (Assigning a
1112 fuse to 1 will read as a zero). This means the case
1113 where no fuses are blown result in these csr's showing
1114 all ones.
1115 Failure \#1 Fuse Mapping
1116 [16:14] bad bank
1117 [13:7] bad high column
1118 [6:0] bad low column
1119 Failure \#2 Fuse Mapping
1120 [33:31] bad bank
1121 [30:24] bad high column
1122 [23:17] bad low column */
1123 #else
1124 uint64_t q3fus : 34;
1125 uint64_t crip_1024k : 1;
1126 uint64_t crip_512k : 1;
1127 uint64_t reserved_36_36 : 1;
1128 uint64_t ema_ctl : 2;
1129 uint64_t reserved_39_63 : 25;
1130 #endif
1131 } cn58xx;
1132 struct cvmx_l2d_fus3_cn58xx cn58xxp1;
1133 };
1134 typedef union cvmx_l2d_fus3 cvmx_l2d_fus3_t;
1135
1136 #endif
1137