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Searched refs:control (Results 1 – 25 of 1090) sorted by relevance

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/f-stack/freebsd/netinet/
H A Dsctp_indata.c526 control->sinfo_stream, control->mid); in sctp_queue_data_to_stream()
587 control, control->on_strm_q); in sctp_queue_data_to_stream()
1086 control, control->end_added, control->mid, control->top_fsn, control->fsn_included); in sctp_deliver_reasm_check()
1094 control, control->on_strm_q); in sctp_deliver_reasm_check()
1151 control, control->end_added, control->mid, in sctp_deliver_reasm_check()
1152 control->top_fsn, control->fsn_included, in sctp_deliver_reasm_check()
1159 control, control->on_strm_q); in sctp_deliver_reasm_check()
1201 control, control->end_added, control->mid, control->top_fsn, control->fsn_included, in sctp_deliver_reasm_check()
1215 control, control->on_strm_q); in sctp_deliver_reasm_check()
5461 strm, control, control->on_strm_q); in sctp_flush_reassm_for_str_seq()
[all …]
H A Dsctputil.c3364 control, in sctp_notify_peer_addr_change()
3495 control, in sctp_notify_send_failed()
3593 control, in sctp_notify_send_failed2()
3640 control, in sctp_notify_adaptation_layer()
3762 control, in sctp_notify_shutdown_event()
3865 control, in sctp_notify_stream_reset_add()
3915 control, in sctp_notify_stream_reset_tsn()
5717 control, so, control->on_strm_q); in sctp_sorecvmsg()
6144 control, so, control->on_strm_q); in sctp_sorecvmsg()
6321 control->data = control->tail_mbuf = NULL; in sctp_sorecvmsg()
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/net/
H A Dmicrel-ksz90x1.txt48 - rxc-skew-ps : Skew control of RXC pad
49 - rxdv-skew-ps : Skew control of RX CTL pad
50 - txc-skew-ps : Skew control of TXC pad
51 - txen-skew-ps : Skew control of TX CTL pad
52 - rxd0-skew-ps : Skew control of RX data 0 pad
53 - rxd1-skew-ps : Skew control of RX data 1 pad
54 - rxd2-skew-ps : Skew control of RX data 2 pad
55 - rxd3-skew-ps : Skew control of RX data 3 pad
56 - txd0-skew-ps : Skew control of TX data 0 pad
77 - rxdv-skew-ps : Skew control of RX CTL pad
[all …]
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Dkeystone-k2hk-clocks.dtsi15 reg-names = "control";
32 reg-names = "control";
41 reg-names = "control";
50 reg-names = "control";
59 reg-names = "control", "domain";
69 reg-names = "control", "domain";
79 reg-names = "control", "domain";
89 reg-names = "control", "domain";
99 reg-names = "control", "domain";
109 reg-names = "control", "domain";
[all …]
H A Dkeystone-k2l-clocks.dtsi15 reg-names = "control";
32 reg-names = "control";
41 reg-names = "control";
49 reg-names = "control", "domain";
60 reg-names = "control", "domain";
70 reg-names = "control", "domain";
80 reg-names = "control", "domain";
90 reg-names = "control", "domain";
100 reg-names = "control", "domain";
110 reg-names = "control", "domain";
[all …]
H A Dkeystone-clocks.dtsi166 reg-names = "control", "domain";
177 reg-names = "control", "domain";
187 reg-names = "control", "domain";
198 reg-names = "control", "domain";
208 reg-names = "control", "domain";
218 reg-names = "control", "domain";
228 reg-names = "control", "domain";
238 reg-names = "control", "domain";
248 reg-names = "control", "domain";
258 reg-names = "control", "domain";
[all …]
H A Dkeystone-k2e-clocks.dtsi14 reg-names = "control", "multiplier", "post-divider";
23 reg-names = "control";
32 reg-names = "control";
41 reg-names = "control", "domain";
51 reg-names = "control", "domain";
61 reg-names = "control", "domain";
71 reg-names = "control", "domain";
H A Dexynos5420-cpus.dtsi31 cci-control-port = <&cci_control1>;
43 cci-control-port = <&cci_control1>;
55 cci-control-port = <&cci_control1>;
67 cci-control-port = <&cci_control1>;
79 cci-control-port = <&cci_control0>;
91 cci-control-port = <&cci_control0>;
103 cci-control-port = <&cci_control0>;
115 cci-control-port = <&cci_control0>;
/f-stack/freebsd/contrib/device-tree/Bindings/sram/
H A Dallwinner,sun4i-a10-system-control.yaml29 - const: allwinner,sun4i-a10-system-control
30 - const: allwinner,sun5i-a13-system-control
32 - const: allwinner,sun7i-a20-system-control
33 - const: allwinner,sun4i-a10-system-control
34 - const: allwinner,sun8i-a23-system-control
35 - const: allwinner,sun8i-h3-system-control
38 - const: allwinner,sun50i-a64-system-control
39 - const: allwinner,sun50i-h5-system-control
41 - const: allwinner,sun50i-h6-system-control
45 - const: allwinner,sun4i-a10-system-control
[all …]
/f-stack/freebsd/contrib/octeon-sdk/
H A Dcvmx-dfa.c68 cvmx_dfa_difctl_t control; in cvmx_dfa_initialize() local
77 control.u64 = 0; in cvmx_dfa_initialize()
78 control.s.dwbcnt = CVMX_FPA_DFA_POOL_SIZE / 128; in cvmx_dfa_initialize()
79 control.s.pool = CVMX_FPA_DFA_POOL; in cvmx_dfa_initialize()
80 control.s.size = (CVMX_FPA_DFA_POOL_SIZE - 8) / sizeof(cvmx_dfa_command_t); in cvmx_dfa_initialize()
82 cvmx_write_csr(CVMX_DFA_DIFCTL, control.u64); in cvmx_dfa_initialize()
H A Dcvmx-hfa.c81 cvmx_dfa_difctl_t control; in cvmx_hfa_initialize() local
93 control.u64 = 0; in cvmx_hfa_initialize()
94 control.s.dwbcnt = CVMX_FPA_DFA_POOL_SIZE / 128; in cvmx_hfa_initialize()
95 control.s.pool = CVMX_FPA_DFA_POOL; in cvmx_hfa_initialize()
96 control.s.size = cmdsize / sizeof(cvmx_dfa_command_t); in cvmx_hfa_initialize()
98 cvmx_write_csr(CVMX_DFA_DIFCTL, control.u64); in cvmx_hfa_initialize()
H A Dcvmx-log.c390 cvmx_core_perf_control_t control; in cvmx_log_perf_setup() local
392 control.u32 = 0; in cvmx_log_perf_setup()
393 control.s.event = counter1; in cvmx_log_perf_setup()
394 control.s.u = 1; in cvmx_log_perf_setup()
395 control.s.s = 1; in cvmx_log_perf_setup()
396 control.s.k = 1; in cvmx_log_perf_setup()
397 control.s.ex = 1; in cvmx_log_perf_setup()
398 asm ("mtc0 %0, $25, 0\n" : : "r"(control.u32)); in cvmx_log_perf_setup()
399 control.s.event = counter2; in cvmx_log_perf_setup()
400 asm ("mtc0 %0, $25, 2\n" : : "r"(control.u32)); in cvmx_log_perf_setup()
[all …]
H A Dcvmx-tim.c241 cvmx_tim_control_t control; in cvmx_tim_start() local
243 control.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS); in cvmx_tim_start()
244 control.s.enable_dwb = 1; in cvmx_tim_start()
245 control.s.enable_timers = 1; in cvmx_tim_start()
249 cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64); in cvmx_tim_start()
258 cvmx_tim_control_t control; in cvmx_tim_stop() local
259 control.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS); in cvmx_tim_stop()
260 control.s.enable_dwb = 0; in cvmx_tim_stop()
261 control.s.enable_timers = 0; in cvmx_tim_stop()
262 cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64); in cvmx_tim_stop()
H A Dcvmx-debug.h149 uint64_t control[4]; member
168 F(hw_ibp.control[0]); \
169 F(hw_ibp.control[1]); \
170 F(hw_ibp.control[2]); \
171 F(hw_ibp.control[3]);
188 F(hw_dbp.control[0]); \
189 F(hw_dbp.control[1]); \
190 F(hw_dbp.control[2]); \
191 F(hw_dbp.control[3]);
/f-stack/freebsd/contrib/device-tree/Bindings/clock/
H A Dnvidia,tegra124-dfll.txt17 - registers for the DFLL control logic.
25 - soc: Clock source for the DFLL control logic.
31 - dvco: Reset control for the DFLL DVCO.
36 the I2C register, control values and supported voltages.
38 Required properties for the control loop parameters:
39 - nvidia,sample-rate: Sample rate of the DFLL control loop.
46 Optional properties for the control loop parameters:
62 that the regulator supports when PWM control is enabled.
77 reg = <0 0x70110000 0 0x100>, /* DFLL control */
106 reg = <0 0x70110000 0 0x100>, /* DFLL control */
[all …]
H A Dpistachio-clock.txt5 general control, and top general control) which are instantiated individually
31 top-level general control.
71 Peripheral general control:
74 The peripheral general control block generates system interface clocks and
76 control registers. The system clock ("sys") generated by the peripheral clock
82 control registers.
99 Top-level general control:
102 The top-level general control block contains miscellaneous control registers and
108 control registers.
/f-stack/dpdk/drivers/raw/ifpga/base/
H A Difpga_feature_dev.c19 struct feature_port_control control; in __fpga_port_enable() local
30 control.csr = readq(&port_hdr->control); in __fpga_port_enable()
31 control.port_sftrst = 0x0; in __fpga_port_enable()
32 writeq(control.csr, &port_hdr->control); in __fpga_port_enable()
38 struct feature_port_control control; in __fpga_port_disable() local
48 control.csr = readq(&port_hdr->control); in __fpga_port_disable()
49 control.port_sftrst = 0x1; in __fpga_port_disable()
50 writeq(control.csr, &port_hdr->control); in __fpga_port_disable()
57 control.port_sftrst_ack = 1; in __fpga_port_disable()
59 if (fpga_wait_register_field(port_sftrst_ack, control, in __fpga_port_disable()
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/phy/
H A Dti-phy.txt7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
20 - reg-names: "otghs_control" for control-phy-otghs
21 "power", "pcie_pcs" and "control_sma" for control-phy-pcie
24 omap_control_usb: omap-control-usb@4a002300 {
25 compatible = "ti,control-phy-otghs";
53 - syscon-phy-power : phandle/offset pair. Phandle to the system control
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/thermal/
H A Darmada-thermal.txt20 to the status register (4B). The second one points to the control
24 "control MSB/control 1", with size of 4 (deprecated binding), or point
25 to "control LSB/control 0" with size of 8 (current binding). All other
26 compatibles must point to "control LSB/control 0" with size of 8.
/f-stack/freebsd/contrib/device-tree/Bindings/arm/
H A Dsyna.txt48 * Marvell Berlin CPU control bindings
50 CPU control register allows various operations on CPUs, like resetting them
64 * Marvell Berlin2 chip control binding
66 Marvell Berlin SoCs have a chip control register set providing several
69 chip control registers, so there should be a single DT node only providing the
77 BG2/BG2CD: chip control register set
78 BG2Q: chip control register set and cpu pll registers
80 * Marvell Berlin2 system control binding
82 Marvell Berlin SoCs have a system control register set providing several
89 - reg: address and length of the system control register set
[all …]
/f-stack/freebsd/net/
H A Dif_llc.h53 u_int8_t control; member
63 u_int8_t control; member
67 u_int8_t control; member
79 u_int8_t control; member
84 u_int8_t control; member
98 #define llc_control llc_un.type_u.control
/f-stack/freebsd/contrib/device-tree/Bindings/mfd/
H A Dtps65910.txt115 ti,regulator-ext-sleep-control = <0>;
124 ti,regulator-ext-sleep-control = <4>;
133 ti,regulator-ext-sleep-control = <0>;
142 ti,regulator-ext-sleep-control = <1>;
149 ti,regulator-ext-sleep-control = <0>;
156 ti,regulator-ext-sleep-control = <0>;
163 ti,regulator-ext-sleep-control = <0>;
171 ti,regulator-ext-sleep-control = <0>;
178 ti,regulator-ext-sleep-control = <0>;
185 ti,regulator-ext-sleep-control = <0>;
[all …]
H A Dti-keystone-devctrl.txt1 * Device tree bindings for Texas Instruments keystone device state control
3 The Keystone II devices have a set of registers that are used to control
11 - reg: contains offset/length value for device state control
16 devctrl: device-state-control@02620000 {
/f-stack/freebsd/contrib/device-tree/Bindings/gpio/
H A Dxylon,logicvc-gpio.yaml18 The controller exposes GPIOs from the display and power control registers,
20 - GPIO[4:0] (display control) mapped to index 0-4
21 - EN_BLIGHT (power control) mapped to index 5
22 - EN_VDD (power control) mapped to index 6
23 - EN_VEE (power control) mapped to index 7
24 - V_EN (power control) mapped to index 8
/f-stack/freebsd/contrib/device-tree/Bindings/reset/
H A Dti-syscon-reset.txt4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
30 - ti,reset-bits : Contains the reset control register information
33 Cell #1 : offset of the reset assert control
36 assert control register
37 Cell #3 : offset of the reset deassert control
40 deassert control register
45 Cell #7 : Flags used to control reset behavior,

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