1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (C) 2019 Marvell International Ltd. 3 */ 4 5 #ifndef _OTX2_CRYPTODEV_H_ 6 #define _OTX2_CRYPTODEV_H_ 7 8 #include "cpt_common.h" 9 #include "cpt_hw_types.h" 10 11 #include "otx2_dev.h" 12 13 /* Marvell OCTEON TX2 Crypto PMD device name */ 14 #define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2 15 16 #define OTX2_CPT_MAX_LFS 64 17 #define OTX2_CPT_MAX_QUEUES_PER_VF 64 18 #define OTX2_CPT_PMD_VERSION 3 19 20 /** 21 * Device private data 22 */ 23 struct otx2_cpt_vf { 24 struct otx2_dev otx2_dev; 25 /**< Base class */ 26 uint16_t max_queues; 27 /**< Max queues supported */ 28 uint8_t nb_queues; 29 /**< Number of crypto queues attached */ 30 uint16_t lf_msixoff[OTX2_CPT_MAX_LFS]; 31 /**< MSI-X offsets */ 32 uint8_t err_intr_registered:1; 33 /**< Are error interrupts registered? */ 34 union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES]; 35 /**< CPT device capabilities */ 36 }; 37 38 struct cpt_meta_info { 39 uint64_t deq_op_info[5]; 40 uint64_t comp_code_sz; 41 union cpt_res_s cpt_res __rte_aligned(16); 42 struct cpt_request_info cpt_req; 43 }; 44 45 #define CPT_LOGTYPE otx2_cpt_logtype 46 47 extern int otx2_cpt_logtype; 48 49 /* 50 * Crypto device driver ID 51 */ 52 extern uint8_t otx2_cryptodev_driver_id; 53 54 void otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev); 55 56 #endif /* _OTX2_CRYPTODEV_H_ */ 57