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Searched refs:combining (Results 1 – 12 of 12) sorted by relevance

/f-stack/tools/libxo/libxo/
H A Dxo_wcwidth.h129 static const struct interval combining[] = { in xo_wcwidth() local
187 if (xo_bisearch(ucs, combining, in xo_wcwidth()
188 sizeof(combining) / sizeof(struct interval) - 1)) in xo_wcwidth()
/f-stack/dpdk/doc/guides/rawdevs/
H A Dntb.rst45 NTB PMD needs kernel PCI driver to support write combining (WC) to get
70 echo "base=0x39bfa0000000 size=0x20000000 type=write-combining" >> /proc/mtrr
71 echo "base=0x39bfc0000000 size=0x20000000 type=write-combining" >> /proc/mtrr
80 reg02: base=0x39bfa0000000 (60553728MB), size= 512MB, count=1: write-combining
81 reg03: base=0x39bfc0000000 (60554240MB), size= 512MB, count=1: write-combining
/f-stack/dpdk/doc/guides/bbdevs/
H A Dacc100.rst37 - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE`` : provides an input for HARQ combining
38 - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`` : provides an input for HARQ combining
H A Dfpga_5gnr_fec.rst35 - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE`` : provides an input for HARQ combining
36 - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`` : provides an input for HARQ combining
/f-stack/dpdk/doc/guides/rel_notes/
H A Drelease_20_11.rst58 * **Added write combining store APIs.**
61 that enable write combining stores (depending on architecture).
197 Updated the Intel ixgbe driver to use write combining stores.
201 Updated the Intel i40e driver to use write combining stores.
205 * Added support for write combining stores.
322 * Added support for write combining stores.
H A Drelease_2_1.rst380 * **Enabled combining of the ``-m`` and ``--no-huge`` EAL options.**
382 Added option to allow combining of the ``-m`` and ``--no-huge`` EAL command
/f-stack/freebsd/contrib/device-tree/Bindings/sram/
H A Dsram.yaml55 as write combining. WC is used by default.
/f-stack/dpdk/doc/guides/nics/
H A Dena.rst156 kernel PCI driver must support write combining (WC).
H A Dmlx5.rst383 By default, the HW Tx doorbell is configured as a write-combining register.
384 The register would be flushed to HW usually when the write-combining buffer
705 - As regular cached memory (usually with write combining attribute), if the
713 memory (with write combining), the PMD will perform the extra write memory barrier
H A Dvirtio.rst443 can receive large packets by combining individual descriptors.
/f-stack/dpdk/doc/guides/prog_guide/
H A Dpacket_classif_access_ctrl.rst302 Each set could be assigned its own category and by combining them into a single database,
/f-stack/freebsd/contrib/openzfs/
H A DLICENSE218 You may create a Larger Work by combining Covered Software with