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Searched refs:clk_div (Results 1 – 9 of 9) sorted by relevance

/f-stack/freebsd/mips/ingenic/
H A Djz4780_clk_gen.c139 msk = (1u << sc->clk_descr->clk_div.div_bits) - 1; in jz4780_clk_gen_recalc_freq()
142 reg = (reg + 1) << sc->clk_descr->clk_div.div_lg; in jz4780_clk_gen_recalc_freq()
168 div_reg = divider >> sc->clk_descr->clk_div.div_lg; in jz4780_clk_gen_set_freq()
169 divider = div_reg << sc->clk_descr->clk_div.div_lg; in jz4780_clk_gen_set_freq()
204 reg = CLK_RD_4(sc, sc->clk_descr->clk_div.div_reg); in jz4780_clk_gen_set_freq()
208 if (sc->clk_descr->clk_div.div_ce_bit >= 0) in jz4780_clk_gen_set_freq()
209 reg |= (1u << sc->clk_descr->clk_div.div_ce_bit); in jz4780_clk_gen_set_freq()
211 if (sc->clk_descr->clk_div.div_st_bit >= 0) in jz4780_clk_gen_set_freq()
212 reg &= ~(1u << sc->clk_descr->clk_div.div_st_bit); in jz4780_clk_gen_set_freq()
214 CLK_WR_4(sc, sc->clk_descr->clk_div.div_reg, reg); in jz4780_clk_gen_set_freq()
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H A Djz4780_clock.c111 .clk_div.div_reg = (reg), \
112 .clk_div.div_shift = (shift), \
113 .clk_div.div_bits = (bits), \
114 .clk_div.div_lg = (lg), \
115 .clk_div.div_ce_bit = (ce), \
116 .clk_div.div_st_bit = (st), \
117 .clk_div.div_busy_bit = (bb),
H A Djz4780_clk.h71 struct jz4780_clk_div_descr clk_div; member
/f-stack/freebsd/arm/freescale/vybrid/
H A Dvf_dcu4.c187 uint32_t clk_div; member
274 panel->clk_div = dts_value[0]; in get_panel_info()
310 WRITE4(sc, DCU_DIV_RATIO, panel->clk_div); in dcu_init()
/f-stack/freebsd/arm/allwinner/
H A Da10_hdmi.c603 int error, clk_div, clk_dbl; in a10hdmi_set_videomode() local
616 error = a10hdmi_get_tcon_config(sc, &clk_div, &clk_dbl); in a10hdmi_set_videomode()
633 PLLCTRL0_CP_S | PLLCTRL0_CS | PLLCTRL0_PREDIV(clk_div) | in a10hdmi_set_videomode()
/f-stack/freebsd/contrib/octeon-sdk/
H A Dcvmx-helper-jtag.c90 jtgc.s.clk_div = clock_div; in cvmx_helper_qlm_jtag_init()
H A Dcvmx-ciu-defs.h10552 uint64_t clk_div : 3; /**< Clock divider for QLM JTAG operations. eclk is member
10564 uint64_t clk_div : 3;
10573 uint64_t clk_div : 3; /**< Clock divider for QLM JTAG operations. eclk is member
10587 uint64_t clk_div : 3;
10595 uint64_t clk_div : 3; /**< Clock divider for QLM JTAG operations. eclk is member
10607 uint64_t clk_div : 3;
10615 uint64_t clk_div : 3; /**< Clock divider for QLM JTAG operations. eclk is member
10629 uint64_t clk_div : 3;
/f-stack/freebsd/contrib/alpine-hal/eth/
H A Dal_hal_eth_mac_regs.h474 uint32_t clk_div; member
H A Dal_hal_eth_main.c4324 al_reg_write32(&mac_regs_base->sgmii.clk_div, 0x03320501); in al_eth_flr_rmn()
4337 al_reg_write32(&mac_regs_base->sgmii.clk_div, 0x00320501); in al_eth_flr_rmn()