Home
last modified time | relevance | path

Searched refs:channels (Results 1 – 25 of 624) sorted by relevance

12345678910>>...25

/f-stack/freebsd/contrib/device-tree/Bindings/input/touchscreen/
H A Dresistive-adc-touch.txt6 The device must be connected to an ADC device that provides channels for
9 - iio-channels: must have at least two channels connected to an ADC device.
10 These should correspond to the channels exposed by the ADC device and should
11 have the right index as the ADC device registers them. These channels
13 - iio-channel-names: must have all the channels' names. Mandatory channels
17 - iio-channels: The third channel named "pressure" is optional and can be
28 io-channels = <&adc 24>, <&adc 25>, <&adc 26>;
/f-stack/freebsd/contrib/device-tree/Bindings/spi/
H A Dspi-sprd-adi.txt8 ADI controller has 50 channels including 2 software read/write channels and
9 48 hardware channels to access analog chip. For 2 software read/write channels,
10 users should set ADI registers to access analog chip. For hardware channels,
14 triggered by hardware components instead of ADI software channels.
16 Thus we introduce one property named "sprd,hw-channels" to configure hardware
17 channels, the first value specifies the hardware channel id which is used to
22 one system is reading/writing data by ADI software channels, that should be under
24 data by ADI software channels at the same time, or two parallel routine of setting
28 The new version ADI controller supplies multiple master channels for different
45 - sprd,hw-channels: This is an array of channel values up to 49 channels.
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/dma/
H A Dbrcm,bcm2835-dma.txt3 The BCM2835 DMA controller has 16 channels in total.
4 Only the lower 13 channels have an associated IRQ.
5 Some arbitrary channels are used by the firmware
7 The channels 0,2 and 3 have special functionality
14 to the DMA channels in ascending order.
18 that is shared by all dma channels.
21 - brcm,dma-channel-mask: Bit mask representing the channels
46 /* unused shared irq for all channels */
H A Dsnps,dw-axi-dmac.txt8 - dma-channels: Number of channels supported by hardware.
13 dma-channels. Priority value must be programmed within [0:dma-channels-1]
16 Array size is equal to the number of dma-channels.
33 dma-channels = <4>;
H A Dowl-dma.yaml11 supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
32 DMA channels.
38 dma-channels:
57 - dma-channels
74 dma-channels = <12>;
H A Dste-coh901318.txt10 - #dma-cells: must be set to <1>, as the channels on the
12 - dma-channels: the number of DMA channels handled
22 dma-channels = <40>;
H A Ddma-common.yaml29 Bitmask of available DMA channels in ascending order that are
32 The first item in the array is for channels 0-31, the second is for
33 channels 32-63, etc.
40 dma-channels:
43 Number of DMA channels supported by the controller.
H A Dingenic,dma.yaml48 ingenic,reserved-channels property.
50 ingenic,reserved-channels:
53 Bitmask of channels to reserve for devices that need a specific
54 channel. These channels will only be assigned when explicitely
55 requested by a client. The primary use for this is channels 0 and
79 ingenic,reserved-channels = <0x3>;
H A Dfsl-mxs-dma.txt6 - interrupts : Should contain the interrupt numbers of DMA channels.
9 - dma-channels : Number of channels supported by the DMA controller
31 dma-channels = <16>;
46 dma-channels = <16>;
H A Dmmp-dma.txt13 - #dma-channels: Number of DMA channels supported by the controller (defaults
36 #dma-channels = <16>;
40 * One irq for all channels
48 #dma-channels = <16>;
74 /* One irq for all channels */
H A Dzxdma.txt8 - dma-channels: physical channels supported
9 - dma-requests: virtual channels supported, each virtual channel
22 dma-channels = <24>;
/f-stack/freebsd/contrib/device-tree/Bindings/iio/adc/
H A Dst,stm32-adc.yaml251 st,adc-channels:
259 st,adc-diff-channels:
261 List of differential channels muxed for this ADC. Some channels can
266 Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
287 array that matches "st,adc-channels" and/or "st,adc-diff-channels"
315 st,adc-channels:
356 st,adc-channels:
373 - st,adc-channels
375 - st,adc-diff-channels
406 st,adc-channels = <8>;
[all …]
H A Dadi,ad7124.yaml66 Represents the external channels which are connected to the ADC.
72 The channel number. It can have up to 8 channels on ad7124-4
73 and 16 channels on ad7124-8, numbered from 0 to 15.
89 diff-channels:
109 - diff-channels
132 diff-channels = <0 1>;
140 diff-channels = <2 3>;
148 diff-channels = <4 5>;
153 diff-channels = <6 7>;
H A Dadc.txt5 - diff-channels : Differential channels muxed for this ADC. The first value
15 diff-channels = <0 1>;
20 diff-channels = <2 3>;
H A Dcc10001_adc.txt11 - adc-reserved-channels: Bitmask of reserved channels,
12 i.e. channels that cannot be used by the OS.
18 adc-reserved-channels = <0x2>;
H A Dst,stm32-dfsdm-adc.yaml92 st,adc-channels:
168 - st,adc-channels
182 st,adc-channels:
198 io-channels:
206 - io-channels
216 st,adc-channels:
241 io-channels:
248 - io-channels
300 st,adc-channels = <1>;
309 io-channels = <&dfsdm0 0>;
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/iio/multiplexer/
H A Dio-channel-mux.txt8 - io-channels : Channel node of the parent channel that has multiplexed
14 - channels : List of strings, labeling the mux controller states.
16 For each non-empty string in the channels property, an io-channel will
18 the list of strings in the channels property, and also matches the mux
33 io-channels = <&adc 0>;
38 channels = "sync", "in", "system-regulator";
/f-stack/app/redis-5.0.5/tests/unit/
H A Dpubsub.tcl2 proc __consume_subscribe_messages {client type channels} {
19 set channels [lreplace $channels $idx $idx]
26 assert {[llength $channels] == 0}
30 proc subscribe {client channels} {
31 $client subscribe {*}$channels
35 proc unsubscribe {client {channels {}}} {
36 $client unsubscribe {*}$channels
40 proc psubscribe {client channels} {
41 $client psubscribe {*}$channels
45 proc punsubscribe {client {channels {}}} {
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/sound/
H A Dxlnx,i2s.txt12 - xlnx,num-channels: Number of I2S streams. Can be any of 1, 2, 3, 4.
13 supported channels = 2 * xlnx,num-channels
21 xlnx,num-channels = <1>;
27 xlnx,num-channels = <1>;
H A Drockchip-i2s.yaml64 rockchip,capture-channels:
68 Max capture channels, if not set, 2 channels default.
70 rockchip,playback-channels:
74 Max playback channels, if not set, 8 channels default.
111 rockchip,capture-channels = <2>;
112 rockchip,playback-channels = <8>;
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Dcros-adc-thermistors.dtsi18 io-channels = <&adc 3>;
25 io-channels = <&adc 4>;
32 io-channels = <&adc 5>;
39 io-channels = <&adc 6>;
/f-stack/freebsd/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zcu106-revA.dts65 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
69 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
73 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
77 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
81 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
85 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
89 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
93 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
97 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
101 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
[all …]
H A Dzynqmp-zcu102-revA.dts65 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
69 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
73 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
77 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
81 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
85 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
89 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
93 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
97 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
101 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/media/
H A Drenesas,drif.txt15 channels (drifn0 & drifn1). These two internal channels share the common
17 irq, dma channels, address space & clock. This internal split is not
21 The internal channels sharing the CLK & SYNC are tied together by their
26 When both internal channels are enabled they need to be managed together
29 properties of both the internal channels. This channel is identified by a
33 - When both the internal channels that are bonded together are enabled,
34 the zeroth channel is selected as primary-bond. This channels accepts
36 - When only one of the bonded channels need to be enabled, the property
54 - dmas: phandles to the DMA channels.
69 among the bonded channels.
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/timer/
H A Dnvidia,tegra30-timer.txt3 The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
4 running counter, and 5 watchdog modules. The first two channels may also
13 - interrupts : A list of 6 interrupts; one per each of timer channels 1
14 through 5, and one for the shared interrupt for the remaining channels.

12345678910>>...25