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Searched refs:cfg0 (Results 1 – 4 of 4) sorted by relevance

/f-stack/freebsd/arm64/freescale/imx/clk/
H A Dimx_clk_frac_pll.c89 uint32_t cfg0; in imx_clk_frac_pll_set_gate() local
95 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_frac_pll_set_gate()
97 cfg0 &= ~(CFG0_PD); in imx_clk_frac_pll_set_gate()
99 cfg0 |= CFG0_PD; in imx_clk_frac_pll_set_gate()
100 WRITE4(clk, sc->offset + CFG0, cfg0); in imx_clk_frac_pll_set_gate()
103 if (enable && ((cfg0 & CFG0_BYPASS) == 0)) { in imx_clk_frac_pll_set_gate()
105 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_frac_pll_set_gate()
106 if (cfg0 & CFG0_PLL_LOCK) in imx_clk_frac_pll_set_gate()
121 uint32_t cfg0, cfg1; in imx_clk_frac_pll_recalc() local
127 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_frac_pll_recalc()
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H A Dimx_clk_sscg_pll.c101 uint32_t cfg0; in imx_clk_sscg_pll_set_gate() local
107 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_sscg_pll_set_gate()
109 cfg0 &= ~(CFG0_PD); in imx_clk_sscg_pll_set_gate()
111 cfg0 |= CFG0_PD; in imx_clk_sscg_pll_set_gate()
112 WRITE4(clk, sc->offset + CFG0, cfg0); in imx_clk_sscg_pll_set_gate()
117 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_sscg_pll_set_gate()
118 if (cfg0 & CFG0_PLL_LOCK) in imx_clk_sscg_pll_set_gate()
133 uint32_t cfg0, cfg2; in imx_clk_sscg_pll_recalc() local
139 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_sscg_pll_recalc()
144 if (cfg0 & CFG0_BYPASS2) in imx_clk_sscg_pll_recalc()
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/f-stack/freebsd/mips/mips/
H A Dcpu.c100 u_int32_t cfg0; in mips_get_identity() local
118 cfg0 = mips_rd_config(); in mips_get_identity()
121 ((cfg0 & MIPS_CONFIG0_MT_MASK) >> MIPS_CONFIG0_MT_SHIFT); in mips_get_identity()
122 cpuinfo->icache_virtual = cfg0 & MIPS_CONFIG0_VI; in mips_get_identity()
125 if (!(cfg0 & MIPS_CONFIG0_M)) in mips_get_identity()
299 uint32_t cfg0, cfg1, cfg2, cfg3; in cpu_identify() local
424 cfg0 = mips_rd_config(); in cpu_identify()
426 if (!(cfg0 & MIPS_CONFIG_CM)) in cpu_identify()
/f-stack/freebsd/mips/atheros/ar531x/
H A Dar5312_chip.c121 uint32_t cfg0, cfg1; in ar5312_chip_device_start() local
125 cfg0 = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG0); in ar5312_chip_device_start()
137 printf("SDRMCTL %x %x %x %x\n", cfg0, cfg1, size0, size1); in ar5312_chip_device_start()