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/f-stack/dpdk/examples/pipeline/examples/
H A Dvxlan.spec8 bit<48> dst_addr
9 bit<48> src_addr
10 bit<16> ethertype
14 bit<8> ver_ihl
15 bit<8> diffserv
16 bit<16> total_len
19 bit<8> ttl
20 bit<8> protocol
29 bit<16> length
34 bit<8> flags
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/mfd/
H A Dmc13xxx.txt55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
86 sw1 : regulator SW1 (register 24, bit 0)
87 sw2 : regulator SW2 (register 25, bit 0)
88 sw3 : regulator SW3 (register 26, bit 0)
[all …]
/f-stack/freebsd/contrib/device-tree/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
45 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
46 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
52 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
53 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
82 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
83 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
106 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
107 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
H A Dstm32f7-rcc.h34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) argument
45 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) argument
46 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) argument
52 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) argument
53 #define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) argument
86 #define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) argument
87 #define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) argument
111 #define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) argument
112 #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) argument
H A Dstm32h7-rcc.h17 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) argument
28 #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) argument
37 #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) argument
56 #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) argument
62 #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) argument
90 #define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) argument
99 #define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) argument
118 #define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8)) argument
134 #define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8)) argument
/f-stack/app/redis-5.0.5/deps/jemalloc/include/jemalloc/internal/
H A Dbitmap.h225 bit = goff; in bitmap_set()
246 size_t bit = 0; in bitmap_ffu() local
281 return bit; in bitmap_ffu()
286 size_t bit; in bitmap_ffu() local
288 bit = ffs_lu(g); in bitmap_ffu()
289 if (bit != 0) { in bitmap_ffu()
302 size_t bit; in bitmap_sfu() local
315 bit = (bit << LG_BITMAP_GROUP_NBITS) + (ffs_lu(g) - 1); in bitmap_sfu()
324 bit = (i << LG_BITMAP_GROUP_NBITS) + (bit - 1); in bitmap_sfu()
327 return bit; in bitmap_sfu()
[all …]
/f-stack/app/nginx-1.16.1/src/core/
H A Dngx_radix_tree.c132 bit >>= 1; in ngx_radix32tree_insert()
163 bit >>= 1; in ngx_radix32tree_insert()
190 bit >>= 1; in ngx_radix32tree_delete()
259 bit >>= 1; in ngx_radix32tree_find()
277 bit = 0x80; in ngx_radix128tree_insert()
294 bit >>= 1; in ngx_radix128tree_insert()
333 bit >>= 1; in ngx_radix128tree_insert()
359 bit = 0x80; in ngx_radix128tree_delete()
370 bit >>= 1; in ngx_radix128tree_delete()
433 bit = 0x80; in ngx_radix128tree_find()
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/timer/
H A Drenesas,cmt.yaml42 - renesas,r8a7743-cmt0 # 32-bit CMT0 on RZ/G1M
43 - renesas,r8a7744-cmt0 # 32-bit CMT0 on RZ/G1N
44 - renesas,r8a7745-cmt0 # 32-bit CMT0 on RZ/G1E
45 - renesas,r8a77470-cmt0 # 32-bit CMT0 on RZ/G1C
56 - renesas,r8a7743-cmt1 # 48-bit CMT1 on RZ/G1M
57 - renesas,r8a7744-cmt1 # 48-bit CMT1 on RZ/G1N
58 - renesas,r8a7745-cmt1 # 48-bit CMT1 on RZ/G1E
59 - renesas,r8a77470-cmt1 # 48-bit CMT1 on RZ/G1C
83 - renesas,r8a774a1-cmt1 # 48-bit CMT on RZ/G2M
84 - renesas,r8a774b1-cmt1 # 48-bit CMT on RZ/G2N
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/
H A Dtrivial-devices.yaml127 # mCube 3-axis 8-bit digital accelerometer
129 # MEMSIC 2-axis 8-bit digital accelerometer
131 # Microchip 7-bit Single I2C Digital POT (5k)
133 # Microchip 7-bit Single I2C Digital POT (10k)
135 # Microchip 7-bit Single I2C Digital POT (50k)
139 # Microchip 7-bit Single I2C Digital POT (5k)
141 # Microchip 7-bit Single I2C Digital POT (10k)
143 # Microchip 7-bit Single I2C Digital POT (50k)
147 # Microchip 7-bit Single I2C Digital POT (5k)
333 # 8-Channels, 12-bit ADC
[all …]
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Domap24xx-clocks.dtsi12 ti,bit-shift = <2>;
26 ti,bit-shift = <6>;
78 ti,bit-shift = <23>;
94 ti,bit-shift = <6>;
103 ti,bit-shift = <6>;
132 ti,bit-shift = <2>;
142 ti,bit-shift = <6>;
152 ti,bit-shift = <5>;
180 ti,bit-shift = <3>;
196 ti,bit-shift = <7>;
[all …]
H A Domap3xxx-clocks.dtsi25 ti,bit-shift = <6>;
36 ti,bit-shift = <7>;
85 ti,bit-shift = <4>;
99 ti,bit-shift = <2>;
113 ti,bit-shift = <6>;
140 ti,bit-shift = <2>;
245 ti,bit-shift = <16>;
352 ti,bit-shift = <6>;
360 ti,bit-shift = <8>;
387 ti,bit-shift = <5>;
[all …]
H A Domap2430-clocks.dtsi26 ti,bit-shift = <2>;
40 ti,bit-shift = <4>;
56 ti,bit-shift = <0>;
64 ti,bit-shift = <5>;
80 ti,bit-shift = <0>;
102 ti,bit-shift = <1>;
110 ti,bit-shift = <3>;
118 ti,bit-shift = <3>;
126 ti,bit-shift = <4>;
134 ti,bit-shift = <4>;
[all …]
H A Domap34xx-omap36xx-clocks.dtsi20 ti,bit-shift = <3>;
29 ti,bit-shift = <2>;
37 ti,bit-shift = <1>;
45 ti,bit-shift = <0>;
52 ti,bit-shift = <0>;
62 ti,bit-shift = <0>;
70 ti,bit-shift = <1>;
86 ti,bit-shift = <4>;
118 ti,bit-shift = <7>;
134 ti,bit-shift = <6>;
[all …]
H A Domap2420-clocks.dtsi13 ti,bit-shift = <15>;
21 ti,bit-shift = <8>;
35 ti,bit-shift = <11>;
45 ti,bit-shift = <1>;
53 ti,bit-shift = <5>;
69 ti,bit-shift = <10>;
77 ti,bit-shift = <8>;
100 ti,bit-shift = <8>;
108 ti,bit-shift = <28>;
172 ti,bit-shift = <3>;
[all …]
H A Domap36xx-clocks.dtsi19 ti,bit-shift = <0x1e>;
22 ti,set-bit-to-disable;
29 ti,bit-shift = <0x1b>;
31 ti,set-bit-to-disable;
38 ti,bit-shift = <0xc>;
40 ti,set-bit-to-disable;
47 ti,bit-shift = <0x1c>;
49 ti,set-bit-to-disable;
56 ti,bit-shift = <0x1f>;
58 ti,set-bit-to-disable;
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/crypto/
H A Dfsl-sec2.txt20 bit 0 = reserved - should be 0
21 bit 1 = set if SEC has the ARC4 EU (AFEU)
22 bit 2 = set if SEC has the DES/3DES EU (DEU)
23 bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
24 bit 4 = set if SEC has the random number generator EU (RNG)
25 bit 5 = set if SEC has the public key EU (PKEU)
26 bit 6 = set if SEC has the AES EU (AESU)
27 bit 7 = set if SEC has the Kasumi EU (KEU)
28 bit 8 = set if SEC has the CRC EU (CRCU)
39 bit 1 = set if SEC supports the ipsec_esp descriptor type
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/gpio/
H A Dgpio-74xx-mmio.txt5 "ti,741g125": for 741G125 (1-bit Input),
6 "ti,741g174": for 741G74 (1-bit Output),
7 "ti,742g125": for 742G125 (2-bit Input),
8 "ti,7474" : for 7474 (2-bit Output),
9 "ti,74125" : for 74125 (4-bit Input),
10 "ti,74175" : for 74175 (4-bit Output),
11 "ti,74365" : for 74365 (6-bit Input),
12 "ti,74174" : for 74174 (6-bit Output),
13 "ti,74244" : for 74244 (8-bit Input),
14 "ti,74273" : for 74273 (8-bit Output),
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/powerpc/
H A Dibm,powerpc-cpu-features.txt107 If bit 0 is set, then the hwcap-bit-nr property will exist.
125 If the HFSCR bit is set, then the hfscr-bit-nr property will exist and
144 If the FSCR bit is set, then the fscr-bit-nr property will exist and
148 - hfscr-bit-nr
161 - fscr-bit-nr
174 - hwcap-bit-nr
214 hwcap-bit-nr = <xx>;
221 hwcap-bit-nr = <xx>;
236 hwcap-bit-nr = <xx>;
243 fscr-bit-nr = <xx>;
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/regulator/
H A Danatop-regulator.yaml25 anatop-vol-bit-shift:
29 anatop-vol-bit-width:
33 anatop-min-bit-val:
49 anatop-delay-bit-shift:
53 anatop-delay-bit-width:
57 anatop-enable-bit:
69 - anatop-vol-bit-shift
70 - anatop-vol-bit-width
71 - anatop-min-bit-val
86 anatop-vol-bit-shift = <9>;
[all …]
/f-stack/freebsd/i386/i386/
H A Dgeode.c103 int bit; in led_func() local
105 bit = *(int *)ptr; in led_func()
106 if (bit < 0) { in led_func()
107 bit = -bit; in led_func()
113 u |= 1 << bit; in led_func()
115 u &= ~(1 << bit); in led_func()
122 int bit; in cs5536_led_func() local
126 if (bit < 0) { in cs5536_led_func()
127 bit = -bit; in cs5536_led_func()
132 if (bit >= 16) { in cs5536_led_func()
[all …]
/f-stack/freebsd/contrib/openzfs/config/
H A Dhost-cpu-c-abi.m424 dnl contains 32-bit instructions, whereas 'sparc64' code contains 64-bit
66 # - 64-bit instruction set, 64-bit pointers, 64-bit 'long': x86_64.
67 # - 64-bit instruction set, 64-bit pointers, 32-bit 'long': x86_64
69 # - 64-bit instruction set, 32-bit pointers, 32-bit 'long': x86_64-x32.
70 # - 32-bit instruction set, 32-bit pointers, 32-bit 'long': i386.
105 # - 32-bit instruction set, 32-bit pointers, 32-bit 'long': arm or armhf.
485 # - 64-bit instruction set, 64-bit pointers, 64-bit 'long': x86_64.
486 # - 64-bit instruction set, 64-bit pointers, 32-bit 'long': x86_64
488 # - 64-bit instruction set, 32-bit pointers, 32-bit 'long': x86_64-x32.
489 # - 32-bit instruction set, 32-bit pointers, 32-bit 'long': i386.
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/dma/
H A Dst,stm32-mdma.yaml22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
31 0x0: byte (8bit)
32 0x1: half-word (16bit)
33 0x2: word (32bit)
34 0x3: double-word (64bit)
36 0x0: byte (8bit)
37 0x1: half-word (16bit)
38 0x2: word (32bit)
39 0x3: double-word (64bit)
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/leds/
H A Dregister-bit-led.txt3 Register bit leds are used with syscon multifunctional devices
16 - compatible : must be "register-bit-led"
18 - mask : bit mask for the bit controlling this LED in the register
36 compatible = "register-bit-led";
44 compatible = "register-bit-led";
52 compatible = "register-bit-led";
60 compatible = "register-bit-led";
67 compatible = "register-bit-led";
74 compatible = "register-bit-led";
81 compatible = "register-bit-led";
[all …]
/f-stack/freebsd/contrib/octeon-sdk/
H A Dcvmx-interrupt.c384 int bit; in __cvmx_interrupt_ciu() local
392 bit = 63 - bit; in __cvmx_interrupt_ciu()
396 int bit; in __cvmx_interrupt_ciu() local
399 bit = 63 - bit; in __cvmx_interrupt_ciu()
401 if (bit <= 9 && bit >= 4) { in __cvmx_interrupt_ciu()
432 bit = 63 - bit; in __cvmx_interrupt_ciu()
467 int bit; in __cvmx_interrupt_ciu_cn61xx() local
472 bit = 63 - bit; in __cvmx_interrupt_ciu_cn61xx()
473 if (bit >= 0) { in __cvmx_interrupt_ciu_cn61xx()
724 if (bit < 0) in __cvmx_interrupt_ciu2_mask_unmask_irq()
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/media/i2c/
H A Dtda1997x.txt6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
17 - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
21 The Video port output pins are mapped via 4-bit 'pin groups' allowing
57 - VP[15:0] connected to IMX6 CSI_DATA[19:4] for 16bit YUV422
58 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
99 - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
100 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
141 - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
[all …]

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