| /f-stack/freebsd/arm/nvidia/tegra124/ |
| H A D | tegra124_clk_super.c | 49 uint32_t base_reg; member
63 .base_reg = r, \
100 uint32_t base_reg; member
162 RD4(sc, sc->base_reg, ®); in super_mux_init()
200 RD4(sc, sc->base_reg, ®); in super_mux_set_mux()
213 WR4(sc, sc->base_reg, reg); in super_mux_set_mux()
214 RD4(sc, sc->base_reg, &dummy); in super_mux_set_mux()
217 WR4(sc, sc->base_reg, reg); in super_mux_set_mux()
224 WR4(sc, sc->base_reg, reg); in super_mux_set_mux()
225 RD4(sc, sc->base_reg, &dummy); in super_mux_set_mux()
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| H A D | tegra124_clk_pll.c | 108 uint32_t base_reg; member
223 .base_reg = PLLM_BASE,
234 .base_reg = PLLX_BASE,
247 .base_reg = PLLC_BASE,
295 .base_reg = PLLP_BASE,
305 .base_reg = PLLA_BASE,
315 .base_reg = PLLU_BASE,
326 .base_reg = PLLD_BASE,
362 .base_reg = PLLE_BASE,
391 uint32_t base_reg; member
[all …]
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| H A D | tegra124_clk_per.c | 64 uint32_t base_reg; member
400 .base_reg = r, \
525 uint32_t base_reg; member
559 RD4(sc, sc->base_reg, ®); in periph_init()
599 RD4(sc, sc->base_reg, ®); in periph_set_mux()
614 WR4(sc, sc->base_reg, reg); in periph_set_mux()
630 RD4(sc, sc->base_reg, ®); in periph_recalc()
686 sc->base_reg = clkdef->base_reg; in periph_register()
758 uint32_t reg, mask, base_reg; in pgate_set_gate() local
763 base_reg = get_enable_reg(sc->idx); in pgate_set_gate()
[all …]
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| /f-stack/freebsd/arm64/nvidia/tegra210/ |
| H A D | tegra210_clk_super.c | 47 uint32_t base_reg; member
59 .base_reg = r, \
93 uint32_t base_reg; member
152 RD4(sc, sc->base_reg, ®); in super_mux_init()
180 RD4(sc, sc->base_reg, ®); in super_mux_set_mux()
193 WR4(sc, sc->base_reg, reg); in super_mux_set_mux()
194 RD4(sc, sc->base_reg, &dummy); in super_mux_set_mux()
213 sc->base_reg = clkdef->base_reg; in super_mux_register()
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| H A D | tegra210_clk_pll.c | 135 uint32_t base_reg; member
277 .base_reg = PLLM_BASE,
301 .base_reg = PLLX_BASE,
313 .base_reg = PLLC_BASE,
364 .base_reg = PLLP_BASE,
375 .base_reg = PLLA_BASE,
399 .base_reg = PLLU_BASE,
412 .base_reg = PLLD_BASE,
449 .base_reg = PLLE_BASE,
577 uint32_t base_reg; member
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| H A D | tegra210_clk_per.c | 59 uint32_t base_reg; member
509 .base_reg = r, \
638 uint32_t base_reg; member
672 RD4(sc, sc->base_reg, ®); in periph_init()
713 RD4(sc, sc->base_reg, ®); in periph_set_mux()
728 WR4(sc, sc->base_reg, reg); in periph_set_mux()
744 RD4(sc, sc->base_reg, ®); in periph_recalc()
800 sc->base_reg = clkdef->base_reg; in periph_register()
872 uint32_t reg, mask, base_reg; in pgate_set_gate() local
877 base_reg = get_enable_reg(sc->idx); in pgate_set_gate()
[all …]
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| /f-stack/dpdk/drivers/net/axgbe/ |
| H A D | axgbe_regs.h | 177 unsigned int base_reg, reg; in axgbe_regs_dump() local
183 base_reg = DMA_CH_BASE + (j * DMA_CH_INC); in axgbe_regs_dump()
185 reg = base_reg + dma_txch_reg_tbl[i]; in axgbe_regs_dump()
191 base_reg = DMA_CH_BASE + (j * DMA_CH_INC); in axgbe_regs_dump()
193 reg = base_reg + dma_rxch_reg_tbl[i]; in axgbe_regs_dump()
202 base_reg = MTL_Q_BASE + (j * MTL_Q_INC); in axgbe_regs_dump()
204 reg = base_reg + mtl_txq_reg_tbl[i]; in axgbe_regs_dump()
210 base_reg = MTL_Q_BASE + (j * MTL_Q_INC); in axgbe_regs_dump()
212 reg = base_reg + mtl_rxq_reg_tbl[i]; in axgbe_regs_dump()
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| /f-stack/dpdk/drivers/net/bnx2x/ |
| H A D | ecore_init_ops.h | 810 uint32_t base_reg, uint32_t reg) in ecore_qm_set_ptr_table() argument
815 REG_WR(sc, base_reg + i*4, in ecore_qm_set_ptr_table()
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